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S.K.P.

Engineering College, Tiruvannamalai VI SEM

SKP Engineering College


Tiruvannamalai – 606611

A Course Material
on
Embedded Systems

By

V.Suresh
Assistant Professor
Electrical and Electronics Engineering Department

Electrical and Electronics Engineering Department 1 Embedded Systems


S.K.P. Engineering College, Tiruvannamalai VI SEM

Quality Certificate

This is to Certify that the Electronic Study Material

Subject Code: EE 6602

Subject Name:Embedded Systems

Year/Sem:III/VI

Being prepared by me and it meets the knowledge requirement of the University


curriculum.

Signature of the Author

Name: V.Suresh

Designation: Assistant Professor

This is to certify that the course material being prepared by Mr.V.Suresh is of the
adequate quality. He has referred more than five books and one among them is from
abroad author.

Signature of HD Signature of the Principal

Name: Mrs.R.Sridevi Name: Dr.V.Subramania Bharathi

Seal: Seal:

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EE6602 EMBEDDED SYSTEMS LT P C3 0 0 3

OBJECTIVES:
To introduce the Building Blocks of Embedded System
To Educate in Various Embedded Development Strategies
To Introduce Bus Communication in processors, Input/output interfacing.
To impart knowledge in Various processor scheduling algorithms.
To introduce Basics of Real time operating system and example tutorials to discuss on one
realtimeoperating system tool

UNIT I INTRODUCTION TO EMBEDDED SYSTEMS 9


Introduction to Embedded Systems – The build process for embedded systems- Structural units
in Embedded processor , selection of processor & memory devices- DMA – Memory
management methods- Timer and Counting devices, Watchdog Timer, Real Time Clock, In
circuit emulator, Target Hardware Debugging.

UNIT II EMBEDDED NETWORKING 9


Embedded Networking: Introduction, I/O Device Ports & Buses– Serial Bus communication
protocols -RS232 standard – RS422 – RS485 - CAN Bus -Serial Peripheral Interface (SPI) –
Inter Integrated Circuits (I2C) –need for device drivers.

UNIT III EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT 9


Embedded Product Development Life Cycle- objectives, different phases of EDLC, Modelling of
EDLC; issues in Hardware-software Co-design, Data Flow Graph, state machine model,
Sequential Program Model, concurrent Model, object oriented Model.

UNIT IV RTOS BASED EMBEDDED SYSTEM DESIGN 9


Introduction to basic concepts of RTOS- Task, process & threads, interrupt routines in RTOS,
Multiprocessing and Multitasking, Preemptive and non-preemptive scheduling, Task
communication shared memory, message passing-, Inter process Communication –
synchronization between processes-semaphores, Mailbox, pipes, priority inversion, priority
inheritance, comparison of Real time Operating systems: Vx Works, чC/OS-II, RT Linux.

UNIT V EMBEDDED SYSTEM APPLICATION DEVELOPMENT 9


Case Study of Washing Machine- Automotive Application- Smart card System Application.

TOTAL: 45 PERIODS

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OUTCOMES:
Ability to understand and analyse, linear and digital electronic circuits.
TEXT BOOKS:
1. Rajkamal, ‘Embedded System-Architecture, Programming, Design’, Mc Graw Hill, 2013.
2. Peckol, “Embedded system Design”, John Wiley & Sons,2010
3. Lyla B Das,” Embedded Systems-An Integrated Approach”, Pearson, 2013
REFERENCES:
1. Shibu. K.V, “Introduction to Embedded Systems”, Tata Mcgraw Hill,2009.
2. Elicia White,” Making Embedded Systems”, O’ Reilly Series,SPD,2011.
3. Tammy Noergaard, “Embedded Systems Architecture”, Elsevier, 2006.
4. Han-Way Huang, ”Embedded system Design Using C8051”, Cengage Learning,2009.
5. Rajib Mall “Real-Time systems Theory and Practice” Pearson Education, 2007.

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CONTENTS

S.No Particulars Page

1 Unit – I 6

2 Unit – II 36

3 Unit – III 63

4 Unit – IV 76

5 Unit – V 105

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Unit – I

Introduction To Embedded Systems


Part – A

1. How embedded systems are different from conventional PC?


(CO1-L1- April/may 2016)
The difference between an embedded system and a general purpose computer
system is one of purpose, and to a much lesser extent, design. While a general purpose
system can be used for many things, an embedded system is only meant for one
purpose.

2. What are the different types of memory used in embedded system design?
(CO1-L1)
 Volatile Memory Module – RAM
 Non- Volatile Memory-ROM Memory

3. What are the steps involved in the build process? (CO1-L1- April/may 2016)

4. Differentiate between editor and compiler. (CO1-L2)


A Compiler is computer program which transforms the code written in the programming
language to computer language (binary form). An IDE is short for Integrated
Development Environment. ...
Editor: application that allows for the creation of a text-based file.

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5. Decide how suitable memory will be selected for the design of the embedded
system? (CO1-H2)
Selection of suitable memory is very much essential step in high performance
applications, because the challenges and limitations of the system performance are
often decided upon the type of memory architecture. Systems memory requirement
depend primarily on the nature of the application that is planned to run on the system.
Memory performance and capacity requirement for low cost systems are small, whereas
memory throughput can be the most critical requirement in a complex, high
performance system. Following are the factors that are to be considered while selecting
the memory devices,

 Speed
 Data storage size and capacity
 Bus width
 Latency
 Power consumption
 Cost

6. Assess the additional structural units in advanced embedded processor?


(CO1-H2)
 Instruction, Branch Target and Data Cache
 Memory-Management unit (MMU)
 Floating Point Processing unit
 System Register Set
 Floating Point Register Set
 Pre-fetch Control Unit for data into the Iand D-caches
 Instruction level parallelism units (i) multistage pipeline (ii) Multi-line superscalar
Processing

7. What are the different modes of DMA transfer? Which one is suitable for
embedded system? (CO1-L1)
 Single transfer at a time and then release of the hold on the system bus.
 Burst transfer at a time and then release of the hold on the system bus. A burst
may be of a few kB.
 Bulk transfer and then release of the hold on the system bus after the transfer is
completed. Most suitable

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8. List out the states of timer? (CO1-L1)


There are eleven states as follows
Reset state
Idle state
Present state
Over flow state
Over run state
Running state
Reset enabled state / disabled
Finished state
Load enabled / disabled
Auto reload enabled / disabled
Service routine execution enabled / disabled

9. How does a program reside in ROM in embedded systems?(CO1-L3)


Embedded systems typically do not have loaders, and instead the code executes
directly from ROM. In order to load the operating system itself, as part of booting, a
specialized boot loader is used.

10. Define Real Time Clock (RTC)? (CO1-L3)


A clock that continuously generate interrupts at regular interval endlessly. An RTC
interrupt ticks the other timer of the system.

11. Why do we need at least one timer in an ES? (CO1-H2)


The embedded system needs at least one timer device. It is used as a system clock.

12. What is an embedded system? (CO1-L1)


An embedded system employs a combination of hardware & software (a
"computational engine") to perform a specific function; is part of a larger system
that may not be a "computer"; works in a reactive and time-constrained
environment

13. What are the typical characteristics of an embedded system? (CO1-L1)


Typical characteristics:
 Perform a single or tightly knit set of functions;
 Increasingly high-performance & real-time constrained;

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 Power, cost and reliability are often important attributes that influence
design;
 Application specific processor design can be a significant component of
some
 embedded systems.
Other characteristics:
• Application specific
• Digital signal processing in ECS
• Reactive
• Real-time
• Distributed

14. What are the advantages of embedded system? (CO1-L1)


Customization yields lower area, power, cost, etc.,

15. What are the disadvantages of embedded system? (CO1-L1)


Higher HW/software development overhead design, compilers, debuggers, etc.,
may result in delayed time to market.

16. What are the applications of an embedded system? (CO1-L1)


Embedded Systems: Applications:
• Consumer electronics, e.g., cameras, camcorders, etc.,
• Consumer products, e.g., washers, microwave ovens, etc.,
• Automobiles (anti-lock braking, engine control, etc.,)
• Industrial process controllers & avionics/defense applications
• Computer/Communication products, e.g., printers, FAX machines, etc.,
• Emerging multimedia applications & consumer electronics

17. What are the complicating factors in embedded design? (CO1-H1)


Complicating factors in the design of embedded systems
• Many of the subtasks in design are intertwined.
• Allocation depends on the partitioning, and scheduling presumes a certain
allocation.
• Predicting the time for implementing the modules in hardware or software is not
very easy, particularly for tasks that have not been performed before.

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18. What are the real-time requirements of an embedded system? (CO1-H1)


Hard-real time systems: where there is a high penalty for missing a deadline e.g.,
control systems for aircraft/space probes/nuclear reactors; refresh rates for video,
or DRAM. Soft real time systems: where there is a steadily increasing penalty if a
deadline is missed. e.g., laser printer: rated by pages-per-minute, but can take
differing times to print a page (depending on the \"complexity\" of the page) without
harming the machine or the customer.

19. What are the functional requirements of embedded system? (CO1-L1)


Data Collection
• Sensor requirements
• Signal conditioning
• Alarm monitoring Direct Digital Control
• Actuators Man-Machine Interaction
• Informs the operator of the current state of the controlled object
• Assists the operator in controlling the system.

20. What are the main components of an embedded system? (CO1-L1)


Three main components of embedded systems:
1. The Hardware
2. Application Software
3. RTOS

21. Define embedded microcontroller. (CO1-L1)


An embedded microcontroller is particularly suited for embedded applications to
perform dedicated task or operation. Example: 68HC11xx, 8051, PIC, 16F877, etc.

22. What are the various classifications of embedded systems? (CO1-L1)


1. Small scale embedded systems
2. Medium scale embedded systems
3. Sophisticated embedded systems

23. What are the two essential units of a processor on an embedded system?
(CO1-L1)
1. Program flow control unit (CU)
2. Execution unit (EU)

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24. What does the execution unit of a processor in an embedded system do?
(CO1-L1)
The execution unit implements data transfer and data conversion. It includes
ALU and circuits that execute instruction for jump, interrupt, etc.,

25. Give examples for general purpose processor. (CO1-L1)


1. Microprocessor
2. Microcontroller
3. Embedded processor
4. Digital Signal Processor
5. Media Processor

26. Define ROM image. (CO1-L1)


ROM image in a system memory consists of:Boot-up program, stack address
pointer, program counter address pointer, application tasks, ISRs, input data, RTOS
and vector addresses.Bytes at each address must be defined to create ROM image.

27. Define device driver. (CO1-L1)


A device driver is software for controlling, reading, sending a byte of stream of
bytes from/to the device.

28. Give some examples for small scale embedded systems. (CO1-L1)
68HC05, PIC 16F8x, 8051, etc.,

29. Give some examples for medium scale embedded systems. (CO1-L1)
8051, 80251, 80x86, 80196,68HC11xx

30. Give some examples for sophisticated embedded systems. (CO1-L1)


ARM7, Power PC, Intel 80960,

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Part – B

1.Describe the memory management concepts in embedded system design.


(CO1-L1- APRIL/MAY 2016)

Memories are used to store primarily two kinds of information – Program


and data.

Program information are the instructions i.e. opcodes that are to be


executed by the processor. Generally they are stored in a non-volatile memory
that is mapped directly to the address space of the processor. Or they might be
stored in external memories (say as files in a partition) and loaded on to a
volatile memory just prior to execution of the program.

Data memory can be used to store primarily two kind of information. One
is relating to the intermediate data being processed- for e.g. a variable storing a
value during course of execution of an algorithm or a Process Control Block in
an OS etc. The other is the Stack which is used by the processor to store its
return functions and local variables. In either case the memory type is volatile.

Selection of suitable memory is very much essential step in high


performance applications, because the challenges and limitations of the system
performance are often decided upon the type of memory architecture.Systems
memory requirement depend primarily on the nature of the application that is
planned to run on the system. Memory performance and capacity requirement
for low cost systems are small, whereas memory throughput can be the most
critical requirement in a complex, high performance system.

Following are the factors that are to be considered while selecting the memory
devices,

 Speed
 Data storage size and capacity

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 Bus width
 Latency
 Power consumption
 Cost

SRAM’s have lower data storage and capacity hence they are suitable for lower
end systems where as SDRAM for higher end systems with complex
requirements.

Among the high speed types of SDRAM, DDR2 memory modules can have
memory capacities from 256MB to 4GB capacities. Most of the DDR2 memory
chips come in FBGA (Fine Ball Grid Array) package. The package allows higher
memory densities in smaller space with better electrical properties. DDR2
memory uses 1.8V for power, resulting in lower power and cooler operation,
whereas the DDR uses 2.5V.

Further there are variations of DDR available that are fine tuned for particular
applications. For example, the Graphic DDR (GDDR) memory is designed for
higher performance than the standard DDR memory. To achieve this, they
operate at additional voltage of 2.0V. But the capacity of GDDR memory devices
in comparison to DDR tends to be reduced typically from 256Mb to 512Mb. This
enables them to be used in resource intensive video cards. On the other end of
the spectrum, Mobile DDR (MDDR) memory devices are optimized for low
power applications such as battery operated and handheld devices. In deep
power down (DPD) mode of operation, their current can go as low as 10uA.

The data rates are defined by the RAM manufacturer and are based on various
factors such as CAS latency, RAS-CAS delay etc. Even a increase of 0.5 cycle,
can impact a change of up to 10% of speed.

Again, these high speed varieties of SDRAM needs careful PCB layout with
signal integrity considerations including presence of suitable terminations.

Obviously a 32-bit width memory can fetch more data in a same cycle as a 16
bit memory. Thus more the data width, better the transfer rate, provided the data
line support is available.

Another factor, when going for non-volatile programmable storage, is deciding


the programming model. For example, it could be ISP (In-System Programming)

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that allows programming the flash but needs the application to be stopped at
that time. Or it could be IAP (In-Application Programming) that will allow re-
programming of the memory even when the application firmware is running. This
is determined by the memory architecture. Nowadays many microcontrollers
support both the options and ISP is used for manufacturing and IAP is
appropriate for field updates.

Though nowadays the memory controllers available in the SoC primarily dictate
the selection of the memory devices, we believe this blog provides a good
insight about various memory technologies, their application and selection. In
the next blog, we will analyze about the power supply design in an embedded
system.

2. Quote in brief about the various steps involved in the Embedded System build
process. (CO1-L2- APRIL/MAY 2016)

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When build tools run on the same system as the program they produce,
they can make a lot of assumptions about the system. This is typically not the
case in embedded software development, where the build tools run on a host
computer that differs from the target hardware platform. There are a lot of things
that software development tools can do automatically when the target platform is
well defined. [1] This automation is possible because the tools can exploit
features of the hardware and operating system on which your program will
execute. For example, if all of your programs will be executed on IBM-
compatible PCs running Windows, your compiler can automate—and, therefore,
hide from your view—certain aspects of the software build process. Embedded
software development tools, on the other hand, can rarely make assumptions
about the target platform. Instead, the user must provide some of her own
knowledge of the system to the tools by giving them more explicit instructions.

The process of converting the source code representation of your embedded


software into an executable binary image involves three distinct steps:

1. Each of the source files must be compiled or assembled into an object file.
2. All of the object files that result from the first step must be linked together
to produce a single object file, called the relocatable program.
3. Physical memory addresses must be assigned to the relative offsets within
the relocatable program in a process called relocation.

The result of the final step is a file containing an executable binary image that is
ready to run on the embedded system.The embedded software development
process just described is illustrated in Figure In this figure, the three steps are
shown from top to bottom, with the tools that perform the steps shown in boxes
that have rounded corners. Each of these development tools takes one or more
files as input and produces a single output file. More specific information about
these tools and the files they produce is provided in the sections that follow.

3. List and explain the various hardware units that must be present in the
embedded systems. (CO1-L1)

Program Flow and data path ControlUnit (CU) —includes a fetch


unit forfetching instructions from thememory
Execution Unit (EU) —includescircuits for arithmetic and logical
unit

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(ALU), and for instructions for aprogram control task, say, datatransfer
instructions, halt, interrupt,or jump to another set of instructionsor call
to another routine or sleep orreset

1a. General purpose microprocessor


For example, Intel 80x86, Sparc, orMotorola 68HCxxx

PROCESSOR IN EMBEDDED SYSTEM

Fig: Typical Embedded System Hardware Unit.

1b. Embedded general purpose processor


Fast context switching features,use of on-chip Compilers, forexample,
Intel® XScale™ Applications Personal Internet ClientArchitecture-based PDAs,
cell phonesand other wireless devices.
2. Application Specific Instruction-Set Processor (ASIP)
(a) Microcontroller — Intel, Motorola,Hitachi, TI, Philips and ARM,for

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example, an Intel® MCS51, Philips®51XA, 51MX, orMotorola — 68HC11,


68HC12, 68HC16
(b) Media processor TI DSP TMS320DM310 or TrimediaPhillips
Media Processor 1x00series for Processing Streaming Networks and Image,
Video and Speech: PNX 1300, PNX 1500(2002)
(c) IO processor or
(d) Network processor or
(e) A domain specific processor
3. GPP or ASIP core (s)
GPP or ASIP integrated into either an Application Specific Integrated
Circuit(ASIC), or a Very Large Scale Integrated Circuit (VLSI) circuit or a
FPGA core integrated with processor unit(s) in a VLSI (ASIC) chip
4. Application Specific System Processor (ASSP)
Typically a set top box processor or mpeg video-processor or network
application processor or mobile application processor
5. Single purpose processor or Application Specific Instruction processor
• Floating point Coprocessor
• CCD Pixel coprocessor and imagecodec in digital camera
• Graphic processor
• Speech processor
• Adaptive filtering processor Encryption engine
• Decryption engine
• Communication protocol stack processor
• Java accelerator Examples Java Accelerator Nazonin
Communications Java codes run 15 to60 Times fast, Video
Accelerator for fast Video Processing
6. Multi core processors or multiprocessor system using GPPs
Examples
• Multiprocessor system for Real time performance in a video-
conference system,
• Embedded firewall cum router, High-end cell phone.

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4. Explain how the processor is Selected in Embedded Systems. (CO1-L2)

The first and foremost consideration in selecting the processor is its


performance. The performance speed of a processor is dependent primarily on
its architecture and its silicon design. Evolution of fabrication techniques helped
packing more transistors in same area there by reducing the propagation delay.
Also presence of cache reduces instruction/data fetch timing. Pipelining and
super-scalar architectures further improves the performance of the processor.
Branch prediction, speculative execution etc are some other techniques used for
improving the execution rate. Multi-cores are the new direction in improving the
performance.

Rather than simply stating the clock frequency of the processor which has
limited significance to its processing power, it makes more sense to describe the
capability in a standard notation. MIPS (Million Instructions Per Second) or
MIPS/MHz was an earlier notation followed by Dhrystones and latest EEMBC’s

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CoreMark. CoreMark is one of the best ways to compare the performance of


various processors.

Processor architectures with support for extra instruction can help improving
performance for specific applications. For example, SIMD (Single
Instruction/Multiple Data) set and Jazelle – Java acceleration can help in
improving multimedia and JVM execution speeds.

So size of cache, processor architecture, instruction set etc has to be taken in to


account when comparing the performance.

Power Considerations

Increasing the logic density and clock speed has adverse impact on power
requirement of the processor. A higher clock implies faster charge and
discharge cycles leading to more power consumption. More logic leads to higher
power density there by making the heat dissipation difficult. Further with more
emphasis on greener technologies and many systems becoming battery
operated, it is important the design is for optimal power usage.

Techniques like frequency scaling – reducing the clock frequency of the


processor depending on the load, voltage scaling – varying the voltage based
on load can help in achieving lower power usage. Further asymmetric
multiprocessors, under near idle conditions, can effectively power off the more
powerful core and load the less powerful core for performing the tasks. SoC
comes with advanced power gating techniques that can shut down clocks and
power to unused modules.

Peripheral Set

Every system design needs, apart from the processor, many other peripherals
for input and output operations. Since in an embedded system, almost all the
processors used are SoCs, it is better if the necessary peripherals are available
in the chip itself. This offers various benefits compared to peripherals in external
IC’s such as optimal power architecture, effective data communication using
DMA, lower BoM etc. So it is important to have peripheral set in consideration
when selecting the processor.

Operating Voltages

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Each and every processor will have its own operating voltage condition. The
operating voltage maximum and minimum ratings will be provided in the
respective data sheet or user manual.

While higher end processors typically operate with 2 to 5 voltages including 1.8V
for Cores/Analogue domains, 3.3V for IO lines, needs specialized PMIC
devices, it is a deciding factor in low end micro-controllers based on the input
voltage. For example it is cheaper to work with a 5V micro-controller when the
input supply is 5V and a 3.3 micro-controllers when operated with Li-on
batteries.

Specialized Processing

Apart from the core, presence of various co-processors and specialized


processing units can help achieving necessary processing performance. Co-
processors execute the instructions fetched by the primary processor thereby
reducing the load on the primary. Some of the popular co-processors include

Floating Point Co-processor:

RISC cores supports primarily integer only instruction set. Hence presence of a
FP co-processor can be very helpful in application involving complex
mathematical operations including multimedia, imaging, codecs, signal
processing etc.

Graphic Processing Unit:

GPU(Graphic Processing Unit) also called as Visual processing unit is


responsible for drawing images on the frame buffer memory to be displayed.
Since human visual perception needed at-least 16 Frames per second for a
smooth viewing, drawing for HD displays involves a lot of data bandwidth. Also
with increasing graphic requirements such as textures, lighting shaders etc,
GPU’s have become a mandatory requirements for mobile phones, gaming
consoles etc.

Various GPU’s like ARM’s MALI, PowerVX, OpenGL etc are increasing
available in higher end processors. Choosing the right co-processor can enable
smooth design of the embedded application.

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Digital Signal Processors

DSP is a processor designed specifically for signal processing


applications. Its architecture supports processing of multiple data in parallel. It
can manipulate real time signal and convert to other domains for processing.
DSP’s are either available as the part of the SoC or separate in an external
package. DSP’s are very helpful in multimedia applications. It is possible to use
a DSP along with a processor or use the DSP as the main processor itself.

Price

Various considerations discussed above can be taken in to account when


a processor is being selected for an embedded design. It is better to have some
extra buffer in processing capacities to enable enhancements in functionality
without going for a major change in the design. While engineers (especially
software/firmware engineers) will want to have all the functionalities, price will be
the determining factor when designing the system and choosing the right
processor.In the upcoming blog, we will discuss about various memory
technologies and factors to be considered when selecting them.

5. Summarize the various form of memories present in an embedded system.


(CO1-L2)

The primary differentiation of the memory is based on the volatility i.e.


whether the stored data is retained after power cycling the device. Accordingly,
the memory can be either Volatile memory or a non-volatile memory.

Volatile memory

Volatile memories can hold their contents only when power is continuously
applied to the memory devices. As soon as the power is removed, the contents
in the memories are lost. The primary usage is to store the data/stack as well as
storing the program instructions.

Examples of volatile memories include static RAM, dynamic RAM and static
dynamic RAM.

Generally the volatile memories used are of type Random Access Memory
(RAM) i.e. data at any address in the memory can be accessed by giving the

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address in the address bus of the memory. Primarily the volatile memory is
divided in to two types:

SRAM – Static Random Access Memory

The static RAM is a type of memory that uses bi-stable latching circuitry to store
each bit. Due to the design, the memories need not be refreshed. Thus the data
stored will be static till the duration of power being applied to the RAM.

The primary advantage of SRAM is its speed. Fast SRAMs can operate on par
with the processor speed enabling access times equal to a clock cycle used by
the microprocessor. Synchronous SRAMs are the preferred way of
implementing Instruction and Data caches in a processor system. Further since
there is no need for specialized controllers to refresh the RAM, they are easier
to use with low end microcontrollers.

The down side is that the density of the SRAMs is comparatively lower than the
DRAMs. Also the cost is comparatively higher.

DRAM – Dynamic Random Access Memory

DRAM stores each bit in a storage cell consisting of capacitor and transistors.
Since capacitors lose their charges quickly they need to be recharged. So by
design, each bit in the DRAM must be refreshed periodically to maintain its
contents and hence the name “Dynamic”. Due to the structural simplicity (only
one transistor and a capacitor per bit), DRAM can be packed much denser than
SRAM.

Even though they need specialized controller to take care of refreshing, their
higher density provides a higher cost to memory ratio compared to SRAM’s.

The most popular type of DRAM used in the SDRAM.

SDRAM – Static Dynamic Random Access Memory

SDRAM is a type of DRAM that ‘Synchronous’ with the system bus. The
device needs a SDRAM controller typically a part of the SoC for it to function
properly. The data is organized as row and column and an internal state
machine that takes care of fetch and refresh logic.

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High speed varieties of SDRAM include DDR, DDR2, and DDR3. DDR – Double
Data Rate RAMs can transfer data on both edges of the clock and hence the
name. DDR2/DDR3 has higher data width and different power requirements
even though internally they operate at the same rates as DDR.

Non-volatile memory

Non-volatile memories will retain their contents even when the power to the
memory device is removed. This makes them better choice for storing the data
that are to be retrieved after the system is restarted. The configurations settings
are typically stored in the non-volatile memory. They are typically slower than
volatile memory and require complex procedures for reading and writing.

Though there are many other kinds of technologies such as Disk-On-Chip, SSD,
MMC Cards etc, are available, the most common non-volatile memories found in
embedded systems are as follows

 Flash memory
 EEPROM
 SD cards

Flash memory

Flash memory is a most commonly used type of non volatile memory in the
embedded system for their durability and larger number of erase cycles.

Microcontroller unit mostly contains flash memory on which the programs are
written for execution. Since flash memory is integrated on-chip with the
microcontroller, its usage become easier. Flash memory is generally
sector/block erasable, which means one sector/block of the memory can be
erased at a time in which each bit erased is moved to a state ‘1’. When it is
written, the state is changed from ‘1’ to ‘0’.

Apart from the on-chip flash memories, there are two types of flash memories
available for external storage. They are NAND and NOR flash memories

NAND flash

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NAND flash memories are the most commonly used types of flash memory.
NAND type of flash memory can be written and read in blocks. They are
generally smaller and are primarily used in USB flash drives and SSD’s. They
have core cells connected in series either as 8 or 16 cells.

NOR flash

NOR flash contains core cells connected in parallel (common ground). Since
random access is supported, they are used for storing Execute in Place code.

Though NAND technology is slower compared to NOR flash, it offers higher


density and better cost ratio as well as a higher life span up to 10 times more
than NOR. Typical interface for flash memory to the processor is the SPI bus.

EEPROM (Electrically Erasable Programmable Read Only Memory)

EEPROM is a special type of memory that supports erasing and programming of


each bit of memory unlike the flash technology that supports only block erases.
Further the power consumption is very low for EEPROM. SPI, I2C are the most
commonly available interface options for EEPROM.

SD cards (Secure Digital cards)

SD cards are the type of non volatile memory commonly used in portable
devices. The SD card itself has a processor inside to take care of the complex
interface requirements as well as performing internal operations like error
correction, wear levelling etc. SD cards are also used as a boot device is most
of the high performance embedded system. Common SD card interface modes
available are SD and SPI.

6. Demonstrate in detail about DMA controller. (CO1-L2- APRIL/MAY 2016)

Direct Memory Access (DMA) allows devices to transfer data without subjecting
the processor a heavy overhead. Otherwise, the processor would have to copy
each piece of data from the source to the destination. This is typically slower
than copying normal blocks of memory since access to I/O devices over a
peripheral bus is generally slower than normal system RAM. During this time the
processor would be unavailable for any other tasks involving processor bus
access. But it can continue to work on any work which does not require bus

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access. DMA transfers are essential for high performance embedded systems
where large chunks of data need to be transferred from the input /output devices
to or from the primary memory.
DMA controller
A DMA controller is a device, usually peripheral to a CPU that is
programmed to perform a sequence of data transfers on behalf of the CPU. A
DMA controller can directly access memory and is used to transfer data from
one memory location to another, or from an I/O device to memory and vice
versa. A DMA controller manages several DMA channels, each of which can be
programmed to perform a sequence of these DMA transfers. Devices, usually
I/O peripherals, that acquire data that must be read (or devices that must output
data and be written to) signal the DMA controller to perform a DMA transfer by
asserting a hardware DMA request (DRQ) signal. A DMA request signal for
each channel is routed to the DMA controller. This signal is monitored and
responded to in much the same way that a processor handles interrupts. When
the DMA controller sees a DMA request, it responds by performing one or many
data transfers from that I/O device into system memory or vice versa. Channels
must be enabled by the processor for the DMA controller to respond to DMA
requests. The number of transfers performed, transfer modes used, and
memory locations accessed depends on how the DMA channel is programmed.
A DMA controller typically shares the system memory and I/O bus with the CPU
and has both bus master and slave capability. Fig.16.1 shows the DMA
controller architecture and how the DMA controller interacts with the CPU. In
bus master mode, the DMA controller acquires the system bus (address, data,
and control lines) from the CPU to perform the DMA transfers. Because the
CPU releases the system bus for the duration of the transfer, the process is
sometimes referred to as cycle stealing.
In bus slave mode, the DMA controller is accessed by the CPU, which
programs the DMA controller's internal registers to set up DMA transfers. The
internal registers consist of source and destination address registers and
transfer count registers for each DMA channel, as well as control and status
registers for initiating, monitoring, and sustaining the operation of the DMA
controller.

DMA Transfer Types and Modes

DMA controllers vary as to the type of DMA transfers and the number of DMA
channels they support. The two types of DMA transfers are flyby DMA transfers

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and fetch-and-deposit DMA transfers. The three common transfer modes are
single, block, and demand transfer modes. These DMA transfer types and
modes are described in the following paragraphs. The fastest DMA transfer
type is referred to as a single-cycle, single-address, or flyby transfer. In a flyby
DMA transfer, a single bus operation is used to accomplish the transfer, with
data read from the source and written to the destination simultaneously. In flyby
operation, the device requesting service asserts a DMA request on the
appropriate channel request line of the DMA controller. The DMA controller
responds by gaining control of the system bus from the CPU and then issuing
the pre-programmed memory address. Simultaneously, the DMA controller
sends a DMA acknowledge signal to the requesting device. This signal alerts
the requesting device to drive the data onto the system data bus or to latch the
data from the system bus, depending on the direction of the transfer. In other
words, a flyby DMA transfer looks like a memory read or write cycle with the
DMA controller supplying the address and the I/O device reading or writing the
data. Because flyby DMA transfers involve a single memory cycle per data
transfer, these transfers are very efficient. Fig.16.2 shows the flyby DMA
transfer signal protocol.

The second type of DMA transfer is referred to as a dual-cycle, dual-address,


flow- through, or fetch-and-deposit DMA transfer. As these names imply, this
type of transfer involves two memory or I/O cycles. The data being transferred
is first read from the I/O device or memory into a temporary data register
internal to the DMA controller. The data is then written to the memory or I/O
device in the next cycle. Fig.16.3 shows the fetch-and-deposit DMA transfer
signal protocol. Although inefficient because the DMA controller performs two
cycles and thus retains the system bus longer, this type of transfer is useful for
interfacing devices with different data bus sizes. For example, a DMA controller
can perform two 16-bit read operations from one location followed by a 32-bit
write operation to another location. A DMA controller supporting this type of
transfer has two address registers per channel (source address and
destination address) and bus-size registers, in addition to the usual transfer
count and control registers.

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Unlike the flyby operation, this type of DMA transfer is suitable for both
memory-to-memory and I/O transfers.
Single, block, and demand are the most common transfer modes. Single
transfer mode transfers one data value for each DMA request assertion. This
mode is the slowest method of transfer because it requires the DMA controller
to arbitrate for the system bus with each transfer. This arbitration is not a major
problem on a lightly loaded bus, but it can lead to latency problems when
multiple devices are using the bus. Block and demand transfer modes increase
system throughput by allowing the DMA controller to perform multiple DMA
transfers when the DMA controller has gained the bus. For block mode
transfers, the DMA controller performs the entire DMA sequence as specified
by the transfer count register at the fastest possible rate in response to a single
DMA request from the I/O device. For demand mode transfers, the DMA
controller performs DMA transfers at the fastest possible rate as long as the I/O
device asserts its DMA request. When the I/O device unasserts this DMA
request, transfers are held off.
DMA Controller Operation

For each channel, the DMA controller saves the programmed address and
count in the base registers and maintains copies of the information in the
current address and current count registers, as shown in Fig.16.1. Each DMA
channel is enabled and disabled via a DMA mask register. When DMA is

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started by writing to the base registers and enabling the DMA channel, the
current registers are loaded from the base registers. With each DMA transfer,
the value in the current address register is driven onto the address bus, and the
current address register is automatically incremented or decremented. The
current count register determines the number of transfers remaining and is
automatically decremented after each transfer. When the value in the current
count register goes from 0 to -1, a terminal count (TC) signal is generated,
which signifies the completion of the DMA transfer sequence. This termination
event is referred to as reaching terminal count. DMA controllers often generate
a hardware TC pulse during the last cycle of a DMA transfer sequence. This
signal can be monitored by the I/O devices participating in the DMA transfers.
DMA controllers require reprogramming when a DMA channel reaches TC.
Thus, DMA controllers require some CPU time, but far less than is required for
the CPU to service device I/O interrupts. When a DMA channel reaches TC,
the processor may need to reprogram the controller for additional DMA
transfers. Some DMA controllers interrupt the
processor whenever a channel terminates. DMA controllers also have
mechanisms for automatically reprogramming a DMA channel when the DMA
transfer sequence completes. These mechanisms include auto initialization and
buffer chaining. The auto initialization feature repeats the DMA transfer
sequence by reloading the DMA channel's current registers from the base
registers at the end of a DMA sequence and re-enabling the channel. Buffer
chaining is useful for transferring blocks of data into noncontiguous buffer
areas or for handling double- buffered data acquisition. With buffer chaining, a
channel interrupts the CPU and is programmed with the next address and
count parameters while DMA transfers are being performed on the current
buffer. Some DMA controllers minimize CPU intervention further by having a
chain address register that points to a chain control table in memory. The DMA
controller then loads its own channel parameters from memory. Generally, the
more sophisticated the DMA controller, the less servicing the CPU has to
perform.
A DMA controller has one or more status registers that are read by the CPU to
determine the state of each DMA channel. The status register typically
indicates whether a DMA request is asserted on a channel and whether a
channel has reached TC. Reading the status register often clears the terminal
count information in the register, which leads to problems when multiple
programs are trying to use different DMA channels.

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Steps in a Typical DMA cycle


1. Device wishing to perform DMA asserts the processors bus request
signal. Processor completes the current bus cycle and then asserts the bus
grant signal to the device.
2. The device then asserts the bus grant ack signal.
3. The processor senses in the change in the state of bus grant ack signal
and starts listening to the data and address bus for DMA activity.
4. The DMA device performs the transfer from the source to destination
address.
5. During these transfers, the processor monitors the addresses on the bus
and checks if any location modified during DMA operations is cached in the
processor. If the processor detects a cached address on the bus, it can take
one of the two actions: 1) Processor invalidates the internal cache entry for the
address involved in DMA write operation. 2)Processor updates the internal
cache when a DMA write is detected
6. Once the DMA operations have been completed, the device releases the
bus by asserting the bus release signal.
7. Processor acknowledges the bus release and resumes its bus cycles
from the point it left off.

7. Explain the function of timing and counting devices in embedded systems.


(CO1-L2)
TIMER: A timer is a specialized type of clock which is used to measure
time intervals. A timer that counts from zero upwards for measuring time
elapsed is often called a stopwatch. It is a device that counts down from a
specified time interval and used to generate a time delay, for example, an
hourglass is a timer.

A counter is a device that stores (and sometimes displays) the number of times
a particular event or process occurred, with respect to a clock signal. It is used
to count the events happening outside the microcontroller. In electronics,

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counters can be implemented quite easily using register-type circuits such as a


flip-flop.

Difference between a Timer and a Counter

The points that differentiate a timer from a counter are as follows −

Timer Counter

The register is incremented considering


The register incremented
1 to 0 transition at its corresponding to
for every machine cycle.
an external input pin (T0, T1).

Maximum count rate is 1/12 Maximum count rate is 1/24 of the


of the oscillator frequency. oscillator frequency.

A timer uses the frequency


A counter uses an external signal to
of the internal clock, and
count pulses.
generates delay.

8. Write a short on watch dog timer. (CO1-L2)

A timing device such that it is set for a preset time interval and an event must
occur during that interval else the device will generate the timeout signal on
failure to get that event in the watched time interval.On that event, the
watchdog timer is disabled to disable generation of timeout or
reset Timeout may result in processor start a service routine or start from
beginning.It resets the system after a defined time.
 Baud or Bit Rate Control for serialcommunication on a line or
network.Timer timeout interrupts define thetime of each baud
 Input pulse counting when using atimer, which is ticked by giving

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nonperiodicinputs instead of the clockinputs. The timer acts as a


counter if, inplace of clock inputs, the inputs aregiven to the timer for
each instance tobe counted.
 Scheduling of various tasks. A chain ofsoftware-timers interrupt and
RTOSuses these interrupts to schedule thetasks.
 Time slicing of various tasks. Amultitasking or multi-
programmedoperating system presents the illusion thatmultiple
tasks or programs are runningsimultaneously by switching
betweenprograms very rapidly, for example, afterevery 16.6 ms.
 Process known as a context switch.[RTOSswitches after preset
time-delay from one running task to the next. task. Each task
cantherefore run in predefined slots of time]
Time division multiplexing (TDM)
 _ Timer device used for multiplexing theinput from a number of
channels.
 _ Each channel input allotted a distinctand fixed-time slot to get a
TDMoutput. [For example, multipletelephone calls are the inputs and
TDMdevice generates the TDM output forlaunching it into the optical
fiber.
Software Timer
_ A software, which executes andincreases or decreases a count-
variable(count value) on an interrupt from on asystem timer output or
from on a realtimeclock interrupt.
_ The software timer also generateinterrupt on overflow of count-value oron
finishing value of the countvariable.
System clock
• In a system an hardware-timing device isprogrammed to tick at
constant intervals.
• At each tick there is an interrupt
• A chain of interrupts thus occur at periodicintervals.
• The interval is as per a presetcount value
• The interrupts are called system clockinterrupts, when used to control
the schedulesand timings of the system

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Software timer (SWT)


• SWT is a timer based on the system clockinterrupts
• The interrupt functions as a clock input toan SWT.
• This input is common to all the SWTs thatare in the list of activated
SWTs.
• Any number of SWTs can be made active ina list.
• Each SWT will set a status flag on itstimeout (count-value reaching
0).
• Actions are analogous to that of ahardware timer. While there is
physicallimit (1, 2 or 3 or4) for the number ofhardware timers in a
system, SWTscan be limited by the number ofinterrupt vectors
provided by the user.

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Example
•Assume that we anticipate that a set of tasks must finish in 100 ms interval.
•The watchdog timer is disabled and stopped by the program instruction in
case the tasks finish
within 100 ms interval.
•In case task does not finish (not disabled by the program instruction),
watchdog timer generates
interrupts after 100 ms and executes a routine, which is programmed to run
because there is
failure of finishing the task in anticipated interval.

The main program typically has a loop that it constantly goes through
performing various functions. The watchdog timer is loaded with an initial value
greater than the worst case time delay through the main program loop. Each
time it goes through the main loop the code resets the watchdog timer
(sometimes called “kicking” or “feeding” the dog). If a fault occurs and the main
program does not get back to reset the timer before it counts down, an
interrupt is generated to reset the processor. Used in this way, the watchdog
timer can detect a fault on an unattended embedded device and attempt
corrective action with a reset. Typically after reset, a register can also be read
to determine if the watchdog timer generated the reset or if it was a normal
reset. On the mbed this register is called the Reset Source Identification
Register (RSID)

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9. Write a short on In-circuit Emulators and Hardware debugging. (CO1-L2)

In-circuit Emulators are the hardware devices that help in debugging


embedded code in microcontroller. They are not only specified for debugging
software but also, debugging certain parts of hardware. In-circuit Emulators are
also called I.C.E devices that allow engineers , debuggers to emulate the
microprocessors or microcontrollers. The in-circuit emulator take the place of
processor and allow special control of the microprocessor such as stopping the
device under test and checking/setting registers or memory, even showing a
trace of the microprocessor has been doing real time before it was stopped.

There are different types and sizes of in-circuit emulators are available
according to the need of engineers and it depends on their project
requirements. The best in-circuit emulator can emulate a large number of
processor family simply by changing the pod and reconfiguration of emulator.
Microcontrollers or Microprocessors family are included such as Intel, Motorola,
PIC, Samsung, NXP, ARM and many more
Benefits- In-circuit emulator offers additional benefits when integrated with
compilers. When in-circuit emulators are integrated with compilers, the
build/make process is streamline so when bugs are found the code can be
quickly changed in-circuit emulator environment and retested. You can get in-
circuit emulators that can support multiple microprocessors built by different
manufacturers.
Hardware Elements in the Embedded Systems
Features- One of the greatest feature of in-circuit emulator is the ability to set
trace condition. Complex trace condition and filters allow developers to trap bug
and then look back the events that led up to the error. The trace offers the
engineers a view of what he would normally not be able to see. The trace
happens in real time which help of events that may need to happen without
delays of stopping or even slowing down the microprocessors.

So, you can choose a good in-circuit emulator that comes in your budget and
according to the compatibility of your computer or laptop as some configuration
has to be checked before buying and using emulators.

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HARDWARE DEBUGGING
Embedded systems are designed to accomplish a very specific task or group of
tasks. Although no single set of constraints will factor in all embedded systems,
it is likely that the designer must balance constraints such as robustness, small
size and weight, real-time requirements, long life cycle, low price, and low (or
no) tolerance for malfunctions. According to Robert Cravotta, Technical Editor –
EDN, in his article “Shedding light on embedded debugging”, 9/4/2008 “For
each year of Embedded Systems Design’s annual market survey of embedded-
system developers, the single most requested area of improvement for
design activities is debugging tools. The percentage of respondents making this
request has remained steady at around 32% throughout the three years of the
survey.” There are many reasons why debugging is seen as the most
problematic and costly issue of the development cycle including increasing
complexity, the balance of often conflicting constraints, “increased
inaccessibility to silicon, lack of bug reproducibility and more pressure to meet
shorter
development schedule cycles.”
The trends in the industry that these reasons will continue to intensify and so
new approaches to debugging are required. In this paper we put forward some
suggestions that have been found to assist. The underlying principle is simple -
use all available tools, low level and high level, to isolate and identify the core
issue. Our suggestions are:
1. Use both high and low level debugging tools
2. Have built-in unit testing in your code
3. Make sure that your code can also run on a desktop
4. Have integrated debugging architecture in your code
5. Use memory management tools
6. Use profilers and code coverage tools
7. Use and re-use proven and well-tested software components

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Unit-II

Embedded Networking

Part-A

1. Give the summary of I/O devices used in embedded system. (CO2-L2-


APRIL/MAY 2016)
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
i) Program memory - program can be located anywhere in memory. Jump, branch
and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB. All jump/branch instructions use absolute addressing.
ii) Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
iii) Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by
RSTinstructions.
 I/O ports
 256 Input ports
 256 Output ports
 Registers
 Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O
and load/store operations.

2. Define bus. (CO2-L1)


Buses: The exchange of information.Information is transferred between units of the
microcomputer by collections of conductors called buses.
There will be one conductor for each bit of information to be passed, e.g., 16 lines for
a 16 bit address bus. There will be address, control, and data buses

3. What are the classifications of I/O devices? (CO2-L1)


i. Synchronous serial input and output
ii. Asynchronous serial UART input and output
iii. Parallel one bit input and output
iv. Parallel port input and output

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4. Give some examples for serial input I/O devices. (CO2-L3)


Audio input, video input, dial tone, transceiver input, scanner, serial IO bus input, etc.,

5. Give the steps for accomplishing input output data transfer. (CO2-L3)
Accomplishing input/output data transfer There are three main methods used to
perform/control input/output data transfers. They are,
• Software programming (scanning or polling)
• interrupt controlled
• Direct memory access (DMA)

6. Give the limitations of polling technique. (CO2-L1)


The polling technique, however, has limitations.
• It is wasteful of the processors time, as it needlessly checks the status of all devices
all the time.
• It is inherently slow, as it checks the status of all I/O devices before it comes back to
check any given one again.
• When fast devices are connected to a system, polling may simply not be fast
enough to satisfy the minimum service requirements. Priority of the device is
determined

7. What do you meant by bus arbitration? (CO2-L1)


Bus Arbitration
Most processors use special control lines for bus arbitration, ie, controlling the use of
The address and data bus,
• An input which the DMAC uses to request the bus
• An output(s) indicating the bus status
• An output indicating acceptance of the DMAC\'s bus request

8. What are the two characteristics of synchronous communication? (CO2-L1)


• Bytes/frames maintain constant phase difference and should not be sent at random
time intervals. No handshaking signals are provided during the communication.
• Clock pulse is required to transmit a byte or frame serially. Clock rate information is
transmitted by the transmitter.

9. What do you mean by asynchronous communication? (CO2-L1)


The most basic way of sharing data is by copying the data in question to each
server. This will only work if the data is changed infrequently and always by
someone with administrative access to all the servers in the cluster.

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10. What are the characteristics of asynchronous communication? (CO2-L1)


• Variable bit rate - need not maintain constant phase difference
• Handshaking method is used
• Transmitter need not transmit clock information along with data bit stream

11. What are the three ways of communication for a device? (CO2-L1)
i. Separate clock pulse along with data bits
ii. Data bits modulated with clock information
iii. Embedded clock information with data bits before transmitting

12. Expand a) SPI b) SCI. (CO2-L2)


SPI - SERIAL PERIPHERAL INTERFACE
SCI - SERIAL COMMUNICATION INTERFACE

13. What are the features of SPI? (CO2-L1)


• SPI has programmable clock rates
• Full-duplex mode
• Crystal clock frequency is 8MHz
• Open drain or totempole output from master to slave

14. Define software timer. (CO2-L1)


A software timer is software that executes the increase/decrease count value on an
interrupt from timer or RTC. Software timer is used as virtual timing device.

15. What are the forms of timer? (CO2-L1)


• Hardware interrupt timer
• Software timer
• User software controlled hardware timer
• RTOS controlled hardware timer
• UP/DOWN count action timer
• One-shot timer (No reload after overflow and finished states)

16. Define RTC. (CO2-L1)


RTC Stands for Real Time Systems. Once the system starts, do not stop/reset and
the count value cannot be reloaded.

17. What is I2C? (CO2-L1)

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Inter- Integrated Circuit (2-wire/line protocol) which offers synchronous


communication.Standard speed: 100Kbps and High speed: 400 Kbps

18. What are the bits in I2C corresponding to? (CO2-L2)


SDA - Serial Data Line and SCL - Serial Clock line

19. What is a CAN bus? Where is it used? (CO2-H1)


CAN stands for Controller Area Network. Serial line, bi-directional bus used in
automobiles.Operates at the rate of 1Mbps.

20. What is USB? Where is it used? (CO2-H1)


USB - Universal Serial Bus
Operating speed - upto 12 Mbps in fast mode and 1.5Mbps in low-speed mode.

21. What are the features of the USB protocol? (CO2-L1)


A device can be attached, configured and used, reset, reconfigured and used,
detached and reattached, share the bandwidth with other devices.

22. What are the four types of data transfer used in USB? (CO2-L1)
• Controlled transfer
• Bulk transfer
• Interrupt driven data transfer
• Iso-synchronous transfer

23. Explain briefly about PCI and PCI/X buses. (CO2-L2)


• Used for most PC based interfacing
• Provides superior throughput than EISA
• Platform-independent
• Clock rate is nearest to sub-multiples of system clock

24. Mention some advanced bus standard protocols; (CO2-L1)


1. GMII (Gigabit Ethernet MAC Interchange Interface)
2. XGMI (10 Gigabit Ethernet MAC Interchange Interface)
3. CSIX-1 6.6 Gbps
4. Rapid IO interconnect specification v1.1 at 8 Gbps

25. What do you meant by high speed device interfaces? (CO2-L1)


Fail-over clustering would not be practical without some way for the redundant

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servers to access remote storage devices without taking a large performance hit, as
would occur if these devices were simply living on the local network. Two common
solutions to this problem are double-ended SCSI and fibre-channel.

26. Mention some I/O standard interfaces. (CO2-L1)


HSTL - High Speed Transceiver Logic (Used in high speed operations)
SSTL - Stub Series Terminated Logic (Used when the buses are needed to isolate
from the large no. of stubs)

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Part-B

1. Describe the functions of a typical parallel I/O interface with a neat diagram.
(CO2-L1)

Types of parallel ports


 Parallel port one bit Input
 Parallel one bit output
 Parallel Port multi-bit Input
 Parallel Port multi-bit Output
Parallel Port single bit input
 Completion of a revolution of a wheel,
 Achievingpreset pressure in a boiler,
 Exceeding the upper limit of permittedweight over the pan of an
electronicbalance,
 Presence of a magnetic piece in the vicinityof or within reach of a
robot arm to its endpoint and Filling of a liquid up to a fixed level.
Parallel Port Output- single bit
 PWM output for a DAC, which controlsliquid level, or temperature, or
pressure, orspeed or angular position of a rotating shaftor a linear
displacement of an object or ad.c. motor control
 Pulses to an external circuit
 Control signal to an external circuit
Parallel Port Input- multi-bit
 ADC input from liquid level measuringsensor or temperature sensor
or pressuresensor or speed sensor or d.c. motor rpmsensor
 Encoder inputs for bits for angular positionof a rotating shaft or a
linear displacementof an object.

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Parallel Port Output- multi-bit


 LCD controller for Multilane LCD displaymatrix unit in a cellular phone
to display onthe screen the phone number, time,messages, character
outputs or pictogrambit-images for display screen or e-mail orweb
page
 Print controller output
 Stepper-motor coil driving bits
Parallel Port Input-Output
PPI 8255
 Touch screen in mobile phone
Ports or DevicesCommunication and communicationprotocols
Two Modes of communication between the devices and computer
system
Full Duplex – Both devices or device and computer system
simultaneously communicate each other.
Half Duplex – Only one device can communicate with another at aninstance

2. Discuss the types of serial port devices. (CO2-L1)


Types of Serial ports
 Synchronous Serial Input
 Synchronous Serial Output
 Asynchronous Serial UART input
 Asynchronous Serial UART output (both as input and as output, for
example,modem.)
Synchronous Serial Input Example
 Inter-processor data transfer, reading from CD or hard disk, audio input, video
input, dial tone, network input, transceiver input, scanner input, remote controller
input, serial I/O
bus input, writing to flash memory using SDIO (Secure Data Association IO based

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card).

Synchronous Serial Input


 The sender along with the serial bits also sends the clock pulses
SCLK (serial clock) to the receiver port pin. The port synchronizes the
serial data input bits with clock bits. Each bit in each byte as well as
each byte in synchronization
 Synchronization means separation by a constant interval or
phase difference. If clock period = T, then each byte at the port is
received at input in period = 8T.
 The bytes are received at constant rates. Each byte at input port
separates by 8T and data transfer rate or the serial line bits is (1/T)
bps. [1bps = 1 bit per s]
 Serial data and clock pulse-inputs
 On same input line − when clock pulses either encode or modulate
serial data input bits suitably. Receiver detects the clock pulses
and receives data bits after decoding or demodulating.
On separate input line − When a separate SCLK input is sent, the
receiver detects at the middle or+ ve edge or –ve edge of the clock
pulses that whether the data-input is 1 or 0 and saves the bits in an 8-
bit shift register. The processing element at the port (peripheral) saves
the byte at a port register from where the microprocessor reads the
byte.

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Master output slave input (MOSI) and Master input slave output (MISO)
MOSI when the SCLK is sent from the sender to the receiver
and slave is forced to synchronize sent inputs from the master as per
the inputs from master clock.

MISO when the SCLK is sent to the sender (slave)from the receiver
(master) and slave is forced to synchronize for sending the inputs to
master as per the master clock outputs.
 Synchronous serial input is used for interprocessor transfers, audio
inputs and streaming data inputs.
Example Synchronous Serial Output

Inter-processor data transfer, multiprocessor communication,


writing to CD or hard disk, audio Input/output, video Input/output,dialer
output, network device output, remote TV Control, transceiver output, and
serial I/O bus output or writing to flash memory using SDIO Synchronous
Serial Output
 Each bit in each byte sent in synchronization with a clock.

Bytes sent at constant rates. If clock period= T, then data transfer rate
is (1/T) bps.
Sender either sends the clock pulses at SCLK pin or sends the
serial data output and clock pulse-input through same output line
with clock pulses either suitably modulate or encode the serial
output bits.
Synchronous serial output using shift register
 The processing element at the port (peripheral) sends the byte through

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a shift register at the port to where the microprocessor writes the byte.
Synchronous serial output is used for inter processor transfers, audio outputs
and streaming data outputs. Synchronous Serial Input/output

 Each bit in each byte is in synchronization at input and each


bit in each byte is in synchronization at output with the master
clock output.
 The bytes are sent or received at constant rates. The I/Os can also be
on same I/O line when input/output clock pulses either suitably
modulate or encode the serial input/output, respectively. If clock
period = T, then data transfer rate is (1/T)bps.
 The processing element at the port (peripheral)sends and receives the
byte at a port register to or from where the microprocessor writes or
reads the byte

Asynchronous Serial port line RxD (receive data).

 Does not receive the clock pulses or clock information along with the
bits.
 Each bit is received in each byte at fixed intervals but each
received byte is not in synchronization.

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 Bytes separate by the variable intervals or phase differences.


 Asynchronous serial input also called UART input if serial input is
according to UART protocol

Example Serial Asynchronous Input

 Asynchronous serial input is used for keypad inputs and modem inputs
in computers
 Keypad controller serial data-in, mice, keyboard controller, modem
input, character send inputs on serial line [also called UART (universal
receiver and transmitter) input when according to UART mode]

UART protocol serial line format


 Starting point of receiving the bits for each byte is indicated by a line
transition from 1to 0
for a period = T. [T−1 called baud rate.]
 If sender‘s shift-clock period = T, then a byte at the port is received at
input in period=
10.T or 11.T due to use of additional bits at start and end of each
byte. Receiver detects n bits at the intervals of T from the middle of
the start indicating bit. The n = 0, 1, …, 10 or 11 and finds whether
the data-input is 1 or 0 and saves the bits in an 8-bit shift register.
 Processing element at the port (peripheral)saves the byte at a port

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register from where the microprocessor reads the byte.


Asynchronous Serial Output
 Asynchronous output serial port line TxD(transmit data).
 Each bit in each byte transmit at fixed intervals but each output byte is
not in synchronization (separates by a variable interval or phase
difference). Minimum separation is 1 stop bit interval TxD.
 Does not send the clock pulses along with the bits.
 Sender transmits the bytes at the minimum intervals of n.T. Bits
receiving starts from the middle of the start indicating bit,
 n = 0, 1, …, 10 or 11 and sender sends the bits through a 10 or
11 -bit shift register. The processing element at the port(peripheral)
sends the byte at a port register to where the microprocessor is to write
the byte. Synchronous serial output is also called UART output if serial
output is according to UART protocol
Example Serial Asynchronous Output
_ Output from modem, output for printer, the output on a serial line [also
called UART output when according to UART]
Half Duplex
 Half duplex means as follows: at an instant communication can only
be one way (input or output) on a bi-directional line.
 An example of half-duplex mode─ telephone communication. On
one telephone line, the talk can only in the half duplex way mode.
Full Duplex
 Full duplex means that at an instant,the communication can be both
ways.
An example of the full duplexasynchronous mode of communicationis the
communication between themodem and the computer though TxDand RxD
lines or communication using
SI in modes 1, 2 and 3 in 8051

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3. Explain the serial communication using SERIAL BUS COMMUNICATION


PROTOCOLS– USB. (CO2-L2- APRIL/MAY 2016)

USB Host ApplicationsConnecting


• flash memory cards,
• pen-like memory devices,
• digital camera,
• printer,
• mouse-device,
• PocketPC,
• video games,
• Scanner
Universal Serial Bus (USB)
 Serial transmission and receptionbetween host and serial devices
 The data transfer is of four types: (a)Controlled data transfer, (b) Bulk
datatransfer, (c) Interrupt driven datatransfer, (d) Iso-synchronous
transfer
 A bus between the host system andinterconnected number of
peripheraldevices
USB Protocol Features

 Maximum 127 devices can connect ahost.


 Three standards: USB 1.1 (a low speed1.5 Mbps 3 meter channel along
with ahigh speed 12 Mbps 25 meter channel),USB 2.0 (high speed 480
Mbps 25meter channel), and wireless USB(high speed 480 Mbps 3 m)

Host connection to the devices or nodes


 Using USB port driving software andhost controller,
 Host computer or system has a hostcontroller,which connects to a

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roothub.
 A hub is one that connects to othernodes or hubs.
 A tree- like topology
USB Device features
 Can be hot plugged (attached), configuredand used, reset,
reconfigured and used
 Bandwidth sharing with other devices: Hostschedules the sharing of
bandwidth amongthe attached devices at an instance.
 Can be detached (while others are inoperation) and reattached.
 Attaching and detaching USB device orhost without rebooting
USB device descriptor
 Has data structure hierarchy asfollows:

It has device descriptor at the root,which has number of configuration
descriptors, which has number ofinterface descriptor and which
hasnumber of end point descriptor.
Powering USB device
 A device can be either bus-powered orself- powered.
 In addition, there is a powermanagement by software at the host
forUSB ports
USB protocol
o USB bus cable has four wires, one for+5V, two for twisted pairs and
one forground.

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o Termination impedances at each end asper the device-speed.


o Electromagnetic Interference (EMI)-shielded cable for the 15 Mbps
USBdevices
o Serial signals NRZI (Non Return toZero (NRZI)
o The synchronization clock encoded byinserting synchronous code
(SYNC)field before each USB packet
o Receiver synchronizes its bits recoveryclock continuously
USB Protocol
• A polled bus
• Host controller regularly polls the presenceof a device as scheduled by the
software.
• It sends a token packet.
• The token consists of fields for type,direction, USB device address and
deviceend-point number.
• The device does the handshaking through ahandshake packet,
indicating successful orunsuccessful transmission.
• A CRC field in a data packet permitserror detection
USB supported three types of pipes
1. 'Stream' with no USB- defined protocol. Itis used when
the connection is alreadyestablished and the data flow
starts
2. 'Default Control' for providing access.
3. 'Message' for the control functions for of thedevice.
4. Host configures each pipe with the databandwidth to be used, transfer
service typeand buffer sizes.

4. Explain the serial communication using SERIAL BUS COMMUNICATION


PROTOCOLS– CAN. (CO2-L2- APRIL/MAY 2016)
Distributed Control Area Networkexample - a network of embeddedsystems
in automobile
_ CAN-bus line usually interconnects to aCAN controller between line and

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host at thenode. It gives the input and gets outputbetween the physical and
data link layers atthe host node.
_ The CAN controller has a BIU (businterface unit consisting of buffer
anddriver), protocol controller, status-cumcontrolregisters, receiver-buffer
andmessage objects. These units connect thehost node through the host
interface circuit

Three standards:
1. 33 kbps CAN,
2. 110 kbps Fault Tolerant CAN,
3. 1 Mbps High Speed CAN
CAN protocol
There is a CAN controller between the CANline and the host node.
_ CAN controller ─BIU (Bus Interface Unit)consisting of a buffer and driver
_ Method for arbitration─ CSMA/AMP(Carrier Sense Multiple Access
withArbitration on Message Priority basis)

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Each Distributed Node Uses:


• Twisted Pair Connection up to 40 m –for bi-directional data
• Line, which pulls to Logic 1 through aresistor between the line and + 4.5V to
+12V.
• Line Idle state Logic 1 (Recessivestate)
• Uses a buffer gate between an inputpin and the CAN line
• Detects Input Presence at the CAN linepulled down to dominant (active)
statelogic 0 (ground ~ 0V) by a sender tothe CAN line
• Uses a current driver between theoutput pin and CAN line and pulls linedown
to dominant (active) state logic 0(ground ~ 0V) when sending to theCAN
lineProtocol defined start bit followed bysix fields of frame bitsData frame
starts after first detecting thatdominant state is not present at the CANline with
logic 1 (R state) to 0 (D statetransition) for one serial bit interval
• After start bit, six fields starting fromarbitration field and ends with seven
logic0s end-field
• 3-bit minimum inter frame gap before nextstart bit (R→ D transition) occurs
Protocol defined First field in frame bits
First field of 12 bits ,arbitration field,11-bit destination address and RTR bit
(Remote Transmission Request)

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_ Destination device address specified in an11-bit sub-field and whether the


data bytebeing sent is a data for the device or arequest to the device in 1-bit
sub-field.
_ Maximum 211 devices can connect a CANcontroller in case of 11-bit
address fieldstandard11-bit address standard CAN
_ Identifies the device to which data isbeing sent or request is being made.
_ When RTR bit is at '1', it means thispacket is for the device at
destinationaddress. If this bit is at '0' (dominantstate) it means, this packet is
a requestfor the data from the device.
Protocol defined frame bits Second field
_ Second field of 6 bits─ control field.
The first bit is for the identifier‘sextension.
_ The second bit is always '1'.
_ The last 4 bits specify code for dataLength
_ Third field of 0 to 64 bits─ Its lengthdepends on the data length code in
thecontrol field.
• Fourth field (third if data field has nobit present) of 16 bits─ CRC

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(CyclicRedundancy Check) bits.


• The receiver node uses it to detect theerrors, if any, during the transmission
• Fifth field of 2 bits─ First bit 'ACK slot'
• ACK = '1' and receiver sends back '0' in this slotwhen the receiver detects an
error in the reception.
• Sender after sensing '0' in the ACK slot, generallyretransmits the data frame.
• Second bit 'ACK delimiter' bit. It signals the endof ACK field.
• If the transmitting node does not receive anyacknowledgement of data frame
within a specifiedtime slot, it should retransmit.
Sixth field of 7-bits ─ end- of- theframespecification and has seven '0's

4.Explain the serial bus communication protocol using I2C. (CO2-L2- APRIL/MAY
2016)
Interconnecting number of device circuits, Assume flash memory,
touch screen,ICs for measuring temperatures andICs for measuring
pressures at a number of processes in a plant.ICs mutually network
through acommon synchronous serial bus I2C An 'Inter Integrated Circuit'
(I2C) bus,a popular bus for these circuits.Synchronous Serial Bus
Communication for networking. Each specific I/O synchronous serial
devicemay be connected to other using specificinterfaces, for example,
with I/O deviceusing I2C controller
I2C Bus communication− use of onlysimplifies the number of connections
andprovides a common way (protocol) of connecting different or same type
of I/Odevices using synchronous serialcommunication
IO I2C Bus
Any device that is compatible with a I2Cbus can be added to the
system(assuming an appropriate device driverprogram is available), and a
I2C devicecan be integrated into any system thatuses that I2C bus.

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Originally developed at Philips Semiconductors Synchronous Serial


Communication 400kbps up to 2 m and 100 kbps forlonger distances
Three I2C standards
1. Industrial 100 kbps I2C,
2. 100 kbps SM I2C,
3. 400 kbps I2C

I2C Bus
The Bus has two lines that carry its signals— one line is for the clock
andone is
for bi- directional data.There is a standard protocol for the I2Cbus.
Device Addresses and Master in the I2C bus
 Each device has a 7-bit address using which the data transfers take
place.
 Master can address 127 other slaves at an instance.
 Master has at a processing elementfunctioning as bus controller or
amicrocontroller with I2C (InterIntegrated Circuit) bus interfacecircuit.

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Slaves and Masters in the I2C bus


o Each slave can also optionally has I2C (InterIntegrated Circuit) bus
controller and processing element.
o Number of masters can be connected on thebus.
o However, at an instance, master is one,which initiates a data transfer on
SDA(serial data) line and which transmits theSCL (serial clock) pulses.
From master, a data frame has fields beginning from startbit

Synchronous Serial Bus Fields and its length


_ First field of 1 bit─ Start bit similar to onein an UART
Second field of 7 bits─ address field. Itdefines the slave address, which is
beingsent the data frame (of many bytes) by the master. Third field of 1
control bit defines whether a read or write cycle is in progress. Fourth field
of 1 control bit defines whether is the present data is an acknowledgment
(from slave).Fifth field of 8 bits
I2C device data byte
Sixth field of 1-bit─ bit NACK (negativeacknowledgement) from the
receiver. If active then acknowledgment after a transferis not needed from
the slave, elseacknowledgement is expected from the slave .Seventh field
of 1 bit ─ stop bit like in anUART
Disadvantage of I2C bus
• Time taken by algorithm in thehardware that analyzes the bits throughI2C in
case the slave hardware does notprovide for the hardware that supportsit.

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• Certain ICs support the protocol andcertain do not.


• Open collector drivers at the masterneed a pull-up resistance of 2.2 K
oneach line
5.Write a short note on RS 232 bus. (CO2-L2)
This is the original serial port interface “standard” and it stands for “Recommended
Standard Number 232” or more appropriately EIA Recommended Standard 232 is the
oldest and the most popular serial communication standard. It was first introduced in
1962 to help ensure connectivity and compatibility across manufacturers for simple
serial data communications.
Applications
• Peripheral connectivity for PCs (the PC COM port hardware), which can range
beyond modems and printers to many different handheld devices and modern
scientific instruments.
All the various characteristics and definitions pertaining to this standard can be
summarized according to:
• The maximum bit transfer rate capability and cable length.
• Communication Technique: names, electrical characteristics and functions of
signals.

• The mechanical connections and pin assignments.


Maximum Bit Transfer Rate, Signal Voltages and Cable Length
• RS-232’s capabilities range from the original slow data rate of up to 20 kbps
to over 1 Mbps for some of the modern applications.
• RS-232 is mainly intended for short cable runs, or local data transfers in a
range up to 50 feet maximum, but it must be mentioned here that it also
depends on the Baud Rate.
• It is a robust interface with speeds to 115,200 baud, and
• It can withstand a short circuit between any 2 pins.
• It can handle signal voltages as high / low as ±15 volts.

Signal states and communication technique


Signals can be in either an active state or an inactive state. RS232 is an Active LOW
voltage driven interface where:

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ACTIVE STATE: An active state corresponds to the binary value 1. An active signal
state can also be indicated as logic “1”, “on”, “true”, or a “mark”.
INACTIVE STATE: An inactive signal state is stated as logic “0”, “off”, “false”, or a
“space”.
• For data signals, the “true” state occurs when the received signal voltage is more
negative than -3 volts, while the "false" state occurs for voltages more positive
than 3 volts.
• For control signals, the "true" state occurs when the received signal voltage is
more positive than 3 volts, while the "false" state occurs for voltages more
negative than -3 volts.

Transition or “Dead Area”


Signal voltage region in the range >-3.0V and < +3.0V is regarded as the 'dead
area' and allows for absorption of noise. This same region is considered a transition
region, and the signal state is undefined.
To bring the signal to the "true" state, the controlling device unasserts (or lowers) the
value for data pins and asserts (or raises) the value for control pins. Conversely, to
bring the signal to the "false" state, the controlling device asserts the value for data pins
and unasserts the value for control pins. The "true" and "false" states for a data signal
and for a control signal are as sh A factor that limits the distance of reliable data transfer
using RS-232 is the signaling technique that it uses.
• This interface is “single-ended” meaning that communication occurs over a
SINGLE WIRE referenced to GROUND, the ground wire serving as a second
wire. Over that single wire, marks and spaces are created.
• While this is very adequate for slower applications, it is not suitable for faster and
longer applications.

The communication technique


• RS-232 is designed for a unidirectional half-duplex communications mode.
That simply means that a transmitter (driver) is feeding the data to a receiver
over a copper line. The data always follows the direction from driver to receiver
over that line. If return transmission is desired, another set of driver- receiver
pair and separate wires are needed. In other words, if bi-directional or full-
duplex capabilities are needed, two separate communications paths are
required.

Disadvantage

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Being a single-ended system it is more susceptible to induced noise, ground loops


and ground shifts, a ground at one end not the same potential as at the other end of
the cable e.g. in applications under the proximity of heavy electrical installations and
machineries But these vulnerabilities at very high data rates and for those applications
a different standard, like the RS-422 etc., is required which have been explained
further.

6. Write a short note on RS 422 bus. (CO2-L2)


RS-422 and RS-423 (EIA Recommended Standard 422 and 423)
These were designed, specifically; to overcome the distance and speed limitations of
RS-232.Although they are similar to the more advanced RS-232C, but can
accommodate higher baud rates and longer cable lengths and, accommodate multiple
receivers.
Maximum Bit Transfer Rate, Signal Voltages and Cable Length
• For both of these standards the data lines can be up to 4,000 feet with a data rate
around 100 kbps.
• The maximum data rate is around 10 Mbps for short runs, trading off distance
for speed.
• The maximum signal voltage levels are ±6 volts.
• The signaling technique for the RS-422 and RS-423 is mainly responsible for there
superiority over RS-232 in terms of speed and length of transmission as
explained in the next subsection.

Communication Technique
• The flair of this standard lies in its capability in tolerating the ground voltage
differences between sender and receiver. Ground voltage differences can occur
in electrically noisy environments where heavy electrical machinery is
operating.
• The criterion here is the differential-data communication technique, also
referred to as balanced-differential signaling. In this, the driver uses two wires
over which the signal is transmitted. However, each wire is driven and floating
separate from ground, meaning, neither is grounded and in this respect this
system is different to the single-ended systems. Correspondingly, the receiver
has two inputs, each floating above ground and electrically balanced with the
other when no data is being transmitted. Data on the line causes a desired

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electrical imbalance, which is recognized and amplified by the receiver. The


common-mode signals, such as induced electrical noise on the lines caused
from machinery or radio transmissions, are, for the most part, canceled by the
receiver. That is because the induced noise is identical on each wire and the
receiver inverts the signal on one wire to place it out of phase with the other
causing a subtraction to occur which results in a Zero difference. Thus, noise
picked up by the long data lines is eliminated at the receiver and does not
interfere with data transfer. Also, because the line is balanced and separate from
ground, there is no problem associated with ground shifts or ground loops.

• It may be mentioned here to avoid any ambiguity in understanding the RS-422 and
the RS-423 standards, that, the standard RS-423 is an advanced counterpart of
RS-422 which has been designed to tolerate the ground voltage differences
between the sender and the receiver for the more advanced version of RS-232,
that is, the RS-232C.
• Unlike RS-232, an RS-422 driver can service up to 10 receivers on the same line
(bus). This is often referred to as a half-duplex single-source multi-drop
network, (not to be confused with multi-point networks associated with RS-
485), this will be explained further in conjugation with RS-485.

• Like RS-232, however, RS-422 is still half-duplex one-way data communications


over a two-wire line. If bi-directional or full-duplex operation is desired, another
set of driver, receiver(s) and two-wire line is needed. In which case, RS-485 is
worth considering.
Applications
This fits well in process control applications in which instructions are sent out to many
actuators or responders. Ground voltage differences can occur in electrically
noisy environments where heavy electrical machinery is operating.

7.Write a short note on RS 485 bus. (CO2-L2)


This is an improved RS-422 with the capability of connecting a number of devices
(transceivers) on one serial bus to form a network.
The Standard
Maximum Bit Transfer Rate, Signal Voltages and Cable Length
• Such a network can have a "daisy chain" topology where each device is connected
to two other devices except for the devices on the ends.

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• Only one device may drive data onto the bus at a time. The standard does not
specify the rules for deciding who transmits and when on such a network. That
solely depends upon the system designer to define.
• Variable data rates are available for this standards but the standard max. data rate
is 10 Mbps, however ,some manufacturers do offer up to double the standard
range i.e. around 20 Mbps,but of course, it is at the expense of cable width. It
can connect upto 32 drivers and receivers in fully differential mode similar to the
RS – 422.

COMMUNICATION TECHNIQUE
EIA Recommended Standard 485 is designed to provide bi-directional half-duplex
multi-point data communications over a single two-wire bus.
• Like RS-232 and RS-422, full-duplex operation is possible using a four-wire, two-
bus network but the RS-485 transceiver ICs must have separate transmit and
receive pins to accomplish this.
• RS-485 has the same distance and data rate specifications as RS-422 and
uses differential signaling but, unlike RS-422, allows multiple drivers on the
same bus. As depicted in the Figure below, each node on the bus can include
both a driver and receiver forming a multi-point star network. Each driver at each
node remains in a disabled high-impedance state until called upon to transmit.
This is different than drivers made for RS-422 where there is only one driver and
it is always enabled and cannot be disabled.
• With automatic repeaters and tri-state drivers the 32-node limit can be greatly
exceeded. In fact, the ANSI-based SCSI-2 and SCSI-3 bus specifications use
RS-485 for the physical (hardware) layer.
Advantages
• Among all of the asynchronous standards mentioned above this standard offers the
maximum data rate.
• Apart from that special hardware for avoiding bus contention and ,
• A higher receiver input impedance with lower Driver load impedances are its other
assets.
All together the important electrical and mechanical characteristics for application
purposes may be classified and summarized according to the table below
. RS-232 RS-422/423 RS-485
Signaling Single-Ended Differential Differential
Technique (Unbalanced) (Balanced) (Balanced)

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Drivers and 1 Driver 1 Driver 32 Drivers


Receivers on 1 Receiver 10 Receivers 32 Receivers
Bus
Maximum 50 feet 4000 feet 4000 feet
Cable Length
Original Standard 20 kbps 10 Mbps 10 Mbps
Maximum down to down to
Data Rate 100 kbps 100 kbps
Minimum Loaded +/-5.0 V +/-2.0 V +/-1.5 V
Driver Output
Voltage Levels
Driver Load 3 to 7 k 100 54
Impedance
Receiver Input 3 to 7 k 4k 12 k
Impedance or greater or greater

8. Write a short note on Device drivers. (CO2-L2)


A device driver has a set of routines (functions) used by a high-level language
programmer, which does the interaction with the device hardware, sends
control commands to the device, communicates data to the device and runs the
codes for reading device data.
• Each device in a system needs devicedriver routine with number of device functions.
• An ISR relates to a device driver command (device-function). The device driver uses
SWI to call the related ISR (device-function routine)
• The device driver also responds to device hardware interrupts.
A programmer uses generic commands for device driver for using a device. The
operating system provides these generic commands. Each command relates to an ISR.
The device driver command uses an SWI to call the related ISR device-function routine)
Generic functions used for the commands to the device are device create ( ), open ( ),
connect ( ), bind ( ), read ( ), write ( ), ioctl ( ) [for IO control], delete ( ) and close ( ).
Different in different operating system. Same device may have different code for the
driver when system is using different operating system Does the interrupt service for
any event related to the device and use the system and IO buses required for the
device service. _ Device driver can be considered software layer between an
application program and the device

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Unit-III

Embedded Firmware development Environment

Part-A

1. Describe the concept of EDLC. (CO3-L1- APRIL/MAY 2016)


EDLC is an Analysis-Design-Implementation based problem solving
approach for the product development.
 Analysis – What product need to be developed
 Design – Good approach for building it
 Implementation – To develop it

2. Quote the different phases of EDLC. (APRIL/MAY 2016-CO3-L1)


 Need
 Analysis
 Design
 Development and testing
 Support
 Upgrade
 Disposal

3. Generalize why EDLC is essential in embedded systems. (CO3-H1)


Essential in understanding the scope and complexities involved in any
Embedded product development.Defines interaction and activities among
Various groups of product development sector.
 Project management
 System design and development
 System testing
 Release management and quality assurance

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4. List the objectives of Embedded product Development Life Cycle.


(CO3-L1)
 Aim of any product development is the Marginal benefit

 Marginal benefit = Return on investment


 Product needs to be acceptable by the end user i.e. it has to meet
the requirements of the end user in terms of quality, reliability &
functionality.
 EDLC helps in ensuring all these requirements by following three
objective
 Ensuring that high quality products are delivered to user
 Risk minimization and defect prevention in product
development through project management
 Maximize productivity

5. Predict the aim of product development in embedded systems.


(CO3-H2)
 Aim of any product development is the Marginal benefit

 Marginal benefit = Return on investment


 Product needs to be acceptable by the end user i.e. it has to meet
the requirements of the end user in terms of quality, reliability &
functionality.

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6.Design the classic embedded product development life cycle model. (CO3-H3)

7. What are different types of testing? (CO3-L1)


Testing phase can be divided into
 Unit testing – independent testing of hardware and firmware
 Integration testing – testing after integrating hardware and firmware
 System testing – testing of whole system on functionality and non-
functionality basis
 User acceptance testing – testing of the product against the criteria
mentioned by the end-user/client
 Test reports

8.What are the steps used for designing co-design? (CO3-L1)


Modeling
The system to be designed and experimenting with algorithms involved;
Refining (or “partitioning”)
The function to be implemented into smaller, interacting pieces

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HW-SW partitioning:
Allocating elements in the refined model to either (1) HW units, or (2) SW
running on custom Hardware or a general microprocessor.
Scheduling
The times at which the functions are executed. This is important when
several modules in the Partition shares a single hardware unit.
Mapping (Implementing)
A functional description into (1) software that runs on a processor or (2) a
collection of custom, semi-custom, or commodity HW.

9. Draw the flowchart for hardware-software codesign. (CO3-L1)

10.What are the different approaches used for designing embedded system.
(CO3-L1)
1. Linear/Waterfall Model
2. Iterative/Incremental/fountain model
3. Prototyping/evolutionary model
4. Spiral model

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Part-B

1. What is hardware software co-design? Explain the fundamental issues


in hardware software codesign.( CO3-L1- APRIL/MAY 2016)
Embedded systems employ a combination of application specific h/w (boards,
ASICs, FPGAs etc.)–performance, low power s/w on prog. processors: DSPs,
μcontrollers etc.–flexibility, complexity
Increasingly on the same chip: System-on-a-chip Application Specific Gates
Processor Cores Analog I/O Memory DSP Code.
A significant part of the problem is deciding which parts should be in s/w on
programmable processors and which in specialized h/w Lots of issues in this
decision making Ad hoc approaches based on earlier experience with similar
products, & on manual design H/W-S/W partitioning decided at the beginning,
and then designs proceed separately CAD tools take care of h/w fairly well. But,
S/W is a different story...HLLs such as C help, but can’t cope with complexity.
H/W-like synthesis & verification based design methodology. System behavior
described at a high level of abstraction using formal computation model.
Decomposition into H/W and S/W based on trade-off evaluations from behavioral
description–H/W & S/W design proceed in parallel with feedback. Final
implementation made as much as possible using automatic synthesis from high
level of abstraction–ensures “correct by construction” implementations.
simulation or verification at higher levels of abstraction.
 Co-design-joint optimization of hardware and software
 Co-synthesis-synthesis assisting co-design–mixed h.w-s.w design from
(formal) specification–rapid
Exploration of design alternatives–enable exploration of architectural
alternatives
 Co-simulation-simulation of mixed h/w and s/w systems
 Co-specification-specifying mixed h/w and s/w systems
 Co-verification
Designing Embedded Systems
Modeling
The system to be designed and experimenting with algorithms involved;
Refining (or “partitioning”)
The function to be implemented into smaller, interacting pieces
HW-SW partitioning:
Allocating elements in the refined model to either (1) HW units, or (2) SW
running on custom Hardware or a general microprocessor.

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Scheduling
The times at which the functions are executed. This is important when
several modules in the Partition shares a single hardware unit.
Mapping (Implementing)
A functional description into (1) software that runs on a processor or (2) a
collection of custom, semi-custom, or commodity HW.

2. Design a classic embedded product development life cycle model and


discuss about Various steps involved in it. (CO3-H3- APRIL/MAY 2016)

Different phases of edlc


 A life cycle of product development is commonly referred as the “model”
 A simple model contains five phases

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 Requirement analysis
 Design
 Development and test
 Deployment and maintenance
 The no of phases involved in EDLC model depends on the complexity
of the product
Classic Embedded product development life cycle model

NEED:
 Any embedded product may evolves as an output of a need.
 Need may come from an individual/from public/from company(generally
speaking from an end user/client)
 New/custom product development
 Product re-engineering
 Product maintenance

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ANALYSIS:

DESIGN: Deals with the entire design of the product taking the
requirements into consideration and focuses on how the functionalities can be
delivered.
• Only i/p & o/p are defined here
• Product will look like a black box
• Sent for approval from client
• Generates detailed architecture
• Detailed architecture also needs approval
DEVELOPMENT AND TESTING:
 Development phase transforms the design into realizable product
 Design is transformed into hardware and firmware
 Look and feel of the device is very important

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Testing phase can be divided into


 Unit testing – independent testing of hardware and firmware
 Integration testing – testing after integrating hardware and firmware
 System testing – testing of whole system on functionality and non-
functionality basis
 User acceptance testing – testing of the product against the criteria
mentioned by the end-user/client
 Test reports
DEPLOYMENT:
 A process of launching fully functional model into the market
SUPPORT:
 Deals with the operation and maintenance of the product
 Support should be provide to the end user/client to fix the bugs of the
product
UPGRADES:
 Releasing of new version for the product which is already exists in the
market
 Releasing of major bug fixes.
RETIREMENT/DISPOSAL:
 Everything changes, the technology you feel as the most advanced and best
today may not be the same tomorrow
 Due to this the product cannot sustain in the market for long
 It has to be disposed on right time before it causes the loss.

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3. Illustrate with an example the phenomenon of Linear/waterfall model in


embedded system design. (CO3-L2- APRIL/MAY 2016)
Linear/Waterfall Model

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4. Write a short note on Iterative , prototyping and spiral model. (CO3-L1-


APRIL/MAY 2016)

Prototyping/evolutionary model:
 Similar to iterative model, product is developed in multiple cycles

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The only difference is the model produces more refined prototype of the product at
each cycle instead of just adding the functionality at each cycle like in iterative model.

Spiral model:
 Spiral model is best suited for the development of complex embedded products
and situations where the requirements are changing from customer side.
 Risk evaluation in each stage helps in reducing risk

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Unit-IV
RTOS Based Embedded System Design
Part-A

1. Define process.(CO4-L1)
A process is a program that performs a specific function.

2. Define task and Task state. (CO4-L1)


A task is a program that is within a process. It has the following states:
1. Ready
2. Running
3. Blocked
4. Idle

3. Define (TCB). (CO4-L1)


The TCB stands for Task Control Block which holds the control of all the tasks
within the block. It has separate stack and program counter for each task.

4. What is a thread? (CO4-L1)


A thread otherwise called a lightweight process (LWP) is a basic unit of CPU
utilization, it comprises of a thread id, a program counter, a register set and a
stack. It shares with other threads belonging to the same process its code
section, data section, and operating system resources such as open files and
signals.

5. What are the benefits of multithreaded programming? (CO4-L1)


The benefits of multithreaded programming can be broken down into four major
categories:
¬ Responsiveness
¬ Resource sharing
¬ Economy
¬ Utilization of multiprocessor architectures

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6. Compare user threads and kernel threads. (CO4-H1)


User threads Kernel threads User threads are supported above the kernel and
are implemented by a thread library at the user level Kernel threads are
supported directly by the operating system Thread creation & scheduling are
done in the user space, without kernel intervention. Therefore they are fast to
create and manage Thread creation, scheduling and management are done by
the operating system. Therefore they are slower to create & manage compared
to user threads Blocking system call will cause the entire process to block If the
thread performs a blocking system call, the kernel can schedule another thread
in the application for execution
7. Define RTOS. (CO4-L1)
A real-time operating system (RTOS) is an operating system that has been
developed for realtime applications. It is typically used for embedded
applications, such as mobile
telephones, industrial robots, or scientific research equipment.

8. Define task and task rates. (CO4-L1)


An RTOS facilitates the creation of real-time systems, but does not guarantee
that they are real-time; this requires correct development of the system level
software. Nor does an RTOS necessarily have high throughput — rather they
allow, through specialized scheduling algorithms and deterministic behavior, the
guarantee that system deadlines can be met. That is, an RTOS is valued more
for how quickly it can respond to an event than for the total amount of work it can
do. Key factors in evaluating an RTOS are therefore maximal interrupt and
thread latency

9. Define CPU scheduling. (CO4-L1)


CPU scheduling is the process of switching the CPU among various processes.
CPU scheduling is the basis of multi-programmed operating systems. By
switching the CPU among processes, the operating system can make the
computer more productive.

10. Define Synchronization. (CO4-L1)


Message passing can be either blocking or non-blocking. Blocking is considered
to be synchronous and non-blocking is considered to be asynchronous.

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11. Define Inter process communication. (CO4-L1)


Inter-process communication (IPC) is a set of techniques for the exchange of
data among multiple threads in one or more processes. Processes may be
running on one or more computers connected by a network. IPC techniques are
divided into methods for message passing, synchronization, shared memory, and
remote procedure calls (RPC). The method of IPC used may vary based on the
bandwidth and latency of communication between the threads, and the type of
data being communicated.

12. Define Semaphore. (CO4-L1)


A semaphore ‘S’ is a synchronization tool which is an integer value that, apart
from initialization, is accessed only through two standard atomic operations; wait
and signal. Semaphores can be used to deal with the n-process critical section
problem. It can be also used to solve various synchronization problems.
The classic definition of ‘wait’
wait (S){
while (S<=0)
;
S--; }
The classic definition of ‘signal’
signal (S){
S++;
}

13. What is a semaphore? (CO4-L1)


Semaphores -- software, blocking, OS assistance solution to the mutual
exclusion problem basically a non-negative integer variable that saves the
number of wakeup signals sent so they are not lost if the process is not sleeping
another interpretation we will see is that the semaphore value represents the
number of resources available

14. Give the semaphore related functions. (CO4-L2)


A semaphore enforces mutual exclusion and controls access to the process
critical sections. Only one process at a time can call the function fn.
SR Program: A Semaphore Prevents the Race Condition.
SR Program: A Semaphore Prevents Another Race Condition.

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15. When the error will occur when we use the semaphore? (CO4-L2)
i. When the process interchanges the order in which the wait and signal
operations on the semaphore mutex.
ii. When a process replaces a signal (mutex) with wait (mutex).
iii. When a process omits the wait (mutex), or the signal (mutex), or both.

17. Differentiate counting semaphore and binary semaphore. (CO4-H1)


Binary Semaphore:
The general-purpose binary semaphore is capable of addressing the
requirements of both forms of task coordination: mutual exclusion and
synchronization. A binary semaphore can be viewed as a flag that is available
(full) or unavailable (empty). Counting semaphores are another means to
implement task synchronization and mutual exclusion.
Counting Semaphore:
The counting semaphore works like the binary semaphore except that it keeps
track of the number of times a semaphore is given. Every time a semaphore is
given, the count is incremented; every time a semaphore is taken, the count is
decremented. When the count reaches zero, a task that tries to take the
semaphore is blocked. As with the binary semaphore, if a semaphore is given
and a task is blocked, it becomes unblocked. However, unlike the binary
semaphore, if a semaphore is given and no tasks are blocked, then the count is
incremented. This means that a semaphore that is given twice can be taken
twice without blocking.

18. What is priority inheritance? (CO4-L1)


Priority inheritance is a method for eliminating priority inversion problems. Using
this programming method, a process scheduling algorithm will increase the
priority of a process to the maximum priority of any process waiting for any
resource on which the process has a resource lock.

19. Define Message Queue. (CO4-L1)


A message queue is a buffer managed by the operating system. Message
queues allow a variable number of messages, each of variable length, to be
queued. Tasks and ISRs can send messages to a message queue, and tasks
can receive messages from a message queue (if it is nonempty). Queues can
use a FIFO (First In, First Out) policy or it can be based on priorities. Message
queues provide an asynchronous communications protocol.

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20. Define Mailbox and Pipe. (CO4-L1)


A mailboxes are software-engineering components used for interprocess
communication, or for inter-thread communication within the same process. A
mailbox is a combination of a semaphore and a message queue (or pipe).
Message queue is same as pipe with the only difference that pipe is byte
oriented while queue can be of any size.

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PART-B

1. Discuss about the concepts of process with neat diagram. (CO4-L1-


APRIL/MAY 2016-)
Process Concepts
A process consists of executable program (codes), state of which
is controlled by OS, the state during running of a process
represented by process-status (running, blocked, or finished),
process structure—its data, objects and resources, and process
control block (PCB).
Runs when it is scheduled to run by the OS (kernel)
OS gives the control of the CPU on a process‘s request (system call).
Runs by executing the instructions and the continuous
changes of its state takes Place as the program counter
(PC) changes.
Process is that executing unit of computation, which is
controlled by some process (of the OS) for a scheduling
mechanism that lets it execute on the CPU and by some
process at OS for a resource management mechanism that
lets it use the system- memory and other system
resources such as network, file, display or printer.

Application program can be said to consist of number of processes


Example - Mobile Phone Device embedded software
Software highly complex.
Number of functions, ISRs, processes threads, multiple physical
and virtual device drivers, and several program objects that must
be concurrently processed on a single processor.
Voice encoding and convoluting process─ the device captures the
spoken words through a speaker and generates the digital signals
after analog to digital conversion, the digits are encoded and
convoluted using a CODEC,
Modulating process,
Display process,
GUIs (graphic user interfaces), and

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Key input process ─ for provisioning of the user interrupts

Process Control Block

A data structure having the information using which the


OS controls the Process state.
Stores in protected memory area of the kernel.
Consists of the information about the process state

Information about the process state at Process Control Block…

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Process ID,
process priority,
parent process (if any),
child process (if any), and
address to the next process PCB which will run,
allocated program memory address blocks in physical memory and in
secondary (virtual) memory for the process-codes,
allocated process-specific data address blocks
allocated process-heap (data generated during the program run)
addresses,
allocated process-stack addresses for the functions called
during running of the process,
allocated addresses of CPU register-save area as a process
context represents by CPU registers, which include the program
counter and stack pointer
allocated addresses of CPU register-save area as a process
context [Register-contents (define process context) include the
program counter and stack pointer contents]
process-state signal mask [when mask is set to 0 (active) the
process is inhibited from running and when reset to 1, the process
is allowed to run],
Signals (messages) dispatch table [process IPC functions],
OS allocated resources‘ descriptors (for example, file descriptors
for open files, device descriptors for open (accessible) devices,
device-buffer addresses and status, socket- descriptor for open
socket), and
Security restrictions and permissions.

Context

Context loads into the CPU registers from memory when process
starts running, and the registers save at the addresses of register-
save area on the context switch to another process
The present CPU registers, which include program counter and
stack pointer are called context
When context saves on the PCB pointed process-stack and
register-save area addresses, then the running process

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stops.Other process context now loads and that process runs─


This means that the context has switched.

2. Explain the concept of Threads and Tasks. (CO4-L2- APRIL/MAY 2016)


Thread Concepts
A thread consists of executable program
(codes), state of which is controlled by OS,
The state information─ thread-status (running, blocked, or finished),
threadstructure—its data, objects and a subset of the process
resources, and thread-stack. Considered a lightweight process and a
process level controlled entity.[Light weight means its running does
not depend on system resources] .

Process… heavyweight
• Process considered as a heavyweight process and a kernel-level
controlled entity.
• Process thus can have codes in secondary memory from
which the pages can be swapped into the physical primary
memory during running of the process. [Heavy weight means
its running may depend on system resources]
• May have process structure with the virtual memory
map, file descriptors, user–ID, etc.
• Can have multiple threads, which share the process structure
thread
• A process or sub-process within a process that has its own
program counter, its own stack pointer and stack, its own
priority parameter for its scheduling by a thread scheduler
• Its variables that load into the processor registers on context
switching.
• Has own signal mask at the kernel. Thread‘s signal mask
• When unmasked lets the thread activate and run.
• When masked, the thread is put into a queue of pending threads.
• A thread stack is at a memory address block allocated by the
OS.

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Application program can be said to consist of number of


threads or Processes:

Multiprocessing OS

• A multiprocessing OS runs more than one processes.


• When a process consists of multiple threads, it is
called multithreaded process.
• A thread can be considered as daughter process.
• A thread defines a minimum unit of a multithreaded process
that an OS schedules onto the CPU and allocates other system
resources.

Thread parameters

• Each thread has independent parameters ID, priority,


program counter, stack pointer, CPU registers and its
present status.
• Thread states─ starting, running, blocked (sleep) and finished

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Thread’s stack


When a function in a thread in OS is called, the calling function
state is placed on the stack top.
• When there is return the calling function takes the state
information from the stack top
• A data structure having the information using which the OS
controls the thread state.
• Stores in protected memory area of the kernel.
• Consists of the information about the thread state
Thread and Task


Thread is a concept used in Java or Unix.

A thread can either be a sub-process within a process or
a process within an application program.
• To schedule the multiple processes, there is the concept of
forming thread groups and thread libraries.
• A task is a process and the OS does the multitasking.
• Task is a kernel-controlled entity while thread is a process-
controlled entity.
• A thread does not call another thread to run. A task also
does not directly call another task to run.
• Multithreading needs a thread-scheduler. Multitasking also
needs a task-scheduler.
• There may or may not be task groups and task libraries in a
given OS
Task and Task States Task Concepts
• An application program can also be said to be a program
consisting of the tasks and task behaviors in various states that
are controlled by OS.
• A task is like a process or thread in an OS.
• Task─ term used for the process in the RTOSes for the
embedded systems. For example, VxWorks and μCOS-
II are the RTOSes, which use the term task.
• A task consists of executable program (codes), state of which
is controlled by OS, the state during running of a task
represented by information of process status (running,
blocked, or finished),process-structure—its data, objects and

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resources, and task control block (PCB).


• Runs when it is scheduled to run by the OS (kernel), which
gives the control of the CPU on a task request (system call) or
a message.
• Runs by executing the instructions and the continuous
changes of its state takes place as the program counter
(PC) changes.
• Task is that executing unit of computation, which is controlled
by some process at the OS scheduling mechanism, which lets
it execute on the CPU and by some process at OS for a
resource-management mechanism that lets it use the system
memory and other system-resources such as network, file,
display or printer.
• A task─ an independent process.
• No task can call another task. [It is unlike a C (or C++)
function, which can call another function.]
• The task─ can send signal (s) or message(s) that can let another
task run.
• The OS can only block a running task and let another task
gain access of CPU to run the servicing codes
Task States
 Idle state [Not attached or not registered]
 Ready State [Attached or registered]
 Running state
 Blocked (waiting) state
 Delayed for a preset period
Idle (created) state
• The task has been created and memory allotted to
its structure however, it is not ready and is not
schedulable by kernel.

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Ready (Active) State


• The created task is ready and is schedulable by the
kernel but not running at present as another higher
priority task is scheduled to run and gets the system
resources at this instance.
Running state
• Executing the codes and getting the system resources at this
instance. It will run till it needs some IPC (input) or wait for an
event or till it gets pre-empted by another higher priority task
than this one.
Blocked (waiting) state
• Execution of task codes suspends after saving the needed
parameters into it Context. It needs some IPC (input) or it needs
to wait for an event or wait for higher
Priority task to block to enable running after blocking.
Deleted (finished) state
• Deleted Task─ The created task has memory deallotted to its
structure. It frees the memory. Task has to be re-created.
Function
• Function is an entity used in any program, function, task or
thread for performing specific set of actions when called and
on finishing the action the control returns to the function calling
entity (a calling function or task or process or thread).
• Each function has an ID (name)
• has program counter and
• has its stack, which saves when it calls another function and
the stack restores on return to the caller.
• Functions can be nested. One function call another, that can
call another, and so on and later the return is in reverse order

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3. Explain the basic concepts of RTOS. What are the different types of RTOS?
Explain the features of Micro OS-II. (CO4-L2- APRIL/MAY 2016)
Kernel of an RTOS
• Used for real-time programming features to meet hard and soft real time
constraints,
• Provides for preemption points at kernel, user controlled dynamic priority
changes, fixed memory blocks, asynchronous IOs, user processes in kernel
space and other functions for a system.

Complex multitasking embedded system design requirements

 Integrated Development Environment,


 Multiple task functions in Embedded C or Embedded C++,
 Real time clock─ hardware and software timers,
 Scheduler,
 Device drivers and device manager,
 Functions for inter inter-processcommunications using the signals,
event flag group, semaphore- handling functions, functions for the
queues, mailboxes, pipe, and sockets,
 Additional functions for example, TCP/IP or USB port, other networking
functions,
 Error handling functions and Exception handling functions, and
 Testing and system debugging software for testing RTOS as well as
developed embedded application

Basic functions expected from kernel of an RTOS


RTOS features in general

 Basic kernel functions and scheduling: Preemptive or Preemptive plus


time slicing
 Support to Limited Number of tasks and threads
 Task priorities and Inter Service Threads priorities definitions
 Priority Inheritance feature or option of priority ceiling feature
 Task synchronization and IPC functions
 Support to task and threads running in kernel space

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 IDE consisting of editor, platform builder, GUI and graphics software,


compiler, debugging and host target support tools
 Device Imaging tool and device drivers
 Clock, time and timer functions,
 Support to POSIX,
 Asynchronous IOs,
 Fixed memory blocks allocation and de allocation system,
 Support to different file systems and flash memory systems
 TCP/IP protocols, network and buses protocols,
 Development environment with Java
 Componentization (reusable modules for different functions), which
leads to small foot print (small of size of RTOS codes placed in ROM
image)
 Support to number of processor architectures ,such as INTEL, ARM,
Philips, …

Development Approaches

Host and Target Based Development Approach:

 A host machine (Computer) for example, a PC uses a general


purpose OS, for example, Windows or Unix for system development.
The target connects by a network protocol for example TCP/IP
during the development phase. The developed codes and the target
RTOS functions first connect a target. The target with downloaded
codes finally disconnects and contains a small size foot print of
RTOS. For example, the target does not download host machine
resident compiler, cross compiler, editor for programs, simulation
and debugging programs, and MMU support.

Self-host Based Development Approach:


 Same system with full RTOS is used for development on which the
application will be running. This also does not require cross
compilation. When application codes are ready, the required RTOS
functions codes and application codes are downloaded into the ROM
of the target board

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Types of RTOSes

1. In-House Developed RTOSes


2. Broad based Commercial RTOSes
3. General Purposes OSes with RTOS
4. Special Focus RTOSes

μC/OS-II System level and taskFunctions

 void OSInit (void)At the beginning prior to the OSStart( )


 void OSStart (void)After OSInit ( ) and task-creating function(s)
 void OSTickInit (void)In first task function that executes
once.Initializes the system timer ticks (RTCinterrupts)

4. Write the fifteen point strategy for synchronization between the ISRs, OS
functions and tasks for resource management.
ISR
• ISR is a function called on an interrupt from an interrupting source.
• Further unlike a function, the ISR can have hardware and
software assigned priorities.
• Further unlike a function, the ISR can have mask, which inhibits
execution on the event, when mask is set and enables execution
when mask reset.

TASK
Task defined as an executing computational unit that processes on a
CPU and state of which is under the control of kernel of an operating
system.
Distinction Between Function, ISR and Task Uses
• Function─ for running specific set of codes for performing a
specific set of actions as per the arguments passed to it
• ISR─ for running on an event specific set of codes for
performing a specific set of actions for servicing the interrupt

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call.
Task ─ for running codes on context switching to it by OS and

the codes can be in endless loop for the event (s)
Calling Source

• Function─ call from another function or process or thread or task.


• ISR─ interrupt-call for running an ISR can be from hardware
or software at any Instance.
• Task ─ A call to run the task is from the system (RTOS).
RTOS can let another higher priority task execute after
blocking the present one. It is the RTOS (kernel) only that
controls the task scheduling.
Context Saving

• Function─ run by change in program counter instantaneous


value. There is a stack. On the top of which the program
counter value (for the code left without running) and other
values (called functions‘ context) save.
• All function have a common stack in order to support the nesting
• ISR─ Each ISR is an event-driven function code. The code run
by change in program counters instantaneous value. ISR has a
stack for the program counter instantaneous value and other
values that must save.
• All ISRs can have common stack in case the OS supports
nesting
• Task ─ Each task has a distinct task stack at distinct memory
block for the context (program counter instantaneous value and
other CPU register values in task control block) that must save .
• Each task has a distinct process structure (TCB) for it at distinct
memory block
Structure

• Function─ can be the subunit of a process or thread or task


or ISR or subunit of another function.
• ISR─ Can be considered as a function, which runs on an
event at the interrupting source.
• A pending interrupt is scheduled to run using an interrupt

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handling mechanism in the OS, the mechanism can be


priority based scheduling.
• The system, during running of an ISR, can let another higher
priority ISR run.
• Task ─ is independent and can be considered as a function,
which is called to run by the OS scheduler using a context
switching and task scheduling mechanism of the OS.
• The system, during running of a task, can let another higher
priority task run. The kernel manages the tasks scheduling

Global Variables Use

• Function─ can change the global variables. The interrupts


must be disabled and after finishing use of global variable
the interrupts are enabled.
• ISR─ When using a global variable in it, the interrupts must
be disabled and after finishing use of global variable the
interrupts are enabled (analogous to case of a function).
• Task ─ When using a global variable, either the interrupts are
disabled and after finishing use of global variable the
interrupts are enabled or use of the semaphores or lock
functions in critical sections, which can use global variables
and memory buffers.

Posting and Sending Parameters

• Function─ can get the parameters and messages through the


arguments passed to it or global variables the references to
which are made by it. Function returns the results of the
Operations.
• ISR─ using IPC functions can send (post) the signals, tokens
or messages. ISR can‘t use the mutex protection of the critical
sections by wait for the signals, tokens or messages.

• Task ─ can send (post) the signals and messages.


• can wait for the signals and messages using the IPC functions,
can use the mutex or lock protection of the code section by wait

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for the token or lock at the section beginning and messages


and post the token or unlock at the section end.
Semaphore as an event signalling variable or notifying variable

• Suppose that there are two trains.


• Assume that they use an identical track.
• When the first train A is to start on the track, a signal or
token for A is set (true, taken) and
• same signal or token for other train, B is reset (false, not
released).

OS Functions for Semaphore as an event signalling variable or


notifying variable:


OS Functions provide for the use of a semaphore for
signalling or notifying of certain action or notifying the
acceptance of the notice or signal.
• Let a binary Boolean variable, s, represents the semaphore.
The taken and post operations on s─ (i)signals or notifies
operations for communicating the occurrence of an event and
(ii) for communicating taking note of the event.
• Notifying variable s is like a token ─ (i) acceptance of the
token is taking note of that event (ii) Release of a token is the
occurrence of an event
Binary Semaphore
• Let the token (flag for event occurrence) s initial value = 0
• Assume that the s increments from 0 to 1 for signalling or
notifying occurrence of an event from a section of codes in a
task or thread.
• When the event is taken note by section in another task waiting
for that event, the s
decrements from 1 to 0 and the waiting task codes start another
action.
• When s = 1─ assumed that it has been released (or sent or
posted) and no task code section has taken it yet.
• When s = 0 ─ assumed that it has been taken (or accepted) and
other task code
• section has not taken it yet

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Binary Semaphore use in ISR and Task


• An ISR can release a token.
• A task can release the token as well accept the token or wait for
taking the token
Device Management Functions
Number of device driver ISRs in a system,
Each device or device function having s a separate driver, which is as
per its hardware
Software that manages the device drivers of each device
Provides and executes the modules for managing the devices and their
drivers ISRs.
effectively operates and adopts appropriate strategy for obtaining optimal
performance for the devices.
Coordinates between application-process, driver and device-controller.
Device manager
Process sends a request to the driver by an interrupt; and the driver
provides the actions by executing an ISR.
Device manager polls the requests at the devices and the actions occur as
per their priorities.
Manages IO Interrupts (requests) queues.
creates an appropriate kernel interface and API and that activates the
control register specific actions of the device. [Activates device controller
through the API and kernel interface.]
manages the physical as well as virtual devices like the pipes and sockets
through a common strategy.
Device management has three standard approaches
Three types of device drivers:
(i) Programmed I/Os by polling from each device its the service need from
each device.
(ii) Interrupt(s) from the device drivers‘ device- ISR and
(iii) Device uses DMA operation used by the devices to
access the memory. Most common is the use of device
driver ISRs

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Device Manager Functions


Device Detection and Addition
Device Deletion
Device Allocation and
Registration
Detaching and Deregistration
Restricting Device to a specific process
Device Sharing
Device control
Device Access Management
Device Buffer Management
Device Queue, Circular-queue or blocks of queues Management
Device drivers updating and upload of new device-functions
Backup and restoration
Device Types
char devices and
block devices

Set of Command Functions for the Device


Management Commands for Device
create
open
write
read
ioctl
close and
delete

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5. Explain RTOS system level functions with an example MUCOS has system
level functions. These are for RTOS initiation and start, RTC ticks initiation and
the ISR enter and exit functions. (CO4-L2- APRIL/MAY 2016).
Functions in this table pass no arguments and return type is void.
There is a global variable,OslntNesting.which increments on entering ISR.Global
variable OSlntNesting decrements on'exit"from an ISR. Initiating the operating $)stem
before
starting the use of the RTOS functions
􏂷 Function void OSInit (void) operating system.
􏂷 Its use is compulsory before functions.
􏂷 It returns no parameter.
Starting use of RTOS multitasking functions and returning the tasks
􏂷 Function void OSStart(void) is used to start the initiated operating system and
create tasks.
􏂷 Its use is compulsory for the multitasking OS kernel operations.
􏂷 It returns no parameter.
Starting the RTOS System clock
􏂷 Function void OsTicklnit(void) is used to initiate the system clock ticks and
interrupts at regular intervals as per OS_TICKS_PER_SEC predefined during
configuring the
MUCOS.
􏂷 Its use is compulsory for the multitasking OS kernel operations when the timer
functions ane to be used.
􏂷 It returns no parameter.
Sending message to RTOS taking control al the start of an ISR
􏂷 Function void OSlntEnter(void) is used at the start of an ISR.
􏂷 It is for sending a message to RTOS kernel for taking control. Its use is
compulsory to let the multitasking OS kernel, control the nesting of the ISRs in case of
occurrences of multiple interrupts of varying priorities.
􏂷 It returns no parameter.

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6. Explain the RTOS programming tool MicroC/OS-II. (CO4-L2- APRIL/MAY 2016).


MicroC/O$II (commonly termed PC/O$II or mC/OSi-il), is a low-cost priories-based
pieemptive real time multitasking operating system kernel for microprocessors, written
mainly in
the C fodarnming language. It is mainly intended for use in embedded systems.
Ports
It has ports for most popular processors and boards in the market and is suitable for use
in safety critical embedded systems such as aviation, medical systems and nuclear
installations.
Task states
pC/OS-[ is a multitasking operating system. Each task is an infinite loop and can be in
any one of the following 5 states:
􏂷 Dormant

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􏂷 Ready
􏂷 Running
􏂷 Waiting
􏂷 ISR
Source files
There are two types of source files.
Master header files includes the #include preprocessor commands for all the files of
both types. It is referred to as include.h file Preprocessor dependent

7. Explain the features of Vx Works. (CO4-L2- APRIL/MAY 2016).


VxWorks is a Unix-like real-time operating system made and sold by Wind River
Systems of Alameda, California" USA. Like most RTOSes, VxWorks includes a
multitasking
kernel with pre-emptive scheduling and fast interrupt response, extensive inter-process

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communications and synchronization facilities, and a file system Major distinguishing


features of VxWorks include efficient POSlX-compliant memory management,
microprocessor facilities, a shell for user interface, symbolic and source level debugging
capabilities, and performance monitoring. VxWorks is generally used in embedded
systems. Unlike "native" systems such as UNIX and Forth, VxWorks development is
done on a "host" machine running Unix or Windows, crosscompiling target software to
run on various "target" CPU architectures as well as on the "host" by means of VxSim.
VxWorks has been ported to a number of platforms and now runs on practically any
modern CPU that is used in the embedded market. This includes the x 86 families,
MIPS, PowerPC, SH-4 and the closely related family of ARM, StrongARM and xScale
CPUs
VxWorks System Functions and System Tasks
The first task that a scheduler executes is UsrRoot from the entrv point of usrRoot0 in
file install/Dir/target /config/alI / usr/Confi g. c. It spawns the VxWorks tools and the
following tasks. The root terminates after all the initializations. Any root task can be
initialized or terminated. The set of functions, tlog Task, logs
the system message without current task context I/O.
Interrupt handling functions
An internal hardware device auto generates an interrupt vector address, ISR-
ECTADDR as per the device. Exceptions are defined in the us6r software.
ISR Design
􏂷 ISR have the highest priority and can preempt any running task.
􏂷 An ISR inhibits the execution of the tasks till return’.
􏂷 An IRS does not execute like a task and does not have regular task context. It has
special interrupt context'
􏂷 While each task has its own stack" unless and otherwise not permitted -by a
special architecture of a System or a processor
􏂷 An ISR should not wait for taking the semaphore or other IPC.
􏂷 ISR should just write the required data at the memory or post an IPC so that it has
short codes and most of its functions, execute at tasks.
􏂷 ISR should not use flodting-point functions as these takes longer time to execute.
Signals and interrupt handling functions
Function 'void sigHandler(int sigNum)' declares a signal servicing routine for a signal
identified by sigNum and a signal servicing routine registers a signal as follows:
Signal (sigNum, sigISR). The parameters that pass are the sigNum and signal servicing
routine name, sigISR.A pointwer pSigCtx associates with the signal context. The signal
xcontewxt savwes PC, SP, registers, etc. like an ISR context.
The signal ISR calls the following functions:

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􏂷 Call taskRestart0, to restart the task which generated the sigNum.


􏂷 Call exit0 to terminate the task, which generated the sigNum.
􏂷 Call longiumpO. This results in starting the. Execution from a memory location.

8. Explain the use of Semaphores for a Task or for the Critical Sections of a Task.
Use of a Single Semaphore. (CO4-L2).
Semaphore provides a mechanism to let a task wait till another finishes. It is a way of
synchronizing concurrent process operations. When a semaphore is 'taken' by a task,
then that task has to access to the necessary resources; when given, the resources
unlock. Semaphore can be used as an event flag or as a resource key. Resource key is
one that permits use of resources like CPU, memory or other functions or critical section
codes Semaphore, which is a binary Boolean variable (or it is a signaling variable or
notifying variable.)Used as event flag. Semaphore is called binary semaphore when its
value is 0 and it is assumed that it has Boolean taken. When its value is l, it is assumed
that no task has taken it and that it has been released.

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Use of Multiples Semaphores


Consider two semaphores. A task I when executing a critical section notifies the os to
take the semaphore. os returns information that the semaphore has been taken to l and
M. Now,
the task I executes the codes of the critical. The OS having been notified about a take
semaphore
x from I, does not take and OS does not release the o task J and M' But the os returns
an semaphore at an instance.
Use of Mutex
Mutex is a semaphore that gives at an instance two tasks mutually exclusive access to
resources. Use of mutex facilitates mutually exclusive access by two or more process to
the
resource (CPU). The same’ variable, sem_m, is shared between the various processes.
Let

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process and process 2 share sem_m and its initial value = l.


i) Process’s 1 proceeds after sem_m decreases and equals 0 and gets the exclusive
access
to the CPU.
ii) Process I ends after sem_m increases and equals l; process 2 can now gets
exclusive access to the CPU.

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Unit-V
Embedded System Application Development
Part-A
1. Define smart card?(CO5-L1)
Smart card is one of the most used embedded systems today. It is used for
credit, debit bank card, e-wallet card, identification card, medical card (for history
and diagnosis details) and card for a number of new innovative applications
2. What are the hardware units needed to design smart card. (CO5-L1)

 Microcontroller or ASIP
 RAM for temporary variables and Stack
 OTP ROM for application codes and RTOS codes for scheduling the tasks
 Flash for storing user data, user address, user identification codes, card number
and expiry date
 Timer and interrupt controller
 A carrier frequency generating circuit and ASK modulator
 Interfacing circuit for the IOs.
 Charge pumps for delivering power to the antenna for transmission and for the
system circuits.

3. What are the Software units needed to design smart card. (CO5-L1)

 Boot-up, initialization and OS program


 Smart card secure file system
 Connection establishment and termination
 Communication with the host
 Cryptography algorithm
 Host authentication
 Card authentication
 Saving addition parameters or recent new data sent by the host(ex-balance
receipt)

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4. Design the architectural hardware units needed in smartcard. (CO5-H3)

5. Recommend the tasks for smartcard. (CO5-H3)

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6. What are the hardware units needed to design Washing machine. (CO5-L1)
Buttons, Display & buzzer, electronic circuitry.
7. What are the software units needed to design Washing machine. (CO5-L1)
It has a chip on the circuit that holds the software which drives controls &
monitors the various operations possible.

8. Write the different modes in working of washing machine. (CO5-L1- APRIL/MAY


2016)
i) Fully Automatic Mode
ii) Semi Automatic Mode:
iii) Manual Mode:

9. List out the components of washing machine. (CO5-L1)


i) Display Panel
ii) Sensor
iii) Driving Motor
iv) System Controller
V) Water pum
10. Mention the types of washing machine. (CO5-L1)
Front loading,Top loading
11. What are the types of ECU? (CO5-L1- APRIL/MAY 2016-)
1. High-speed Electronic Control Units (HECUs)
2. Low-speed Electronic Control Units (LECUs)

12. What is meant by CAN? (CO5-L1)


CAN bus was originally proposed by Robert Bosch.
It supports medium speed and high speed data
transfer

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CAN is an event driven protocol interface with support


for error handling in data transmission.

13.What do meant by LIN? (CO5-L1)


LIN bus is single master multiple slave communication interface with support
for
data rates up to 20 Kbps and is used for sensor/actuator interfacing

14. Describe about MOST. (CO5-L1)


MOST is targeted for automotive audio/video equipment interfacing
A MOST bus is a multimedia fiber optics point–topoint network implemented
in
a star , ring or daisy chained topology over optical fiber cables.
MOST bus specifications define the physical as well as application layer ,
network layer and media access control.

15. Mention the uses of embedded controller. (CO5-L1)


a. Air Conditioner
b. Engine Control
c. Fan Control
d. Headlamp Control
e. Automatic break system control
f. Wiper control
g. Air bag control
h. Power Windows

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PART-B

1. Explain in detail about the working of washing machine.( CO5-L2- APRIL/MAY


2016)
Washing machine supports three functional modes:
i) Fully Automatic Mode: In fully automatic mode, once the system is started it
perform independently without user interference and after the completion of work it
should notify the user about the completion of work. This mode instantaneously sense
cloth quality and requirement of water, water temperature, detergent, load, wash cycle
time and perform operation accordingly.
ii) Semi Automatic Mode:
In this semiautomatic mode in which washing conditions are predefined. Once the
predefined mode is started the system perform its job and after completion it inform the
user about the completion of work.
iii) Manual Mode:
In this mode, user has to specify which operation he wants to do and has to provide
related information to the control system. For example, if user wants to wash clothes
only, he has to choose ‘wash’ option manually. Then the system ask the user to enter
the wash time, amount of water and the load. After these data are entered, the user
should start the machine. When the specified operation is completed system should
inform the user. Remember that Modes should be a selectable by a keypad.
A washing machine may have a System Controller (Brain of the System) which
provides the power control for various monitors and pumps and even controls the
display that tells us how the wash cycles are proceeding. A washing machine
comprise several components as shown in Figure
The working of these components is as follows:
i) Display Panel:
It is a touch panel screen to control all the operations of a machine
ii) Sensor:
It measures the water level and appropriate amount of soap. Input devices
for automatic washing machine are sensors for water flow, water level and
temperature; door switch; selector knob or buttons for settings such as spin speed,

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temperature, load size and types of wash cycle required.


Water Level Sensor: It indicates beep sound when water level is low in washing tub.
Door Sensor: It indicates beep sound when all clothes are washed that means now
you can open the maching door and also you can move to your next phase. Next phase
will be dry Phase. This phase also follows same concept for drying the clothes.
iii) Driving Motor:
Motor can rotate in two directions either “reverse’ or ‘forward’.
The forward direction drives the current in forward direction and motor rotates
forward. The reverse direction driver does the opposite of it. A washing machine
can maintain single motor in fully automatic or double motor in semi automatic
washing machine.

Sequence of washing the clothes with this can be explained in few steps as follows:

1) Put on your dirty clothes on to the wash tub for washing

2) Put the detergent Soap (of your choice like Surf n Excel etc.)
3) Put ON the tap, water rushes inside the tub. Embedded Systems
4) If its electronic control , then by the press of the keys ,you could program , if its
mechanical it shall something like an mechanical switches wherein you are allowed to
operate for setting the wash time.
5) Now the wash motor rotates and washes the clothes and gives you a beep sound
6) Now your clothes are washed …remove it from the wash tub and put it on the spin
tub and program it accordingly…after spinning clothes are dried and you
are allowed to hang it for proper drying in sunlight.

The fully automatic also comes in two category front loading as well as top loading.
i) Front loading is the one wherein you are given an opening to put clothes in on the
front side.
ii) Top loading is on the top.
iv) System Controller: Such Component is used to control the motor speed. Motor
can move in forward direction as well as reverse direction.
System Controller reads the speed of motor and controls the speed of motor in
different phases such as in Washing, Cleaning Drying etc. All kinds of Sensors
such as Door Sensor, Pressure Sensor and Keypad, Speed sensor are also
maintained by this.

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v) Water Pump: The water pump is used to recirculate


water and drain out the dirty water. This pump actually contains two separate pumps
inside one: The bottom half of the pump is hooked up to the drain line, while the top half
recirculates the wash water. The motor that drives the pump can reverse direction.
It spins one way when the washer is running a wash cycle and recirculates
The water; and it spins the other way when the washer is doing a spin cycle and
draining the water

2. Write a brief note on Automotive Embedded System (AES). (CO5-L2-


APRIL/MAY 2016)
The Automotive industry is one of the major application domains of embedded
systems.
Automotive embedded systems are the one where electronics take control over the
mechanical system. Ex. Simple viper control.
The number of embedded controllers in a normal vehicle varies somewhere between
20 to 40 and can easily be between 75 to 100 for more sophisticated vehicles.
One of the first and very popular use of embedded system in automotive industry
was microprocessor based fuel injection.
Some of the other uses of embedded controllers in a vehicle are listed below:
a. Air Conditioner
b. Engine Control
c. Fan Control
d. Headlamp Control
e. Automatic break system control
f. Wiper control
g. Air bag control
h. Power Windows
AES are normally built around microcontrollers or DSPs or a hybrid of the two and
are generally known as Electronic Control Units (ECUs).
Types Of Electronic Control Units(ECU)
1. High-speed Electronic Control Units (HECUs):
a. HECUs are deployed in critical control units
requiring fast response.
b. They Include fuel injection systems, antilock brake systems, engine control, electronic
throttle, steering controls, transmission control and central control units.
2. Low Speed Electronic Control Units (LECUs):-
a. They are deployed in applications where response time is not so critical.

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b. They are built around low cost microprocessors and microcontrollers and digital
signal processors.
c. Audio controller, passenger and driver door locks, door glass control etc.
Automotive Communication Buses
Embedded system used inside an automobile communicate with each other using serial
buses. This reduces the wiring required. Following are the different types of serial
Interfaces used in automotive embedded applications:
a. Controller Area Network (CAN):-
CAN bus was originally proposed by Robert Bosch.
It supports medium speed and high speed data transfer
CAN is an event driven protocol interface with support
for error handling in data transmission.
b. Local Interconnect Network (LIN):-
LIN bus is single master multiple slave communication interface with support for data
rates up to 20 Kbps and is used for sensor/actuatorinterfacing
LIN bus follows the master communication triggering to eliminate the bus arbitration
problem
LIN bus applications are mirror controls , fan controls seat positioning controls
c. Media-Oriented System Transport(MOST):-
MOST is targeted for automotive audio/video equipment interfacing
A MOST bus is a multimedia fiber optics point–topoint network implemented in a star
ring or daisy chained topology over optical fiber cables.
MOST bus specifications define the physical as well as application layer , network
layer and media access control.

3. Design architectural hardware and software units needed in smart card.( CO5-
H3- APRIL/MAY 2016)

Smart card is one of the most used embedded systems today. It is used for
credit, debit bank card, e-wallet card, identification card, medical card (for history
and diagnosis details) and card for a number of new innovative applications.

EMBEDDED HARDWARE COMPONENTS

 Microcontroller or ASIP
 RAM for temporary variables and Stack

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S.K.P. Engineering College, Tiruvannamalai VI SEM

 OTP ROM for application codes and RTOS codes for scheduling the tasks
 Flash for storing user data, user address, user identification codes, card number
and expiry date
 Timer and interrupt controller
 A carrier frequency generating circuit and ASK modulator
 Interfacing circuit for the IOs.
 Charge pumps for delivering power to the antenna for transmission and for the
system circuits.
EMBEDDED SOFTWARE COMPONENTS

 Boot-up, initialization and OS program


 Smart card secure file system
 Connection establishment and termination
 Communication with the host
 Cryptography algorithm
 Host authentication
 Card authentication
 Saving addition parameters or recent new data sent by the host(ex-balance
receipt)

Class diagram

Smart card hardware

Electrical and Electronics Engineering Department 113 Embedded Systems


S.K.P. Engineering College, Tiruvannamalai VI SEM

A plastic card in ISO standard dimensions, 85.60 mm x 53.98 x 0.80mm. It is an


embedded SOC (System-On-Chip). [ISO standards - ISO7816 (1 to 4) for host-machine
contact based card and
ISO14443 (Part A or B) for the contactless cards.] Microcontroller MC68HC11D0 or
PIC16C84 or a smart card processor Philips Smart XA or an ASIP Processor. Needs 8
kb+ internal RAM and 32 kb EPROM and 2/3 wire protected memory. CPU special
features, for example, a security lock. CPU locks certain section of memory -protect 1
kb or more data from modification and access by any external source or instruction
outside that memory. Other way of protecting - CPU access through the physical
addresses, which are different from logical address used in the program. Standard ROM
8 kb for usual or 64 kb when using advanced cryptographic features. Full or part of
ROM bus activates take place after a security check only.
ROM Contains:
i. Fabrication key and Personalization key (after insertion of this key, RTOS and
application use only the logical addresses)
ii. RTOS codes
iii. Application codes
iv. Utilization lock
EEPROM or Flash
scalable – only needed part unlocks when storing P.I.N., unlocking P.I.N., access
condition, card-user data, post activation application run generated non-volatile data,
invalidation lock to invalidate card after the expiry date or server
• RAM – run time temporary variables
• Chip-supply system using charge pump• I/O system i

Tasks and their synchronization model

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on

SOFTWARE ARCHITECTURE
Needs cryptographic software, needs special features in its operating system
over and above the MS DOS or UNIX system features. Protected environment -OS
stored in the protected part of ROM.
• A restricted run-time environment.
• OS, every method, class and run time library should be scalable,
Optimum Code-size
• Limited use of data types; multidimensional arrays, long 64-bitinteger and floating
points and very limited use of the error handlers, exceptions, signals, serialization,
debugging and profiling. Three-layered file system for the data
• Master file to store all file headers (file status, access conditions and the file lock) A
header means file status, access conditions and the file lock.
• Dedicated file─ second file to hold a file grouping and headers of the immediate
successor• Elementary file ─ third file to hold the file header and its file data. Either a
fixed length file management or a variable file length management with each file with a
predefined offset.

Electrical and Electronics Engineering Department 115 Embedded Systems