Middle Technical University

Electrical Engineering Technical college

8086 Microprocessor
Interfacing
Lecture No.3
Mohammed D. Ali
3rd stage
2018-2019

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 Programmable Interval Timer
8253 (PIT)
• What is 8253?
• The Intel 8253 is a programmable counter/timer chip
designed for use as an Intel microcomputer peripheral.
• It is packaged in a 24-pin plastic DIP.
• Six programmable timer modes allow the 8253 to be used
as:
an event counter.
elapsed time indicator.
programmable one-shot.
in many other applications e.g., to create different
intervals.
• It has 3 counters, [Counters 0, 1, 2].

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Block Diagram of the 8253

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Block Diagram of the 8253
• Data Bus Buffer:
• The 3-state, bi-directional, 8-bit
buffer is used to interface the
8253 to the system data bus.
• Data is transmitted or received
by the buffer upon execution of
IN or OUT CPU instructions.
• The Data Bus Buffer has three
basic functions.
1. Programming the MODES of the
8253.
2. Loading the count registers.
3. Reading the count values.

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Block Diagram of the 8253
• Read/Write Logic:
• The Read/Write Logic accepts
inputs from the system bus and
in turn generates control signals
for overall device operation.
• It is enabled or disabled by 𝐶𝑆
so that no operation can occur
to change the function unless
the device has been selected by
the system logic.

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Block Diagram of the 8253
• Control Word Register:
• The Control Word Register is
selected when A0A1 = 11.
• It then accepts information
from the data bus buffer and
stores it in a register.
• The information stored in this
register controls the operation
MODE of each counter,
selection of binary or BCD
counting and the loading of
each count register.
• The Control Word Register can
only be written into; no read
operation of its contents.

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Block Diagram of the 8253
• Counter 0, Counter 1, Counter # 2:
• Each Counter consists of a single, 16-bit, pre-
settable, DOWN counter.
• The counters can operate in either binary or
BCD and its input, gate and output are
configured by the selection of MODES stored
in the Control Word Register.
• The counters are fully independent and each
can have separate MODE configuration and
counting operation, binary or BCD.
• There are special features in the control word
that handle the loading of the count value so
that software overhead can be minimized for
these functions.
• The reading of the contents of each counter
is available to the programmer with simple
READ operations so that the contents of each
counter can be read "on the fly" without
having to inhibit the clock input.
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Table 2: Description of basic operations of the 8253.

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Pin Description of the 8253

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Pin Description of the 8253
• D7-0 (Bidirectional Data Bus):
• Three state, 8-bit bidirectional
data bus used when writing
control words and count values,
and reading count values upon
reception of 𝑊𝑅 and RD signals
from CPU.

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Pin Description of the 8253
• CS (Chip Select):
• Data transfer with the CPU is
enabled when this pin is at low
level CS = 0.
• When CS = 1, the data bus (D0
thru D7) is switched to high
impedance state.
[no writing, no reading can be
executed].
• Internal registers, however,
remain unchanged.

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Pin Description of the 8253
• RD (Read Input):
• Data can be transferred from
the 8253 to CPU when this pin is
at low level.
• WR (Write Input):
• Data can be transferred from
CPU to 8253 when this pin is at
low level.

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Pin Description of the 8253
• A1-0 (Address Input):
• One of the three
internal counters or the
control word register is
selected by A0/A1
combination.
• These two pins are
normally connected to
the two lower order bits
of the address bus.

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Pin Description of the 8253
• CLK0-2 (Clock Input):
• Supply of three clock signals to
the three counters incorporated
in 8253.
• GATE0-2 (Gate Input):
• Control of starting,
interruption, and restarting of
counting in the three respective
counters in accordance with the
set control word contents.
• OUT0-2 (Counter Out):
• Output of counter output
waveform in accordance with
the set mode and count value.
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Table 1: Pin description of the 8253.

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Operation Modes of the 8253
• Each one of the three counters can be
configured to operate in one of six modes.

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Mode 0 (Set Output Bit when timer done)
• The output will start off “zero”.
• The count is loaded and the timer will start to count
down.
• When the count has reached zero the output will be
set high.
• The output remain high until the next count has been
reloaded.
• The Gate signal should remain active high for normal
counting.
• If Gate goes low counting get terminated and current
count is latched till Gate pulse goes high again.
• Counting rate is equal to the input clock frequency 17
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Figure 7: Illustration of Mode 0 operation.

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Mode 1 (Programmable One-Shot )
• The output will go low following the rising edge of the
gate input.
• The counter will count and the output will go high
once the counter has reached zero.

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Figure 8: Illustration of Mode 1 operation. 19
 Mode 2 (Rate Generator)
• In this mode, the device acts as a divide-by-n counter, which is
commonly used to generate a real-time clock interrupt.
• Like other modes, counting process will start the next clock
cycle after COUNT is sent.
• OUT will then remain high until the counter reaches 1, and will
go low for one clock pulse.
• OUT will then go high again, and the whole process repeats
itself.
• The time between the high pulses depends on the preset
count in the counter's register, and is calculated using the
following formula:
value to be loaded into counter = finput/foutput

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Figure 9: Illustration of Mode 2 operation.

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 Mode 3 (Square Wave Generator)
• This mode is similar to mode 2 except in the output
high and low intervals.
• Suppose n is the number loaded into the counter
(the COUNT message), the output will be
 high for n/2 counts, and low for n/2 counts, if n is
even.
 high for (n+1)/2 counts, and low for (n-1)/2
counts, if n is odd.

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 Mode 4 (Software Triggered Pulse)
• After Control Word and COUNT is loaded,
the output will remain high until the counter
reaches zero.
• The counter will then generate a low pulse
for 1 clock cycle (a strobe) – after that the
output will become high again.

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 Mode 5 (Hardware Triggered Strobe)
• This mode is similar to mode 4.
• The counting process is triggered by the GATE
input.
• After receiving the Control Word and COUNT, the
output will be set high.
• Once rising edge on the GATE input, counter will
start counting.
• When counter reaches 0, output will go low for one
clock cycle – after that it will become high again, to
repeat the cycle on the next rising edge of GATE.

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 Programming the 8253
• The format of the Control Word is shown in
Figure 5.
• SC1-SC0 (Select Counter): Select the desired
counter as shown in Table 3.
• RL1-RL0 (Read/Load): Set the reading/loading
format of the initial count value as shown in
Table 4.
• M2-M1-M0 (Modes): Specify the operation
mode of the 8253 as shown in Table 5.
• BCD (Count Mode): Specify the operation count
mode BCD/binary as shown in Table 6.
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Figure 5: Format of the Control Word of the 8253.

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 Table 3: Selection of set counter in the 8253.

Table 4: Count value reading/loading format setting in the 8253.

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Table 5: Operation waveform mode setting in the 8253.

Table 6: Operation count setting in the 8253.

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 Programming the 8253
Setting the Count Value
• Example 2: Program the 8253 shown in
the next figure according to the following
settings:
• Counter #0: Read/Load LSB only, Mode 3,
Binary count, count value 3H
• Counter #1: Read/Load MSB only, Mode 5,
Binary count, count value AA00H
• Counter #2: Read/Load LSB and MSB, Mode
0, BCD count, count value 1234

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Figure 6: Circuit interface of Example 2.

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MOV AL, 1EH
OUT 0EH, AL ; Counter #0 control word setting
MOV AL, 6AH
OUT 0EH, AL ; Counter #1 control word setting
MOV AL, 0B1H
OUT 0EH, AL ; Counter #2 control word setting
MOV AL, 03H
OUT 08H, AL ; Counter #0 control value setting
MOV AL, 0AAH
OUT 0AH, AL ; Counter #1 control value setting
MOV AL, 34H
OUT 0CH, AL ; Counter #2 count value setting (LSB)
MOV AL, 12H
OUT 0CH, AL ; Counter #2 count value setting (MSB)

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 System Interfacing of the 8253
• The 8253 is a component of the Intel
microcomputer systems and interfaces in the same
manner as all other peripherals of the family.
• It is treated by the systems software as an array of
peripheral I/O ports; three are counters and the
fourth is a control register for MODE programming.
• Basically, the select inputs A0, A1 connect to the
A0, A1 address bus signals of the CPU.
• The CS can be derived directly from the address bus
using a linear select method.
• Or it can be connected to the output of a decoder,
such as an Intel 8205 for larger systems.
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Figure 3: System Interfacing of the 8253.

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 System Interfacing of the 8253
Example 1: Show how to interface the 8253 to the
low byte of the 8086 (D0-D7). Assume the following
I/O port addresses are used.
Step (1): Design the address decoding
A15-A12 A11-A8 A7-A4 A3 A2 A1 A0
0000 0000 0000 1 0 0 0
0000 0000 0000 1 0 1 0
0000 0000 0000 1 1 0 0
0000 0000 0000 1 1 1 0
Chip Select (CS’) Port Enable
Select Even Byte
(A1 AliA0) (D0-D7)
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• Step(2): Design control logic (IOW & IOR)

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