Vous êtes sur la page 1sur 28

MachXO3L Starter Kit



User Guide

November 2014
EB95_1.0
MachXO3L Starter Kit User Guide

Introduction
Thank you for choosing the Lattice Semiconductor MachXO3L Starter Kit!

This user’s guide describes how to start using the MachXO3L Starter Kit, an easy-to-use platform for evaluating
and designing with the MachXO3L ultra-low density FPGA. Along with the board and accessories, this kit includes
a pre-loaded demonstration design. You may also reprogram the on-board MachXO3L device to review your own
custom designs.

The MachXO3L Starter Kit currently features the MachXO3L-6900C device in the 256-ball 0.8 mm pitch caBGA
package.

See the Ordering Information section for more information.

Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling
section of this document for handling and storage tips.

Features
The MachXO3L Starter Kit includes:

• MachXO3L Board – The board is a 3” x 3” form factor that features the following on-board components and cir-
cuits:
— MachXO3L FPGA – LCMXO3L-6900C-5BG256C
— USB mini-B connector for power and programming
— Eight LEDs
— 4-position DIP switch
— Momentary push button switch
— 40-hole prototype area
— Four 2 x 20 expansion header landings for general I/O, JTAG, and external power
— 1 x 8 expansion header landing for JTAG
— 1 x 6 expansion header landing for SPI/I2C
— 3.3 V and 1.2 V supply rails

• Pre-loaded Demo – The kit includes a pre-loaded counter design that highlights use of the embedded
MachXO3L oscillator and programmable I/Os configured for LED drive.
• USB Connector Cable – The board is powered from the USB mini-B socket when connected to a host PC. The
USB channel also provides a programming interface to the MachXO3L JTAG port.
• Lattice Development Kits and Boards Web Page – Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.

The content of this user’s guide includes demo operation, programming instructions, top-level functional descrip-
tions of the Starter Kit, descriptions of the on-board connectors, and a complete set of schematics.

2
MachXO3L Starter Kit User Guide

Figure 1. MachXO3L Board, Top Side


Two 2 x 20 Header
Landings (J3, J4)

JTAG Header
Landing (J1)
LED array
(D9-D2)

SPI/I2C Header
Landing (J7)

MachXO3L PLD 4 x 10 40-Hole


(U5) Prototype array

USB Mini-B
Socket (J2)

4-Position DIP
Switch (SW2)
Power LED,
Blue (D1)

Push Button
Switch (SW1)

FTDI USB to Two 2 x 20 Header


UART/FIFO IC (U1) Landings (J6, J8)

Storage and Handling


Static electricity can shorten the lifespan of electronic components. Please observe these tips to prevent damage
that could occur from electro-static discharge:

• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
• Store the evaluation board in the packaging provided.
• Touch a metal USB housing to equalize voltage potential between you and the board.

Software Requirements
You should install the following software before you begin developing new designs for the Starter Kit:

• Lattice Diamond® design software


• FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)

MachXO3L Device
This board currently features the MachXO3L-6900C FPGA which offers embedded Non-Volatile Configuration
Memory (NVCM) technology for instant-on operation in a single chip. Numerous system functions are included,
such as two PLLs and 256 kbits of embedded RAM plus hardened implementations of I2C and SPI. Flexible, high
performance I/Os support numerous single-ended and differential standards including LVDS. The 256-ball BGA
package provides up to 206 user I/Os in a 14 mm x 14 mm form factor. A complete description of this device can be
found in the MachXO3 Family Data Sheet.

3
MachXO3L Starter Kit User Guide

Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO3L device. The design
integrates an up-counter with the on-chip oscillator.

Note: To restore the factory default demo and program it with other Lattice-supplied examples see the Download
Demo Designs section of this document.

Run the Demonstration Design


Upon power-up, the preprogrammed demonstration design automatically loads and drives the LED array in a 1-hertz
pattern. The program shows a clock divider driven either by the MachXO3L internal oscillator or the external FTDI
clock chip. The divider modules (heartbeat.v and kitcar.v) are clocked at the default frequency of 12 MHz which
divides the clock to cycle the LED display approximately once per second. The resulting light pattern is determined by
the DIP Switch (SW2) setting as shown in Table 1.

Figure 2. Demonstration Design Block Diagram


MachXO3L

XO3L_SK_blink.v

OSCH
12.09 MHz Kitcar.v

1x8
LED
Heartbeat.v Array

X1
12.0 MHz

SW2
4-Position DIPSW

SW1
Async Reset
Momentary PB

Table 1. DIP Switch Setting and LED Behavior


Switch Setting LED Behavior
DIP_SW[1] 0 (Down) External 12.0 MHz (X1)
1 (Up) Internal 12.09 MHz (OSCH)
DIP_SW[2:4] 001 1 Hz Sweep
011 1 Hz Left-Right
111 1 Hz Blink
Others 1 Hz Alternating

WARNING: Do not connect the board to your PC before you follow the driver installation procedure of this section.

Communication between the board and a PC via the USB connection cable requires installation of the FTDI chip
USB hardware drivers. Loading these drivers enables the computer to recognize and program the board. Drivers
can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a
stand-alone package.

To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:

1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.

2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.

3. Click Finish to install the USB driver.

4
MachXO3L Starter Kit User Guide

4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a blue Power LED (D1) will light indicating the board is pow-
ered on.

5. The demonstration design will automatically load and drive the LED array in a repeating pattern.

To load the FTDI chip USB hardware drivers via the stand-alone package on a Windows system:

1. Browse to www.latticesemi.com/breakoutboards and download the FTDI Chip USB Hardware Drivers package.

2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.

3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J2). After the connec-
tion is made, a blue Power LED (D1) will light indicating the board is powered on.

4. If you are prompted, “Windows may connect to Windows Update” select No, not this time from available
options and click Next to proceed with the installation. Choose the Install from specific location (Advanced)
option and click Next.

5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder
created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified
folder and click OK.

6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.

7. Click Finish to install the USB driver.

8. The demonstration design will automatically load and drive the LED array in a repeating pattern.

See the Troubleshooting section of this guide if the board does not function as expected.

Download Demo Designs


The counter demo is preprogrammed into the board, however over time it is likely your board will be modified. Lat-
tice distributes source and programming files for demonstration designs compatible with the Starter Kit. The demo
design for the board is available on the web.

To download demo designs:

1. Browse to the Lattice Development Kits and Boards web page (www.latticesemi.com/breakoutboards) of the
Lattice web site. Select MachXO3L Starter Kit Demo Source and save the file.

2. Extract the contents of MachXO3L_Starter_Kit.zip to an accessible location on your hard drive.

3. Open the Blink.ldf project file in the Lattice Diamond design software.

4. Run the Process Flow and regenerate the Bitstream file.

Continue to Programming a Demo Design with Lattice Diamond Design Software.

5
MachXO3L Starter Kit User Guide

Programming a Demo Design with the Lattice Diamond Programmer


The demonstration design is pre-programmed into the MachXO3L board by Lattice. If you have changed the design
but now want to restore the board to factory settings, use the procedure described below.

To program the MachXO3L device:

1. Install, license and run Lattice Diamond software. See www.latticesemi.com/latticediamond for download and
licensing information.

2. Connect the USB cable to the host PC and the MachXO3L board.

3. From Diamond, open the Blink.ldf project file.

4. Click the Programmer icon.

5. Click Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0). If the cable is not
detected, see the Troubleshooting section.

6. Click Device Properties.

7. Change Access Mode to SPI Flash Programming.

8. Choose SPI Flash Background Erase, Program, Verify operation.

9. Select Blink_impl1.bit programming file.

10. Under SPI Flash Options, change Vendor to SPANSION and change Device to SPI-S25FL004D or SPI-
S25FL204K. Click OK.

11. Click the Program icon. When complete, PASS is displayed in the Status column.

12. Change Access mode to NVCM Programming Mode and NVCM Refresh, then click Program (or power-
cycle the Starter Kit board) to initiate a re-boot from the SPI flash.

6
MachXO3L Starter Kit User Guide

MachXO3L Starter Kit


This section describes the features of the MachXO3L Starter Kit in detail.

Overview
The Starter Kit is a complete development platform for the MachXO3L FPGA. The board includes a prototyping
area, a USB program/power port, an LED array, switches, and header landings with electrical connections to most
of the FPGA’s programmable I/O, power, and configuration pins. The board is powered by the PC’s USB port or
optionally with external power. You may create or modify the program files and reprogram the board using Lattice
Diamond software.

Figure 3. MachXO3L-6900C Block Diagram


Bank 0
2 x 20 Header USB USB Mini B
Landing (J3) Controller Socket
1 x 8 Header
JTAG Landing (J1,
GPIO Programming Optional JTAG
Interface)

Bank 1
GPIO
2 x 20 Header
Bank 3, 4 and 5 Landing (J4)
2 x 20 Header GPIO
MachXO3L-6900C device
Landing (J8)
8 LED
Array
4
DIP_SW

GPIO

2 x 20 Header 1 x 6 Header
Landing (J6) Landing (J7,
Bank 2 Optional SPI,
I2C Intrfaces)
Bank 0, 2

7
MachXO3L Starter Kit User Guide

Table 2 describes the components on the board and the interfaces it supports.

Table 2. Starter Kit Components and Interfaces


Schematic
Component/Interface Type Reference Description
Circuits
USB Controller Circuit U1: FT2232H USB-to-JTAG interface and dual USB UART/FIFO IC
USB Mini-B Socket I/O J2:USB_MINI_B Programming and debug interface
Components
U5: LCMXO3L- 6900-LUT device packaged in a 14 mm x14 mm, 
LCMXO3L FPGA
6900C-5BG256C 256-ball caBGA
Interfaces
LED Array Output D9-D2 Red LEDs
Push Button Switch Input SW1 Momentary User Input
4-position DIP Switch Input SW2 User inputs
J3: header_2x20
Four 2 x 20 Header J4: header_2x20
I/O User-definable I/O
Landings J6: header_2x20
J8: header_2x20
1 x 8 Header Landing I/O J1: header_1x8 Optional JTAG interface
1 x 6 Header Landing I/O J7: header_1x6 Optional SPI/I2C interfaces
4 x 10 40-Hole 
Prototype area 100 mil centered holes.
Prototype Area
TP1: +3.3 V
Test Points Power TP2: +1.2 V Power and ground reference points
TP3: GND

Subsystems
This section describes the principle sub systems for the Starter Kit in alphabetical order.

Clock Sources
Clock sources for the LED demonstration designs originate from the MachXO3L on-chip oscillator or the 12 MHz
crystal X1. You may use an expansion header landing to drive a FPGA input with an external clock source.

Expansion Header Landings


The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the
MachXO3L. The remaining pins serve as power supplies for external connections. Each landing is configured as
one 2 x 20 100 mil.

Table 3. Expansion Connector Reference


Item Description
Reference Designators J3, J4, J6, J8
Part Number header_2x20

8
MachXO3L Starter Kit User Guide

Table 4. Expansion Header Pin Information (J3)


Header Pin Number –6900C Function MachXO3L Ball
1 VCCIO0 D5,D12,G8,G9
2 VCCIO0 D5,D12,G8,G9
3 PT36C/INITn A13
4 PT36D/DONE C13
5 PT22A F8
6 PT35B B12
7 PT35A C12
8 PT26B E11
9 PT27B E10
10 PT27A D10
11 GND —
12 GND —
13 PT26A F9
14 PT27C/JTAGENB C10
15 PT17B E8
16 PT21B E9
17 PT14B E7
18 PT21A D8
19 PT16B D7
20 PT15B C7
21 GND —
22 GND —
23 PT10B C5
24 PT14A D6
25 PT16A E6
26 PT9A C4
27 PT25B A10
28 PT17A F7
29 PT22B D9
30 PT25A B9
31 GND —
32 GND —
33 PT11B B6
34 PT15A B7
35 PT9B B5
36 PT11A A5
37 PT12B B4
38 PT10A A4
39 GND —
40 PT12A A3

9
MachXO3L Starter Kit User Guide

Table 5. Expansion Header Pin Information (J4)


Header Pin Number –6900C Function MachXO3L Ball
1 VCCIO1 E13,H10,J10,M13
2 VCCIO1 E13,H10,J10,M13
3 PR19D K12
4 PR19C K13
5 PR23A M14
6 PR24B N14
7 PR18B L14
8 PR24A N16
9 PR23B M15
10 PR21B M16
11 GND —
12 GND —
13 PR21A L15
14 PR18A L16
15 PR17A K14
16 PR16B K16
17 PR17B K15
18 PR15B J14
19 PR12A/PCLKT1_0 H14
20 PR16A J15
21 GND —
22 GND —
23 PR15A J16
24 PR11B H15
25 PR12B/PCLKC1_0 H16
26 PR9A G15
27 PR11A G16
28 PR5B F15
29 PR7B F16
30 PR2B/R_GPLLC_FB E15
31 GND —
32 GND —
33 PR5A E16
34 PR3B/R_GPLLC_IN E14
35 PR3A/R_GPLLT_IN D16
36 PR2C C15
37 PR2A/R_GPLLT_FB D14
38 PR7A F14
39 PR9B G14
40 PR2D B16

10
MachXO3L Starter Kit User Guide

Table 6. Expansion Header Pin Information (J6)


Header Pin Number –6900C Function MachXO3L Ball
1 VCCIO2 K8,K9,N5,N12
2 VCCIO2 K8,K9,N5,N12
3 PB35B T12
4 PB34B T14
5 PB35A R11
6 PB34A R13
7 PB31A T11
8 PB28B M11
9 PB31B P11
10 PB28A N10
11 GND —
12 GND —
13 PB26B T10
14 PB29A P10
15 PB26A R9
16 PB29B R10
17 PB23A/PCLKT2_1 T9
18 PB21B N9
19 PB23B/PCLKC2_1 P9
20 PB21A M8
21 GND —
22 GND —
23 PB18B T8
24 PB15B L8
25 PB18A P8
26 PB15A M6
27 PB13A R7
28 PB16B/PCLKC2_0 R8
29 PB13B P7
30 PB16A/PCLKT2_0 T7
31 GND —
32 GND —
33 PB10B L7
34 PB9B R6
35 PB10A N6
36 PB9A T5
37 PB7B R4
38 PB4A P4
39 PB7A T3
40 PB4B T4

11
MachXO3L Starter Kit User Guide

Table 7. Expansion Header Pin Information (J8)


Header Pin Number –6900C Function MachXO3L Ball
1 VCCIO5 E4
2 VCCIO3 M4
3 PL9D H6
4 PL25B N3
5 PL25A M2
6 PL22B/PCLKC3_0 M1
7 PL22A/PCLKT3_0 L2
8 PL19A L1
9 PL19B L3
10 PL19D L5
11 GND —
12 GND —
13 PL19C K4
14 PL12A/PCLKT4_0 J1
15 PL15B K1
16 PL15A J2
17 PL12B/PCLKC4_0 J3
18 PL11A H3
19 PL10B H2
20 PL11B H1
21 GND —
22 GND —
23 PL9A G2
24 PL10A G1
25 PL6B/PCLKC5_0 F2
26 PL8B F1
27 PL4A/L_GPLLT_IN E2
28 PL6A/PCLKT5_0 E1
29 PL4D D2
30 PL3B/L_GPLLC_FB D1
31 GND —
32 PL2D C2
33 PL4C C1
34 PL9B G3
35 PL2C B1
36 PL3A/L_GPLLT_FB D3
37 PL4B/L_GPLLC_IN E3
38 PL8A F3
39 PL9C F5
40 VCCIO4 H7,J7

12
MachXO3L Starter Kit User Guide

Figure 4. J3/J4 Header Landing Callout


J3 J4
Top Side
1 2 1 2
VCCIO0 VCCIO0 VCCIO1 VCCIO1
A13 C13 K12 K13
F8 B12 M14 N14
C12 E11 L14 N16
E10 D10 M15 M16
GND GND GND GND
F9 C10 L15 L16
E8 E9 K14 K16
E7 D8 K15 J14
D7 C7 H14 J15
GND GND GND GND
C5 D6 J16 H15
E6 C4 H16 G15
A10 F7 G16 F15
D9 B9 F16 E15
GND GND GND GND
B6 B7 E16 E14
B5 A5 D16 C15
B4 A4 D14 F14
GND A3 G14 B16
39 40 39 40
J3 J4

Figure 5. J6/J8 Header Landing Callout


J6 J8

Top Side J6 J8 1 2 1 2
VCCIO2 VCCIO2 VCCIO5 VCCIO3
T12 T14 H6 N3
R11 R13 M2 M1
T11 M11 L2 L1
P11 N10 L3 L5
GND GND GND GND
T10 P10 K4 J1
R9 R10 K1 J2
T9 N9 J3 H3
P9 M8 H2 H1
GND GND GND GND
T8 L8 G2 G1
P8 M6 F2 F1
R7 R8 E2 E1
P7 T7 D2 D1
GND GND GND C2
L7 R6 C1 G3
N6 T5 B1 D3
R4 P4 E3 F3
T3 T4 F5 VCCIO4
39 40 39 40

13
MachXO3L Starter Kit User Guide

Figure 6. J1 Header Landing and LED Array Callout


LED Array
MachXO3L
J1 J1 LED Net Ball
8 D9 LED0 H11
D8 LED1 J13
TCK D9 D7 LED2 J11
GND
D6 LED3 L12
TMS
D5 LED4 K11
nc
D2 D4 LED5 L13
nc
J7 D3 LED6 N15
TDI
D2 LED7 P16
TDO
VCCIO0

Top Side
LCMXO2-7000HE
1 4TG144C

MachXO3L
J7
Net Ball
6
DIP_SW1 DIP_SW1 H11
MCLK DIP_SW2 J13
SISPI DIP_SW3 J11
SPISO DIP_SW4 DIP_SW4 L12
SN
SCL
SDA
1

MachXO3L FPGA
The LCMXO3L-6900C-5BG256C is a 256-ball caBGA package FPGA device which provides up to 206 usable I/Os
in a 14 mm x 14 mm package. 150 I/Os are accessible from the board headers, switches and LEDs.

Table 8. MachXO3L FPGA Interface Reference


Item Description
Reference Designators U5
Part Number LCMXO3L-6900C-5BG256C
Manufacturer Lattice Semiconductor
Web Site www.latticesemi.com

Programming Interface Circuits


For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a
PC host and the JTAG programming chain of the Starter Kit. The USB 5 V supply is also used as a source for the
3.3 V supply rail. A USB mini-B socket is provided for the USB connector cable.

Table 9. USB/JTAG Interface Reference


Item Description
Reference Designators U1
Part Number FT2232HL
Manufacturer Future Technology Devices International (FTDI)
Web Site www.ftdichip.com

14
MachXO3L Starter Kit User Guide

Table 10. JTAG Programming Pin Information


Description MachXO3L Pin
Test Data Output C6:TDO
Test Data Input A6:TDI
Test Mode Select B8:TMS
Test Clock A7:TCK

Table 11. SPI Programming Pin Information


Description MachXO3L Pin
Master Clock/Config Clock P6:MCLK/CCLK
Serial Data Input P13: SI/SISPI
Serial Data Output T6: SO/SPISO
SPI Slave Select R12: SN

Table 12. I2C Programming Pin Information


Description MachXO3L Pin
Serial Data C9:SDA
Serial Clock A9:SCL

LEDs
A blue LED (D1) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO3L device.

Table 13. Power and User LEDs Reference


Item Description
Red LEDs (D2, D3, D4, D5, D6, D7, D8, D9)
Reference Designators
Blue LEDs (D1)
LTST-C190KRKT (D2-D9)
Part Number
LTST-C190TBKT (D1)
Manufacturer Lite-On It Corporation
Web Site www.liteonit.com

Power Supply
3.3 V and 1.2 V power supply rails are converted from the USB 5 V interface when the board is connected to a host
PC.

Test Points
In order to check the various voltage levels used, test points are provided:

• TP1: +3.3 V
• TP2: +1.2 V
• TP3: GND

USB Programming and Debug Interface


The USB mini-B socket of the Starter Kit serves as the programming and debug interface.

JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the
Starter Kit to serve as the programming interface to the MachXO3L FPGA.

Programming requires the Lattice Diamond or ispVM System software.

15
MachXO3L Starter Kit User Guide

Table 14. USB Interface Reference


Item Description
Reference Designators U1
Part Number FT2232HL
Manufacturer Future Technology Devices International (FTDI)
Web Site www.ftdichip.com

Board Modifications
This section describes modifications to the board to change or add functionality.

Bypassing the USB Programming Interface


The USB programming interface circuit (USB Programming and Debug Interface section) may be optionally
bypassed by removing the 0 Ohm resistors: R4, R5, R6, R7 (See Appendix A. Schematics, Sheet 2 of 8). Header
landing J1 provides JTAG signal access for jumper wires or a 1 x 8 pin header.

Applying External Power


The Starter Kit is powered by the circuit of Schematic Sheet 3 of 8 based on the 5 V USB power source. You may
disconnect this power source by removing the 0 Ohm resistors: R35 (VCC_1.2 V) and R42 (VCC_3.3 V). Power
connections are available from the test points, TP1 (+3.3 V) and TP2 (+1.2 V).

Measuring Bank and Core Power


Test points (TP1, TP2) provide access to power supplies of the MachXO3L FPGA. Inline 1 Ohm resistors: R31
(VCCIO0, +3.3 V, Bank 0), R25 (VCCIO1, +3.3 V, Bank 1), R37 (VCCIO2, +3.3 V, Bank 2), R32 (VCCIO3, +3.3 V,
Bank 3), R26 (VCCIO4, +3.3 V, Bank 4), R38 (VCCIO5, +3.3 V, Bank 5), R24 (VCC core, +1.2 V) can be used to mea-
sure current for the power supplies.

Mechanical Specifications
Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]

Environmental Requirements
The evaluation board must be stored between –40° C and 100° C. The recommended operating temperature is
between 0° C and 90° C.

The board can be damaged without proper anti-static handling.

Glossary
FPGA: Field Programmable Gate Array

DIP: Dual in-line package

LED: Light Emitting Diode.

LUT: Look Up Table

PCB: Printed Circuit Board

RoHS: Restriction of Hazardous Substances Directive

USB: Universal Serial Bus

WDT: Watchdog Timer

16
MachXO3L Starter Kit User Guide

Troubleshooting
Use the tips in this section to diagnose problems with the Starter Kit.

LEDs Do Not Flash

If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is
likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design sec-
tion to restore the factory default.

USB Cable Not Detected

If Lattice Diamond Programmer or ispVM System does not recognize the USB cable after installing the Lattice USB
port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the
board to your PC prior to installing the Lattice-supplied USB driver.

To access the Troubleshooting the USB Driver Installation Guide:

For Diamond software and standalone Diamond Programmer:

1. Start Diamond or Diamond Programmer and choose Help.

2. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic.

3. Follow the directions to install the Lattice USB driver.

For ispVM:

1. Start ispVM System and choose Options > Cable and I/O Port Setup.
The Cable and I/O Port Setup Dialog appears.

2. Click the Troubleshooting the USB Driver Installation Guide link.


The Troubleshooting the USB Driver Installation Guide document appears in your system’s PDF file reader.

3. Follow the directions to install the Lattice USB driver.

Determine the Source of a Pre-Programmed Device

If the Starter Kit has been reprogrammed, the original demo design can be restored. To restore the board to the
factory default, see the Download Demo Designs section for details on downloading and reprogramming the
device.

Ordering Information
China RoHS Environment-Friendly
Description Ordering Part Number Use Period (EFUP)

MachXO3L Starter Kit LCMXO3L-6900C-S-EVN

Technical Support Assistance


e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com

17
MachXO3L Starter Kit User Guide

Revision History
Date Version Change Summary
November 2014 1.0 Initial release.

© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

18
5 4 3 2 1

SPI FLASH HEADER


Figure 7. Block Diagram

D D

SPI

I/O'S
I/O'S
BANK-2 BANK-4

HEADER
Appendix A. Schematics

I2C

I/O'S
C C

HEADER
I/O'S
LCMXO3L-6900C-5BG256C
HEADER

BANK-0
BANK-3
JTAG_I/F
USB USB to
CONNECTOR JTAG / RS232 RS232_I/F

19
BANK-1 BANK-5
Power from USB 5V

B B

I/O'S
I/O'S

LEDS (1-8)
HEADER

A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
MACHXO3 Starter Kit - BLOCK DIAGRAM

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 1 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1

+3.3V

L1 VCCIO0
2 1
600ohm 500mA

1
C1 C2
4.7uF
+3.3V 0.1uF

2
D R3 R1 R2 D

L2
2 1
600ohm 500mA 4.7K 4.7K 4.7K

1
C3 C4 VCC1_8FT +3.3V J1
4.7uF 1
0.1uF 1 2 TDO

2
2 3 TDI
3 4
Figure 8. USB Interface to JTAG

4 5
5 6 TMS
6 7
VCC1_8FT +3.3V U1 7 8 TCK
FT2232HL 8

4
9
12
37
64
20
31
42
56
Header 1x8
DNI

VPLL
VPHY
VCCIO
VCCIO
VCCIO
VCCIO

VCORE
VCORE
VCORE
16 0 R4
ADBUS0 TCK Sheet[4]
50 17 0 R5
VREGIN ADBUS1 TDI Sheet[4]
18 0 R6
ADBUS2 TDO Sheet[4]
49 19 0 R7
VREGOUT ADBUS3 TMS Sheet[4]
21
C ADBUS4 C
22
7 ADBUS5 23
Sheet[3] DM DM ADBUS6
Sheet[3] DP 8 24
DP ADBUS7 R8
C5 C6 26 2.2K
R9 2.2K 14 ACBUS0 27
10uF 0.1uF RESET# ACBUS1 28
+3.3V R10 12K ACBUS2 29
6 ACBUS3 30
+3.3V REF ACBUS4 32
R11 R12 R13 ACBUS5 33
ACBUS6 34 FOR FUTURE RS232 FUNCTION
ACBUS7

20
FT_EECS 63
FT_EECLK 62 EECS 38 0 DNI R14
EECLK BDBUS0 RS232_Rx_TTL Sheet[4]
U2 10K 10K 10K FT_EEDATA 61 39 0 DNI R15
EEDATA BDBUS1 RS232_Tx_TTL Sheet[4]
8 1 40 0 DNI R16 RTSn Sheet[4]
7 VCC CS 2 BDBUS2 41 0 DNI R17
NU CLK BDBUS3 CTSn Sheet[4]
6 3 2 43 0 DNI R18 DTRn Sheet[4]
C7 5 ORG DI 4 OSCI BDBUS4 44 0 DNI R20
VSS DO BDBUS5 DSRn Sheet[4]
12K R19 45 0 DNI R21
X1 BDBUS6 DCDn Sheet[4]
0.1uF 93LC56C-I/SN 46 0 DNI R22
BDBUS7 RI Sheet[4]
1 3 3
1 3 OSCO 48
2 4 BCBUS0 52
B B
C8 G1 G2 C9 BCBUS1 53 FOR FUTURE I2C FUNCTION
13 BCBUS2 54
18pF 12MHZ 18pF TEST BCBUS3 55 0 DNI R27 FTDI_SCL Sheet[6]
BCBUS4 57 0 DNI R62
BCBUS5 58 0 DNI R82
FTDI High-Speed USB BCBUS6 FTDI_SDA Sheet[6]
59
BCBUS7
USB_I2C_EN Sheet[6]
FT2232H 60
PWREN#
+3.3V 36
0 R23 SUSPEND#
Sheet[4] 12MHZ
AGND
GND
GND
GND
GND
GND
GND
GND
GND

C10 C11 C12 C13 C14


1
5

10
11
15
25
35
47
51

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
USB to JTAG I/F

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 2 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1
Figure 9. FPGA

VBUS_5V

+3.3V VCC_CORE +3.3V VCCIO0 +3.3V VCCIO1 +3.3V VCCIO2

C15

1
R24 1 R31 1 R25 1 R37 1
L3 0.1uF NOTE : Boot from external SPI Flash (U6)
D D
600ohm 500mA
requires VCCIO2 set to 3.3V. Use caution
+1.2V +1.2V +1.2V +1.2V when setting VCCIO2 to any other voltage.

2
R86 1 R33 1 R28 1 R39 1

DNI DNI DNI DNI


J2
1
VCC 2
D- DM Sheet[2] TP5 TP6 TP7 TP8
3 DP Sheet[2]
D+ 4 R30 0
ID 5 VCC_CORE VCCIO0 VCCIO1 VCCIO2

1
1
1
1
GND C16 0.1uF
SKT_MINIUSB_B_RA

+3.3V VCCIO3 +3.3V VCCIO4 +3.3V VCCIO5


C C

R32 1 R26 1 R38 1


+3.3V
VBUS_5V
+1.2V +1.2V +1.2V
U4 R42 0 L5
R41 3 2 2 1
IN OUT 4 600ohm 500mA R34 1 R29 1 R40 1

1
1K TAB

21
D1 C19 C20 C21
GND DNI DNI DNI
Blue
10uF 22uF 0.1uF
1 NCP1117

2
TP9 TP10 TP11

VCCIO3 VCCIO4 VCCIO5

1
1
1

B B
TP3
TP1 TP2
1

+3.3V +1.2V
1
1

+3.3V

+1.2V C61 C62 C63 C64

10uF 1uF 0.1uF 0.01uF


U3 FAN1112 R35 0 L4
3 2 2 1
Input Output 600ohm 500mA
C17
A 4 C18 A
10uF Tab R36 Lattice Semiconductor Applications

GND
22uF
Email: techsupport@Latticesemi.com
100

1
Phone (503) 268-8001 -or- (800) LATTICE
Title
POWER REGULATORS

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 3 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1
Figure 10. FPGA

VCCIO0
NOTE : MAKE PWR TRACES
CAPABLE OF 1A

U5A VCCIO0 J3 VCCIO0


D D
BANK0 R43 R44
IO_C4 C4 F8 IO_F8 2K 2K 2 1
IO_B5 B5 PT9A*/PT9A*/PT9A* PT18A*/PT20A*/PT22A* D9 IO_D9 DONE 4 3 INITN
PT9B*/PT9B*/PT9B* PT18B*/PT20B*/PT22B* IO_B12 6 5 IO_F8
CREST B3 A9 SCL_1 49.9 R87 150 R90 IO_E11 8 7 IO_C12
PT9C/PT9C/PT9C PT18C/PT20C/PT22C || SCL/PCLKT0_0 SCL Sheet[6]
C9 SDA_1 49.9 R88 150 R89 SDA Sheet[6] IO_D10 10 9 IO_E10
IO_A4 A4 PT18D/PT20D/PT22D || SDA/PCLKC0_0 12 11
IO_C5 C5 PT10A*/PT10A*/PT10A* B9 IO_B9 C65 C66 JTAGENB 14 13 IO_F9
PT10B*/PT10B*/PT10B* PT19A*/PT21A*/PT25A* A10 IO_A10 IO_E9 16 15 IO_E8
IO_A5 A5 PT19B*/PT21B*/PT25B* 150pF 150pF IO_D8 18 17 IO_E7
IO_B6 B6 PT11A*/PT11A*/PT11A* F9 IO_F9 DNI DNI IO_C7 20 19 IO_D7
PT11B*/PT11B*/PT11B* PT19C/PT22A*/PT26A* E11 IO_E11 22 21
IO_A3 A3 PT19D/PT22B*/PT26B* IO_D6 24 23 IO_C5
IO_B4 B4 PT11C/PT12A*/PT12A* D10 IO_D10 IO_C4 26 25 IO_E6
PT11D/PT12B*/PT12B* PT20A*/PT23A*/PT27A* E10 IO_E10 IO_F7 28 27 IO_A10
IO_D6 D6 PT20B*/PT23B*/PT27B* TP4 IO_B9 30 29 IO_D9
IO_E7 E7 PT12A*/PT13A*/PT14A* C10 JTAGENB 32 31
PT12B*/PT13B*/PT14B* PT20C/PT23C/PT27C || JTAGENB B10 PROGRAMN IO_B7 34 33 IO_B6

1
PT20D/PT23D/PT27D || PROGRAMN IO_A5 36 35 IO_B5
TDO C6 A11 RS232_Rx_TTL IO_A4 38 37 IO_B4
Sheet[2] TDO PT12C/PT13C/PT14C || TDO PT21A*/PT24A*/PT28A* RS232_Rx_TTL Sheet[2]
TDI A6 C11 RS232_Tx_TTL IO_A3 40 39
Sheet[2] TDI PT12D/PT13D/PT14D || TDI PT21B*/PT24B*/PT28B* RS232_Tx_TTL Sheet[2]
IO_B7 B7 F10 RTSn
C PT13A*/PT14A*/PT15A* PT21C/PT24C/PT32A* RTSn Sheet[2] C
IO_C7 C7 D11 DTRn
PT13B*/PT14B*/PT15B* PT21D/PT24D/PT32B* DTRn Sheet[2]
Header 2x20
IO_E6 E6 B11 CTSn
PT13C/PT14C/PT16A* PT22A*/PT25A*/PT33A* CTSn Sheet[2]
IO_D7 D7 A12 DSRn
PT13D/PT14D/PT16B* PT22B*/PT25B*/PT33B* DSRn Sheet[2]
IO_F7 F7 B13 DCDn
PT16A*/PT15A*/PT17A* PT22C/PT26A*/PT34A* DCDn Sheet[2]
IO_E8 E8 A14 RI
PT16B*/PT15B*/PT17B* PT22D/PT26B*/PT34B* RI Sheet[2]
TCK A7 C12 IO_C12
Sheet[2] TCK PT16C/PT15C/PT17C || TCK PT23A*/PT27A*/PT35A*
TMS B8 B12 IO_B12
Sheet[2] TMS PT16D/PT15D/PT17D || TMS PT23B*/PT27B*/PT35B*
12MHZ C8 B14 VCCIO0
Sheet[2] 12MHZ PT17A*/PT18A*/PT18A* || PCLKT0_1 PT24A*/PT28A*/PT36A*
A8 A15

22
PT17B*/PT18B*/PT18B* || PCLKC0_1 PT24B*/PT28B*/PT36B*
IO_D8 D8 A13 INITN
IO_E9 E9 PT17C/PT19A*/PT21A* PT24C/PT28C/PT36C || INITN C13 DONE R45
PT17D/PT19B*/PT21B* PT24D/PT28D/PT36D || DONE

VCCIO0 * = TRUE LVDS Output VCCIO0


4.7K
SW1
D5 G8
C22 D12 VCCIO0/VCCIO0/VCCIO0 VCCIO0/VCCIO0/VCCIO0 G9 CREST
C23 C24 VCCIO0/VCCIO0/VCCIO0 VCCIO0/VCCIO0/VCCIO0 C25 C26 C27
B SYS_RST B
C28
0.01uF 0.1uF 0.1uF 1K-2K/4K/7K || 2nd_Fn. 0.1uF 0.1uF 0.1uF
0.1uF

LCMXO3L-6900C-5BG256C

A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK0 I/0

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 4 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1

U5B
NOTE : MAKE PWR TRACES
BANK1 CAPABLE OF 1A
Figure 11. Power LEDs

IO_C15 C15 D14 IO_D14 VCCIO1 J4 VCCIO1


D IO_B16 B16 PR1C/PR2C/PR2C PR1A/PR2A/PR2A || R_GPLLT_FB** E15 IO_E15 D
PR1D/PR2D/PR2D PR1B/PR2B/PR2B || R_GPLLC_FB**
C16 D16 IO_D16 2 1
D15 PR2C/PR4C/PR4C PR2A/PR3A/PR3A || R_GPLLT_IN** E14 IO_E14 IO_K13 4 3 IO_K12
PR2D/PR4D/PR4D PR2B/PR3B/PR3B || R_GPLLC_IN** IO_N14 6 5 IO_M14
F13 E16 IO_E16 IO_N16 8 7 IO_L14
G12 PR3C/PR5C/PR6C PR3A/PR5A/PR5A F15 IO_F15 IO_M16 10 9 IO_M15
PR3D/PR5D/PR6D PR3B/PR5B/PR5B 12 11
F12 F14 IO_F14 IO_L16 14 13 IO_L15
G13 PR4C/PR6C/PR7C PR4A/PR6A/PR7A F16 IO_F16 IO_K16 16 15 IO_K14
PR4D/PR6D/PR7D PR4B/PR6B/PR7B IO_J14 18 17 IO_K15
DQ0
G11 G15 IO_G15 IO_J15 20 19 IO_H14
H12 PR5C/PR8C/PR10C PR5A/PR8A/PR9A G14 IO_G14 22 21
PR5D/PR8D/PR10D PR5B/PR8B/PR9B IO_H15 24 23 IO_J16
H13 G16 IO_G16 IO_G15 26 25 IO_H16
J12 PR6C/PR9C/PR11C PR6A/PR9A/PR11A DQS0 H15 IO_H15 IO_F15 28 27 IO_G16
PR6D/PR9D/PR11D PR6B/PR9B/PR11B DQS0N IO_E15 30 29 IO_F16
IO_J16 J16 H14 IO_H14 32 31
IO_J14 J14 PR7C/PR10C/PR15A PR7A/PR10A/PR12A || PCLKT1_0 H16 IO_H16 IO_E14 34 33 IO_E16
PR7D/PR10D/PR15B PR7B/PR10B/PR12B || PCLKC1_0 IO_C15 36 35 IO_D16
LED0 H11 IO_F14 38 37 IO_D14
Sheet[8] LED0 LED1 J13 PR9C/PR13C/PR16C J15 IO_J15 IO_B16 40 39 IO_G14
Sheet[8] LED1 PR9D/PR13D/PR16D PR9A/PR13A/PR16A DQS1 K16 IO_K16
LED2 J11 PR9B/PR13B/PR16B DQS1N
C Sheet[8] LED2 PR10C/PR14C/PR17C C
LED3 L12 K14 IO_K14
Sheet[8] LED3 PR10D/PR14D/PR17D PR10A/PR14A/PR17A K15 IO_K15 Header 2x20
LED4 K11 PR10B/PR14B/PR17B
Sheet[8] LED4 LED5 L13 PR12C/PR16C/PR21C L16 IO_L16
Sheet[8] LED5 PR12D/PR16D/PR21D PR11A/PR15A/PR18A L14 IO_L14
LED6 N15 PR11B/PR15B/PR18B
Sheet[8] LED6 LED7 P16 PR13C/PR18C/PR23C K13 IO_K13
Sheet[8] LED7 PR13D/PR18D/PR23D PR11C/PR15C/PR19C K12 IO_K12
P15 PR11D/PR15D/PR19D
PR14C/PR20C/PR25C
DQ1 J5
R16 L15 IO_L15
PR14D/PR20D/PR25D PR12A/PR16A/PR21A M16 IO_M16 1
PR12B/PR16B/PR21B Proto Type Area

23
M14 IO_M14
PR13A/PR18A/PR23A M15 IO_M15
PR13B/PR18B/PR23B
N16 IO_N16
PR14A/PR19A/PR24A N14 IO_N14
PR14B/PR19B/PR24B

VCCIO1 ** = 2nd_Fn. applicable for 4K and 7K devices only. VCCIO1


Proto Type Area, Holes on 0.1 inch Centers
B DNI B
E13 J10
C29 H10 VCCIO1/VCCIO1/VCCIO1 VCCIO1/VCCIO1/VCCIO1 M13
C30 C31 VCCIO1/VCCIO1/VCCIO1 VCCIO1/VCCIO1/VCCIO1 C32 C33 C34

0.01uF 0.1uF 0.1uF 1K-2K/4K/7K || 2nd_Fn. 0.1uF 0.1uF 0.1uF


PROTOTYPE AREA
FILL AVAILABLE AREA
LCMXO3L-6900C-5BG256C

A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK1 I/O

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 5 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1

U5C
NOTE : MAKE PWR TRACES
BANK2 CAPABLE OF 1A
VCCIO2 J6 VCCIO2 IO_P4 R46 DNI 100
Figure 12. Bank 2 I/O

IO_P4 P4 M8 IO_M8 IO_T4


IO_T4 T4 PB3A/PB3A/PB4A PB16C/PB18A/PB21A N9 IO_N9
PB3B/PB3B/PB4B PB16D/PB18B/PB21B 2 1 IO_T3 R47 DNI 100
D T2 T9 IO_T9 IO_T14 4 3 IO_T12 IO_R4 D
NOTE : PLACE R84,R81,R83,R85 CLOSE TO U5 R3 PB3C/PB3C/PB4C PB16A/PB20A/PB23A || PCLKT2_1 P9 IO_P9 IO_R13 6 5 IO_R11
PB3D/PB3D/PB4D PB16B/PB20B/PB23B || PCLKC2_1 IO_M11 8 7 IO_T11 IO_T5 R48 DNI 100
CSSPIN 0 R84 R5 R9 IO_R9 IO_N10 10 9 IO_P11 IO_R6
P5 PB5A/PB4A/PB6A || CSSPIN PB18A/PB21A/PB26A T10 IO_T10 12 11
PB5B/PB4B/PB6B PB18B/PB21B/PB26B IO_P10 14 13 IO_T10 IO_N6 R49 DNI 100
IO_T3 T3 M9 IO_R10 16 15 IO_R9 IO_L7
IO_R4 R4 PB6C/PB6A/PB7A PB18C/PB21C/PB26C L10 IO_N9 18 17 IO_T9
PB6D/PB6B/PB7B PB18D/PB21D/PB26D IO_M8 20 19 IO_P9
IO_T5 T5 N10 IO_N10 22 21 IO_R7 R50 DNI 100
IO_R6 R6 PB6A/PB7A/PB9A PB19C/PB23C/PB28A M11 IO_M11 IO_L8 24 23 IO_T8 IO_P7
PB6B/PB7B/PB9B PB19D/PB23D/PB28B IO_M6 26 25 IO_P8
IO_N6 N6 P10 IO_P10 IO_R8 28 27 IO_R7 IO_M6 R51 DNI 100
IO_L7 L7 PB8C/PB9C/PB10A PB19A/PB23A/PB29A R10 IO_R10 IO_T7 30 29 IO_P7 IO_L8
PB8D/PB9D/PB10B PB19B/PB23B/PB29B 32 31
MCLK 0 R81 P6 T11 IO_T11 IO_R6 34 33 IO_L7 IO_T7 R52 DNI 100
SPISO 0 R83 T6 PB8A/PB9A/PB12A || MCLK/CCLK PB21A/PB24A/PB31A P11 IO_P11 IO_T5 36 35 IO_N6 IO_R8
PB8B/PB9B/PB12B || SO/SPISO PB21B/PB24B/PB31B IO_P4 38 37 IO_R4
IO_R7 R7 M10 IO_T4 40 39 IO_T3 IO_P8 R53 DNI 100
IO_P7 P7 PB9A/PB10A/PB13A PB21C/PB24C/PB31C N11 IO_T8
PB9B/PB10B/PB13B PB21D/PB24D/PB31D
M7
N7 PB9C/PB10C/PB13C R13 IO_R13 VCCIO2 Header 2x20 IO_M8 R54 DNI 100
PB9D/PB10D/PB13D PB22C/PB26A/PB34A T14 IO_T14 IO_N9
C PB22D/PB26B/PB34B C
IO_M6 M6
IO_L8 L8 PB11C/PB12A/PB15A R11 IO_R11 NOTE : ROUTE J6 TRACES AS 100OHMS, LENGTH MATCHED IO_T9 R55 DNI 100
PB11D/PB12B/PB15B PB22A/PB27A/PB35A T12 IO_T12 R80 DIFFERENTIAL PAIRS IO_P9
PB22B/PB27B/PB35B
IO_T7 T7 P12 IO_R9 R56 DNI 100
IO_R8 R8 PB11A/PB13A/PB16A || PCLKT2_0 PB24A/PB29A/PB37A T13 IO_T10
PB11B/PB13B/PB16B || PCLKC2_0 PB24B/PB29B/PB37B 10K
IO_P8 P8 R12 SN IO_N10 R57 DNI 100
IO_T8 T8 PB12A/PB15A/PB18A PB25A/PB30A/PB38A || SN P13 IO_M11
PB12B/PB15B/PB18B PB25B/PB30B/PB38B || SI/SISPI 0 R85 SISPI
N8 T15 IO_P10 R58 DNI 100
L9 PB12C/PB15C/PB18C PB25C/PB30C/PB38C R14 IO_R10
PB12D/PB15D/PB18D PB25D/PB30D/PB38D

24
IO_T11 R59 DNI 100
VCCIO2 VCCIO2 IO_P11

IO_R13 R60 DNI 100


K8 N5 IO_T14
C35 K9 VCCIO2/VCCIO2/VCCIO2 VCCIO2/VCCIO2/VCCIO2 N12
C36 C37 VCCIO2/VCCIO2/VCCIO2 VCCIO2/VCCIO2/VCCIO2 C38 C39 C40 IO_R11 R61 DNI 100
IO_T12
0.01uF 0.1uF 0.1uF 1K-2K/4K/7K || 2nd_Fn. 0.1uF 0.1uF 0.1uF

B NOTE : PLACE ALL THE LVDS DIFF TERMINATION B


LCMXO3L-6900C-5BG256C RESISTORS IN TOP AND CLOSE TO U5

+3.3V
NOTE : PLACE SPI FLASH IN THE BOTTOM SIDE
NOTE : PLACE TEST POINTS NEAR PIN 1 OF J7 AND THE SAME LINE
C41
Sheet[2] USB_I2C_EN 1 TP15 R63
100nF
Sheet[2] FTDI_SDA 1 TP14 10V
R64 R65 R66
1 TP13 1K U6
8

Sheet[2] FTDI_SCL

Sheet[4] SDA 1
Sheet[4] SCL 2 J7 SISPI 5 2 SPISO 10K 10K 10K
VCC

SN 3 SDI SDO
SPISO 4 DNI MCLK 6
SISPI 5 SCK
MCLK 6 NOTE : PLACE J7 NEAR J1 3
WP SPI FLASH
CSSPIN 0 R67 1 7
CON6 CS HOLD
GND

A A
4

S25FL204K0TMFI041 Lattice Semiconductor Applications


FTDI_SDA Email: techsupport@Latticesemi.com
SDA 0 DNI R91 TP12 1
Phone (503) 268-8001 -or- (800) LATTICE
SCL 0 DNI R92 FTDI_SCL Title
BANK2 I/O

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 6 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1

U5D U5F

BANK3 BANK5
N2 DIP_SW1 IO_B1 B1 G5
IO_L1 L1 PL13C/PL18C/PL23C P1 DIP_SW2 IO_C2 C2 PL1C/PL2C/PL2C PL4C/PL7C/PL7C G4
D IO_L3 L3 PL11A/PL16A/PL19A PL13D/PL18D/PL23D PL1D/PL2D/PL2D PL4D/PL7D/PL7D D
PL11B/PL16B/PL19B M3 DIP_SW3 IO_D3 D3 F3 IO_F3
IO_K4 K4 PL13A/PL19A/PL24A N1 DIP_SW4 IO_D1 D1 PL1A/PL3A/PL3A || L_GPLLT_FB PL4A/PL7A/PL8A F1 IO_F1
Figure 13. Bank 3, 4, 5 I/O

IO_L5 L5 PL11C/PL16C/PL19C PL13B/PL19B/PL24B PL1B/PL3B/PL3B || L_GPLLC_FB PL4B/PL7B/PL8B


PL11D/PL16D/PL19D M2 IO_M2 IO_E2 E2 G2 IO_G2
K5 PL14A/PL20A/PL25A N3 IO_N3 IO_E3 E3 PL2A/PL4A/PL4A || L_GPLLT_IN PL5A/PL8A/PL9A G3 IO_G3
L4 PL12C/PL17C/PL21C PL14B/PL20B/PL25B PL2B/PL4B/PL4B || L_GPLLC_IN PL5B/PL8B/PL9B
PL12D/PL17D/PL21D R1 IO_C1 C1 F5 IO_F5
PL14C/PL20C/PL25C P2 IO_D2 D2 PL2C/PL4C/PL4C PL5C/PL8C/PL9C H6 IO_H6
PL14D/PL20D/PL25D PL2D/PL4D/PL4D PL5D/PL8D/PL9D
IO_L2 L2 IO_E1 E1
IO_M1 M1 PL12A/PL17A/PL22A || PCLKT3_0 IO_F2 F2 PL3A/PL6A/PL6A || PCLKT5_0
PL12B/PL17B/PL22B || PCLKC3_0 VCCIO3 PL3B/PL6B/PL6B || PCLKC5_0
F4
G6 PL3C/PL6C/PL6C
M4 PL3D/PL6D/PL6D VCCIO5
VCCIO3/VCCIO3/VCCIO3
C42 C43 C44
1K-2K/4K/7K || 2nd_Fn. E4
0.1uF 0.1uF 0.1uF VCCIO5/VCCIO5/VCCIO5
C45 C46 C47
LCMXO3L-6900C-5BG256C 1K-2K/4K/7K || 2nd_Fn.
0.1uF 0.1uF 0.1uF
C C
LCMXO3L-6900C-5BG256C

U5E MAKE PWR TRACES


CAPABLE OF 1A

25
BANK4 VCCIO3 J8 VCCIO5
IO_G1 G1 J2 IO_J2 VCCIO3 PLACE THE RESISTORS IN THE TOP
IO_H2 H2 PL6A/PL9A/PL10A PL9A/PL13A/PL15A K1 IO_K1
PL6B/PL9B/PL10B PL9B/PL13B/PL15B 2 1
H4 H5 IO_N3 4 3 IO_H6
J6 PL6C/PL9C/PL10C PL9C/PL13C/PL15C J4 IO_M1 6 5 IO_M2
PL6D/PL9D/PL10D PL9D/PL13D/PL15D IO_L1 8 7 IO_L2 R68 R69 R70 R71
IO_H3 H3 J5 IO_L5 10 9 IO_L3
IO_H1 H1 PL7A/PL10A/PL11A PL10C/PL14C/PL16C K6 12 11
PL7B/PL10B/PL11B PL10D/PL14D/PL16D IO_J1 14 13 IO_K4
K3 IO_J2 16 15 IO_K1 4.7K 4.7K 4.7K 4.7K SW2
B B
PL10A/PL14A/PL17A K2 IO_H3 18 17 IO_J3 DIP_SW1 1 8
PL10B/PL14B/PL17B IO_H1 20 19 IO_H2 DIP_SW2 2 1 8 7
IO_J1 J1 22 21 DIP_SW3 3 2 7 6
IO_J3 J3 PL7C/PL10C/PL12A || PCLKT4_0 IO_G1 24 23 IO_G2 DIP_SW4 4 3 6 5
PL7D/PL10D/PL12B || PCLKC4_0 IO_F1 26 25 IO_F2 4 5
VCCIO4 IO_E1 28 27 IO_E2
SW-DIP4
IO_D1 30 29 IO_D2
IO_C2 32 31
H7 IO_G3 34 33 IO_C1
VCCIO4/VCCIO4/VCCIO4 J7 IO_D3 36 35 IO_B1
VCCIO4/VCCIO4/VCCIO4 C48 C49 C50 VCCIO4 IO_F3 38 37 IO_E3
40 39 IO_F5
1K-2K/4K/7K || 2nd_Fn. 0.1uF 0.1uF 0.1uF

LCMXO3L-6900C-5BG256C Header 2x20

MAKE PWR TRACES


CAPABLE OF 1A

A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK3,4,5 I/O

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 7 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
5 4 3 2 1

VCC_CORE
D +3.3V LEDs D

U5G

B2 A1
B15 GND/GND/GND VCC/VCC/VCC A16
C3 GND/GND/GND VCC/VCC/VCC G7
C14 GND/GND/GND VCC/VCC/VCC G10 R72 R73 R74 R75 R76 R77 R78 R79
D4 GND/GND/GND VCC/VCC/VCC K7
GND/GND/GND VCC/VCC/VCC 1K 1K 1K 1K 1K 1K 1K 1K
D13 K10
E5 GND/GND/GND VCC/VCC/VCC T1
E12 GND/GND/GND VCC/VCC/VCC T16
F6 GND/GND/GND VCC/VCC/VCC
F11 GND/GND/GND

1
1
1
1
1
1
1
1

H8 GND/GND/GND
H9 GND/GND/GND A2 D2 D3 D4 D5 D6 D7 D8 D9
J8 GND/GND/GND NC/NC/NC
GND/GND/GND Red Red Red Red Red Red Red Red
J9
GND/GND/GND
Figure 14. Power Decoupling and LEDs

L6
L11 GND/GND/GND

2
2
2
2
2
2
2
2

M5 GND/GND/GND
M12 GND/GND/GND
N4 GND/GND/GND LAYOUT LEDs IN A SINGLE ROW
N13 GND/GND/GND
C GND/GND/GND C
P3 Sheet[5] LED7
P14 GND/GND/GND
GND/GND/GND Sheet[5] LED6
R2 Sheet[5] LED5
R15 GND/GND/GND
GND/GND/GND Sheet[5] LED4
Sheet[5] LED3
Sheet[5] LED2
1K-2K/4K/7K
Sheet[5] LED1
Sheet[5] LED0
LCMXO3L-6900C-5BG256C

26
Note : LEDs are controlled by XO3L I/O Bank 1. When
VCCIO1 is set to a voltage less than 3.3V, observe all I/O
overdrive requirements. Refer to Lattice TN1280
"MachXO3L sysIO Usage Guide" for more information.

B B

VCC_CORE PLACE DECOUPLING CAPACITORS CLOSE TO THE U5 POWER PINS

C51 C52 C53 C54 C55 C56 C57 C58 C59 C60

10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.1uF 0.1uF 0.01uF

A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
POWER DECOUPLING AND LED'S

Size Project Schematic Rev 1.0


B MACHXO3 Starter Kit - LCMXO3L-6900C
Board Rev A
Date: 12-SEP-14 Sheet 8 of 8
5 4 3 2 1
MachXO3L Starter Kit User Guide
MachXO3L Starter Kit User Guide

Appendix B. Bill of Materials


Table 15. MachXO3L Starter Kit Bill of Materials
Item Quantity Reference Value Manufacturer MFG Pin
1 2 C1,C3 4.7 uF Panasonic ECJ-1VB0J475K
2 44 C2,C4,C6,C7,C10,C11,C12,C13,C14 0.1 uF Kemet C0402C104K4RACTU
,C15,C16,C21,C23,C24,C25,C26,C2
7,C28,C30,C31,C32,C33,C34,C36,C
37,C38,C39,C40,C42,C43,C44,C45,
C46,C47,C48,C49,C50,C53,C54,
C55,C56,C58,C59,C63
3 5 C5,C17,C19,C51,C61 10 uF Taiyo Yuden LMK107BJ106MALTD
4 2 C8,C9 18 pF Kemet C0402C180K3GACTU
5 2 C18,C20 22 uF Taiyo Yuden LMK212BJ226MG-T
6 6 C22,C29,C35,C57,C60,C64 0.01 uF Kemet C0402C103J4RACTU
7 1 C41 100 nF Murata GRM155R61A104KA01D
8 2 C52,C62 1 uF Kemet C0402C105K9PACTU
9 2 C65,C66 150 pF Kemet C0402C104K4RACTU
10 1 D1 Blue LITE-On INC LTST-C190TBKT
11 8 D2,D3,D4,D5,D6,D7,D8,D9 Red LITE-On INC LTST-C190KRKT
12 1 J1 Header 1 x 8 Molex 0022284081
13 1 J2 Mini USB-B Neltron 5075BMR-05-SM-CR
14 4 J3,J4,J6,J8 Header 2 x 20 Samtec TSW-120-07-G-D
16 1 J7 Header 1 x 6 Samtec TSW-106-07-F-S-ND
17 5 L1,L2,L3,L4,L5 600 Ohm  Murata BLM18AG601SN1D
500 mA
18 8 R1,R2,R3,R45,R68,R69,R70,R71 4.7 K Vishay CRCW06034K70FKEA
19 13 R4,R5,R6,R7,R23,R30,R35,R42,R67 0 Yageo RC0603JR-070RL
,R81,R83, R84,R85
20 2 R8,R9 2.2 K Vishay CRCW06032K20FKEA
21 2 R10,R19 12 K Yageo RC0603FR-0712KL
22 7 R11,R12,R13,R64,R65,R66,R80 10 K Stackpole Electronics Inc RMCF0603JT10K0
23 13 R14,R15,R16,R17,R18,R20,R21,R2 0 Yageo RC0603JR-070RL
2,R27,R62, R82,R91,R92
24 7 R24,R25,R26,R31,R32,R37,R38 1 Vishay CRCW06031R00JNEAHP
25 7 R28,R29,R33,R34,R39,R40,R86 1 Vishay CRCW06031R00JNEAHP
26 1 R36 100 Yageo RC0603FR-07100RL
27 10 R41,R63,R72,R73,R74,R75,R76,R7 1 K Yageo RC0603FR-071KL
7,R78,R79
28 2 R43,R44 2K Vishay CRCW06032K00JNEA
29 16 R46,R47,R48,R49,R50,R51,R52,R5 100 Yageo RC0402FR07100RL
3,R54,R55,R56,R57,R58,R59,R60,
R61
30 2 R87,R88 49.9 Vishay CRCW060349R9FKEA
31 2 R89,R90 150 Vishay CRCW0603150RJNEA
32 1 SW1 E-Switch TL1015AF160QG
33 1 SW2 DIP CTS Electrocomponents 195-4MST
35 1 U1 FTDI FT2232HL
36 1 U2 Microchip 93LC56C-I/SN
37 1 U3 Fairchild Semi FAN1112SX

27
MachXO3L Starter Kit User Guide

Table 15. MachXO3L Starter Kit Bill of Materials (Continued)


Item Quantity Reference Value Manufacturer MFG Pin
38 1 U4 On Semi NCP1117ST33T3G
39 1 U5 Lattice semi LCMXO3L-6900C-
5BG256C
40 1 U6 Spansion S25FL204K0TMFI041
41 1 X1 12 MHz TXC 7M-12.000MAAJ-T

28