VFSTR UNIVERSITY DEPT OF ECE

EXP.NO:01 DATE:
CMOS INVERTER

AIM:
- To design a CMOS Inverter and verify its functionality using transient response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on
a single input variable and CMOS is sometimes referred to as complementary-symmetry
metal– oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the
typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-
type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two
important characteristics of CMOS devices are high noise immunity and low static power
consumption. Significant power is only drawn while the transistors in the CMOS device are
switching between on and off states. Consequently, CMOS devices do not produce as much waste
heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which
uses all n-channel devices without p- channel devices.
The CMOS inverter, a logic gate which converts high input to low and low to high. When the input is
high, the n-MOSFET on the bottom switches on, pulling the output to ground. The p-MOSFET on top
switches OFF. When the input is low, the gate-source voltage on the n-MOSFET is below its
threshold, so it switches off, the p-MOSFET switches on to pull the output high. It consists of only
two transistors, a pair of one N-type and one P-type transistor. If the input voltage is „1‟ (VCC) the
P- type transistor on top is non-conducting and provides a path from GND to the output Y. The
output level therefore is „0‟. On the other hand, if the I/P level is „0‟, the P-transistor is
conducting and provides a path from VCC to the output Y, so that the output level is „1‟ while N-
type transistor is blocked.

VLSI Design LAB Page | 1

SYMBOL:

Vdd Vout=(Vin)‟
Vi Vout

gnd

TRUTH TABLE:

Vin Vout (Theoritical) Vout ( Practical)

0(0v) 1(1.8v)

1(1.8v) 0(0v)

TRANSIENT ANALYSIS:
THE SWITCHING LEVEL OPERATION (ON/OFF) OF THE CMOS INVERTER :
Vin PMOS NMOS Conduction Path of Y
T1 T2 Transistors
0(0v) ON OFF T1 1(1.8v)
1(1.8v) OFF ON T2 0(0V)

RESULT:
 MODEL VIVA QUESTIONS

1) What is the latch up problem that arises in bulk CMOS technology? How is it overcome?
2) Explain the operation of CMOS Inverter using transfer characteristic curves.
3) Distinguish between the bulk CMOS technology with the SoI technology fabrications?
4) In CMOS inverter, PMOS is preferably in pull up stage and NMOS in pull down stage. Why?
5) How CMOS inverter will acts if we interchange NMOS and PMOS positions?
6) Draw the ideal characteristics of a CMOS inverter and compare it with the
actual characteristics?
7) What is noise margin? Find out the noise margin from the actual characteristics the inverter.
8) What is the lower limit of supply voltage of a CMOS inverter? What happens if the supply
voltage is further reduced?
9) What are the various ways to reduce the delay time of a CMOS inverter?
10) Explain the commonly used technique to estimate the delay time of a CMOS inverter?
11) Define nMOS and pMOS transistors.
12) Differentiate enhancement and depletion mode transistors.
13) Compare nMOS and CMOS.
14) What is the abbreviation of ECAD.
15) What is meant by Gpdk 180nm Technology.