Abstract RAK

Abstract Generator
Rapid Adoption Kit

Version 6.1.6
Lab Manual Revision 1.0
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2 June 3, 2013
Table of Contents
Abstract
Module 1: Help Resources
Lab 1-1 Locating Cadence Online Support Solutions ................................................................................ 7
Lab 1-2 Customizing Notification and Search Preferences ....................................................................... 9
Module 2: Virtuoso Lab Setup

Lab 2-1 Virtuoso Lab Setup ....................................................................................................................... 12
Design Information ......................................................................................................................... 12
Starting the Software ....................................................................................................................... 12
Library Manager Window ............................................................................................................... 13
Viewing the Cell ............................................................................................................................. 14
Module 3: Abstract Generator Lab

Lab 3-1 Abstract .......................................................................................................................................... 18
Starting and using Abstract ............................................................................................................. 18
Extracting Logic Pin Information ................................................................................................... 20
Pin Extraction Step.......................................................................................................................... 21
Physical Pin Extraction Step ........................................................................................................... 27
Physical Pin Abstraction Step ......................................................................................................... 33
Abstract Verification Step ............................................................................................................... 43
Cadence Design Systems, Inc. 3

Module 1: Help Resources
Help Resources
Lab 1-1 Locating Cadence Online Support Solutions
Objective: To log in to Cadence Online Support (COS) and search for information
about a specific issue.
You can only complete this lab if you have access to the internet and a Cadence® Online Support
account. If you do not, your instructor might be able to perform a demo of this lab for the class.
In a web browser, enter the following:

http://support.cadence.com
Log in to Cadence Online Support with your email and password.
The Support Home page appears.
7
Help Resources
On the Support Home page, make sure the following options are selected:
 All Document Types
 All Products
In the Search field, enter congestion and click SEARCH.

A window displays the search results.
In the Troubleshooting Info section, click the match called:

What is the meaning of the colors in the routing operation?
A window opens with a description of the problem and the solution.
Close the solution window.

Note: You can filter the search results by selecting specific document types or
products which are listed to the left of the results.
8
Help Resources
Lab 1-2 Customizing Notification and Search Preferences
Objective: To set preferences so you can improve search results and receive email
notification.
You can set product and other preferences for improved search results and email notification.
Click the My Account link.
Click the Notification Preferences tab.
On the Set Email Notification Preferences page, do the following:
a. If you are interested in receiving email notifications, check the following:

Send me email notifications about new product releases.
b. Click Edit Product List. Select your products of interest.
c. Specify your preferred email format.
d. Select the document types you are interested in and the frequency of delivery.
e. Click Save.
Click the Search Preferences tab.
On the Set Search Preferences page:
a. Click Use same product and document type preferences as my Notification

Preferences.
b. Click Save.
9
Module 2: Virtuoso Lab Setup
Virtuoso Lab Setup Lab 2-1
Lab 2-1 Virtuoso Lab Setup
Objective: Setting up work directory, starting Virtuoso and viewing library cells.
In this lab, you will learn to setup your working directory to load and view physical libraries in Virtuoso. It
is important to know about the different library cell views and how to interrogate the physical layout
information. Layer information is important in determining how to create abstracts for use in Place &
Route tools.
Design Information
Once you have downloaded and extracted the lab database Abstract.tar.gz you should see the following
directory structure:
LIB Contains the Virtuoso physical libraries for this lab.

TECH Contains the Virtuoso physical library technology information
work Working directory to run Virtuoso and abstract
Starting the Software
Change to the working directory where you will run Virtuoso and Abstract
cd ABSTRACT/work
Modify the Abstract.cshrc example to point to your SOFTWARE locations and source it.
Issue command: virtuoso –log CDS.log &
This will launch the Virtuoso Command Interpreter Window GUI and create a log file CDS.log
in your current directory.
Command Interpreter Window (CIW)
12 Abstract Generator
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Abstract Generator Lab Lab 3-1
From the Command Interpreter Window (CIW) select Tools – Library Manager which will
launch the Library Manager.
Library Manager Window
The Library Manager allows you to load and view physical libraries along with the cells and
their different views.
Select the Abstract_Lib library to populate the Cell and View columns. You can then scroll down to
the BUFX2 cell and select it, or you can search for the cell name by typing BUFX2 in the window
below the Cell column.
The View column is then populated by all the different views that currently exist for BUFX2
cell.
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Viewing the Cell
In this section, you learn more about the objects on the screen, and how to view and interpret what you see
in the design window.
In the Library Manager window you can either double click on the layout view for the BUFX2
cell, or right-mouse-key select open. This will open the layout view.
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All the layers can be seen in this particular view. To view only the layers that we are interested
in you will select the Used button under the Layers heading on the left side of the form. This
will limit the layers viewable and selectable for this view.
Select the NV (None Visible) switch as shown above, and the select the layers: Metal1 drw
(drawing layer), Metal1 label (Pin Text), Metal1 pin (physical pin marker)

In this simple process, all the logic and power pins are on Metal1 layer. This is important as
these are the only layers that we are interested in using to create an abstract view. Other process
may have pins on Metal2 which we need to make allowances for during extraction.
In viewing the cell you should be able to see that the (0,0) coordinate does not fall on the lower
left corner of the cell. This is important as we need to determine the size of the actual cell that
will be represented to Place & Route tools. Measure the distance from the (0,0) coordinate
point to the edge of the Metal1, what is the distance _____
If we change the boundary locations for the extracted cell to start at the (0,0) coordinate we will
not include the full Metal1 from the layout. The final abstract of this cell will be smaller than
the layout of the cell.
To determine if this is necessary we would need to measure the total height and width of the
cell layout. What is the measured width_____ what is the measured height_____
In the work directory is the Virtuoso technology file named tech.tf, go ahead and open it up to
read in your favorite text viewer. Search for Pitch in this file, what is the Metal1 Pitch____
What is the Metal2 Pitch____
Take your measured width from above and divide it by the Metal2 pitch, what is the result___ is
the result evenly divisible with no remainder?
Take your measured height from above and divide it by the Metal1 pitch, what is the result____
is the result divisible with no remainder?
In this example the height is not divisible by the pitch. If we were take the distance from the
(0,0) coordinate to the edge of the Metal1 what is the distance___. If we subtract this distance
from both the top and bottom of the cell, what is the resulting height____. Is this distance
divisible by the pitch?
Having the cell boundary divisible is extremely important to insure that cells can abut
each other and have the routing grids align accurately. This maximizes placement
and routing densities for a standard cell library.
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Module 3: Abstract Generator Lab

Lab 3-1 Abstract
Objective: Creating Cell Abstracts From Cell Layouts
Starting and using Abstract
In the same window that you started Virtuoso from issue the command abstract &
This should launch the abstract window as shown below
The Abstract Graphics User Interface (GUI) commands can be executed from both the pull down
menu, as well as using the icons shown above.
In the upper left corner of the GUI is the Bin area, this is used to separate standard cells (Core),
Input/Output cells (IO), Power corner cells (Corner), Macro cells (Block), and cells that may not
need to have abstracts created (Ignore). This provides for the ability to have different abstraction
techniques and setting to applied to each Bin category.
Select File – Library – Open and choose the Abstract_Lib
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How many cells have been added to the Core Bin ____ how many cells have been added to the
Ignore Bin ____. On the right side of the Abstract GUI you will see a progress menu that will
have green check marks for each successful completion of each abstract step.
Extracting Logic Pin Information
Once again we will scroll down the cells shown in the Core Bin, and select the same BUFX2 cell
we selected previously in Virtuoso. This will highlight the cell that we are going to run
abstraction steps on.
When we were looking at the BUFX2 layout view we noticed that there were four pins, A, Y,
VDD, VSS. Even though the physical pins exist in the layout, we still need to assign the logical
inference to the pin. In other words, is the pin an input pin, output pin, power pin. This is
accomplished with the first step of abstraction called the “Logical” step.
Select either File – Import – Logical or select the Logical Icon
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There are several means of importing the pin logic inference, in the example above we have selected
to use the Liberty library (.lib) file. You can also choose to use a Verilog cell information file. I
have provided and example file ../LIB/vlog/typical.v.
Selecting OK should results in all the cells to have pin logic inference applied. This should result in
green check marks under the Logical column for all the cells.
Pin Extraction Step
The next step, is called the “Pins step. Usually, no pins are explicitly defined in the layout view,
so they have to be generated before you can continue the abstract generation process. The
abstract generator derives pins from the text labels in the layout view and places the locations at
the text origins.
Select Flow – Pins or the Pins icon which will launch the Pins step form shown below.

The form has four tabs, the “Map” tab is used to map text labels to physical geometries.
Since we have used the logical step previously, there is nothing we need to add to this form. For
more information on the different elements of this form or any other form within abstract, I have
enclosed the Abstract Editors Users Guide in the work directory.
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The “Text” tab is used to manipulate text labels that may contain ASCII characters that may be
reserved Verilog characters or names like VDD!, VSS! This could cause issues with Place and
Route tools. Once again it has been automatically populated and no further action is needed.

The “Boundary” tab is where we will adjust the abstracted cell boundary size based upon our
earlier calculations for pitch divisibility. As you can see from above I have subtracted 0.180u
from both the top and bottom of the layout.
Even though the actual layout will have a larger Metal power and ground pin shape, the
overlap, introduced in Place & Route, will not result in any DRC violations.
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The “Blocks” tab is used specifically for the abstraction of macro cells and or layouts from Place
& Route that you would like to create an IP block from.
Select Run.

Once complete you can go back to the Virtuoso Library Manger window and see that a new view
called “abstract.pin” has been created. If you open this view, you should see the image shown
above. The bright blue squares are the Metal1 Text markers, and the light blue rectangles are
the Metal1 drawing layers.
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Once this step is complete you will see the green check mark once again signifying correct
completion of this step. It is always a good idea that you also check the log file to look for
warnings and info tags. In this instance you will notice that since we choose to only create the
cell boundary around the Metal1 layer other layers fall outside this boundary area.
Physical Pin Extraction Step
The next step called the “Extract” step is used to extract from layout, the full physical shapes of
the pins, obstructions, and the cell boundary size.
In viewing the original layout above, you will see that there exists a Metal1 Pin layer as well
as a Metal1 drawing layer. The extract step will extract the actual pin shape as defined by
the overlap of the Metal1 Pin shape and the Metal1 drawing shapes. Any Metal1 drawing
shape that does not have a Metal1 Pin shape overlapping it will become a Metal1 routing
obstruction.
Select Flow – Extract or the Extract icon which will launch the Extract step form shown
below

The Extract form has four tabs, the “Signal” tab is automatically populated, as shown above, to
extract the metal layer and contact layer information from the layout. These layers will be used
to extract and form both the physical pin shapes as well as obstruction shapes of the cell.
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The “Power” tab, like the Signal tab is used to extract the physical shapes of the Power and
Ground pins. It is also automatically populated with both the metal and contact layer names to
assist in extracting the power pin geometries.

The “Antenna” tab is a very important in the calculation of process antenna data. This data is
used during Place &Route to model process antenna information. Place & Route tools can then
make the appropriate routing decisions to prevent process antenna violations. The data for this
table can be found in the provided ./work/ tech.tf file, under the techLayerProperties subsection
heading. In this simple exercise, we will leave this with the default settings.
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The fourth tab “General” has also been populated with the layer connectivity extraction rules.
As mentioned previously, when a Metal1 text layer overlaps a Metal1 drawing layer, the pin
geometry will be created by following the Metal1 drawing layer as well as any subsequent
contact layers. In the example above, you can see that if a Metal1 drawing layer also overlaps
Via1 and Metal2 layers, they will be extracted as part of the pin geometry.

Select Run
In viewing the BUFX2 abstract.ext view above, you will notice that the A, Y, VDD and VSS
pins have been physically extracted and a new layer called Metal1 net has been formed.
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When I also turn on the Metal1 drawing layer, you will also see a set of geometries in the middle
right of the layout that do not have Metal1 net properties and are not part of any pin. These will
become Metal1 obstructions.
Physical Pin Abstraction Step
The next step, called the abstract step is used to determine how pin shapes are to be adjusted including
both signal and blockage pin shapes. This step will create the abstract view from which a Layout
Exchange File (LEF) will be created from. Information like routing grids, placement sites, pin
fracturing, are considered during this step.

Select Flow – Abstract or select the Abstract icon which will launch Abstract step form,
shown below.
The abstract form has 7 tabs, the “Adjust” tab is used to control how pin shapes are adjusted
during connectivity extraction for creating the final required pin shapes. These pin shapes are
then fractured into rectangles. You will notice that the Signal Nets and Power Nets section are
turned off, as they are specifically used for Blocks and not for Core cells. The Power rail section
is once again automatically populated with the extracted pin width and offset from the cell.
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The Blockage tab will allow us to direct the Abstract step to determine how routing blockages
(obstructions) to be created. In the abstract.ext view shown above, you can see that both Metal1
drawing and Metal1 net layers are coincident, which defines the pin geometries. If we were to
perform the Abstract step, using default settings, the pins would have geometries defined in both
the PINS and OBS section of the LEF file. In order to abstract the correct geometries we define
that blockages will be created for Metal1 drawing layers but not if they are coincident with
Metal1 net layers, as shown above.
Change the Metal1 Geometry Specification element in your form with (Metal1 drawing andnot
Metal1 net).

The “Density’ tab allows you to generate metal density information for abstracts in LEF 5.6. The
density value in LEF helps in verifying metal density fabrication rules early in the design cycle
without having to replace the abstracts with actual layouts. This information in LEF can reduce
the memory requirements and increase the speed of metal fill tools and aid these tools to analyze
and fix the designs using abstracts. We will not make any changes to this form.
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The options on the “Fracture” tab let you control whether or not pins and blockages are fractured
depending on the PR system you are using. By using the options on the Fracture tab, you can
also control the modeling of 45-degree geometry.
In this step we will turn off the Fracturing of pin selection, as there are small Metal1 drawing /
Metal1 net layer geometries that would violate the Minimum Area Rules (MAR), as defined in
the technology file.

The “Site’ tab allows you to determine a common site requirement for the cells that are located
in the “Core’ bin. Sites tell the placer where it can place cells. All cells located in a particular
bin share a common set of properties: symmetry, class (for example, pad or core), width, and
height. These properties are used by the placer to assist in the placement process. We will not
make any changes to this form.
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The “Overlap” tab controls the creation of the overlap boundary. The overlap boundary is a
second, more detailed boundary used by placement tools to test whether cells overlap. Unlike the
PR boundary, which is always rectangular, the overlap boundary can be a rectilinear polygon.
This helps the placement tools achieve better placement density for certain types of standard
cells and rectilinear blocks. The options on this tab control whether the abstract generator is to
update the overlap boundary geometry. We will not make any changes to the default settings.

The final “Grids” tab is used to define the routing grids pitch and offset. The options on this tab
control the grid analysis function that calculates the best metal1, metal2, and metal3 routing grid
pitches and offsets for your standard cells. As you can see that metal pitch and offset have been
automatically extracted from the tech.tf file.
Select Run
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In the Abstract Editor GUI, you should now see that you have 5 green check marks, to indicate
that you have completed steps up to and including the Abstract set.

In viewing the BUFX2 abstract view from the Library Manager window you can then see the
Pins outlined in bright blue and the blockages in a lighter blue. From the Abstract Editor GUI
you can now perform a File – Export LEF and using the default values output a LEF file for the
BUFX2 cell.
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Abstract Verification Step
The abstract generator performs the following functions during the Verify step:
Checks terminals for any differences between logical and abstract views
Checks any pins and geometries off the manufacturing grid
Creates a small test design for each abstract and verifies whether it can be routed using Cadence
Encounter.
Verifies the geometry of each abstract in Cadence Encounter
You can select Flow – Verify or select the icon.

1. The Verify form has two tabs, as shown above. The first tab “Check” is used to select Terminals
and Manufacturing grid. The “Terminals” check verifies that the cell pins have both a logical
and physical shapes. The “Manufacturing Grid” check verifies that the physical pins shapes, that
have been abstracted, intersect the defined routing grid.
2. The second tab “Target” lets you specify the following:
The target system to be used to verify the abstracts
How the target system is to be invoked
The technology LEF to be used with the test design
Guidelines for creating the test design that would contain the cell abstracts to be verified
The engine to be used for routing
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How long the router engine is to run
The configuration file to be used for running the router
Router messages that can be ignored when creating the verify view
3. In this step we will use the default values. Select Run to execute the verification step.
4. In viewing the BUFX2 abstract.ver view from the Library Manager Window, shown above, we
can see that several instances of the BUFX2 cell have been Placed & Routed. We can then
visually check the routing to determine that the pins are accessible.

5. You can see from the Abstract Editor GUI, that we have successfully completed the abstraction
of the BUFX2 cell. This exercise has allowed you to properly setup your abstract forms and
setting such that you can now proceed to run abstract editor on all the cells in the CORE bin. I
would suggest that you pick a more complex cell like a register to verify your settings.
06/13/13

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Abstract Generator

Rapid Adoption Kit

Allegro® First Encounter® SignalStorm®

Module 2: Virtuoso Lab Setup

Module 3: Abstract Generator Lab

Cadence Design Systems, Inc. 3

Lab 1-1 Locating Cadence Online Support Solutions

In a web browser, enter the following:

Log in to Cadence Online Support with your email and password.

The Support Home page appears.

In the Search field, enter congestion and click SEARCH.

In the Troubleshooting Info section, click the match called:

Close the solution window.

Lab 1-2 Customizing Notification and Search Preferences

Click the My Account link.

Click the Notification Preferences tab.

On the Set Email Notification Preferences page, do the following:

a. If you are interested in receiving email notifications, check the following:

b. Click Edit Product List. Select your products of interest.

c. Specify your preferred email format.

Click the Search Preferences tab.

On the Set Search Preferences page:

a. Click Use same product and document type preferences as my Notification

Lab 2-1 Virtuoso Lab Setup

LIB Contains the Virtuoso physical libraries for this lab.

Starting the Software

Issue command: virtuoso –log CDS.log &

Command Interpreter Window (CIW)

Library Manager Window

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Viewing the Cell

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Module 3: Abstract Generator Lab

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Lab 3-1 Abstract

Objective: Creating Cell Abstracts From Cell Layouts

Starting and using Abstract

This should launch the abstract window as shown below

Select File – Library – Open and choose the Abstract_Lib

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Extracting Logic Pin Information

Select either File – Import – Logical or select the Logical Icon

Pin Extraction Step

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Physical Pin Extraction Step

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Physical Pin Abstraction Step

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Abstract Verification Step

Checks any pins and geometries off the manufacturing grid

Verifies the geometry of each abstract in Cadence Encounter

You can select Flow – Verify or select the icon.

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2. The second tab “Target” lets you specify the following:

The target system to be used to verify the abstracts

How the target system is to be invoked