

o
 Improved branch prediction unit
 reduced penalty for wrong direct jump target
 No specifics were disclosed
 µOP Cache
 instruction window is now 64 Bytes (from 32)
 1.5x bandwidth (6 µOPs/cycle, up from 4)
o Execution Engine
 Larger re-order buffer (224 entries, up from 192)
 Larger scheduler (97 entries, up from 64)
 Larger Integer Register File (180 entries, up from 168)
 Larger Retire (4 µOPs/cycle/thread, up from 4
µOPs/cycle/core)?
o Memory Subsystem
 Larger store buffer (56 entries, up from 42)
 L2$ was changed from 8-way to 4-way set associative
 Page split load penalty reduced 20-fold
 Larger Write-back buffer

 Memory
o Support for faster DDR-2400 memory
o L3$ re-gained 512 KiB/core (See §eDRAM architectural changes for the reason)
o A new coherent cache fabric implementation
 doubles the throughput of the last level cache (LLC, L3$ in this case)
miss handling
 50% improvement in bandwidth/watt

o GeForce GTX
o nVidia Titan X
o Radeon HD
o Radeon r5, r7, r9, and RX series
2. Cloud gaming
o nVidia Grid
o Radeon Sky
3. Workstation
o nVidia Quadro
o nVidia Titan X
o AMD FirePro
o Radeon Pro
4. Cloud Workstation
o Nvidia Tesla
o AMD FireStream
5. Artificial Intelligence Cloud
o Nvidia Tesla
o Radeon Instinct
6. Automated/Driverless car
o Nvidia Drive PX

based Clarkdale/Arrandale.[12][13][14][15]:3 These post-2009 single-socket chips

communicate externally via the slower DMI and PCI Express interfaces, because the
functions of the traditional northbridge are actually integrated into these processors,
starting with Lynnfield, Clarksfield, Clarkdale and Arrandale; thus, there is no need to
incur the expense of exposing the (former) front-side bus interface via the processor
socket.[16] Although the core–uncore QPI link is not present in desktop and mobile
Sandy Bridge processors (as it was on Clarkdale, for example), the internal ring
interconnect between on-die cores is also based on the principles behind QPI, at least as
far as cache coherency is concerned.[15]:10