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SpinalHDL is a new HDL based on Scala which emits Verilog or VHDL as output. This output can be integrated with existing IP and built using existing Verilog/VHDL tools
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SpinalHDL: a comprehensive hardware description language
SpinalHDL is a new HDL based on Scala which emits Verilog or VHDL as output. This output can be integrated with existing IP and built using existing Verilog/VHDL tools
SpinalHDL is a new HDL based on Scala which emits Verilog or VHDL as output. This output can be integrated with existing IP and built using existing Verilog/VHDL tools
S PINAL HDL is a new HDL language offering the ability – Base Types Bool, Bits, UInt, SInt, Enumeration. to break the limitations of the most common hardware de- – Bundle Allows to describe a data structure with the scription languages, like VHDL and Verilog. possibility to specify the direction (in, out) for each element. Useful to describe buses. 1 S PINAL HDL Structure – Reg Creates a register signal. – Vec Allows to create an array of data. S PINAL HDL is a library constructed over the Scala inter- nal DSL, allowing the user to design productively his dig- – Mem Gives the possibility to manipulate memory. ital hardware. The user designs can be converted to VHDL – BlackBox Allows to instantiate a third party HDL files for synthesis with any PLD/FPGA/ASIC specialized component. toolchain. Figure 1: S PINAL HDL structure layers 4 Lib primitives The Spinal library is separated in two parts : one - the – Interfaces Flow, handshake, fragments, ... core - providing basic elements for hardware description – Components FIFOs, inter-clock domain bridges, ... and another one on it - the lib - providing interfaces and utilities for construct powerful design and help the user in – Peripherals UART, ... his tasks. – Utils Gray conversions, counters, one-hot encoding, majority vote... 2 Highlights – Digital design analysis Tool for pipeline latency evaluation. Here’s a list of the main advantages of S PINAL HDL com- paratively to VHDL and Verilog : 5 To go further... – No restriction with the genericity of your hardware description by using the power of the Scala language. – Repositories available on Github : – No more endless wiring : create and connect complex https://github.com/SpinalHDL buses like AXI in only one text line. – Some examples : – Evolving capabilities : create your own buses defini- https://github.com/SpinalHDL/SpinalHDL/ tions and abstraction layers. blob/master/README.md – Reduce code size by a high factor - especially for wiring - allowing you to have a better visibility, more productivity and fewer headaches. – Available user friendly IDE with auto-completion, error highlight, navigation shortcut and many others. – Extract information from your digital design and generate files containing data about some latency and addresses, for example. – Bidirectional translation between bunch of bits and any data type/structures. Useful to load a complex data structure from a CPU interface. – Check for combinational loop/latch presence. – Check for user unintentional cross clock domain vio- lations.
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