A low-pass filter is added at power supply input of the UFSBI to block ripples and power-line

harmonic frequencies and to act as energy reservoir to defend against power supply sags in the
24V dc input. The filter circuit shown below:

10mH
+24V +24V

+ C1 + C2 + C3 + C4
0.1 0.1
uF uF
N24 N24

C1,C2,C3,C4 = 4700 uF,50V, Electrolytic

Capacitors C1 to C4 are 4700 microfarad ,50 V Al-Electrolytic and 0.1-microfarad capacitors are
ceramic.

The cut-off frequency of the filter is approximately 23 Hz. 

Calculated sag (drop in voltage) after 20 ms is about 4.2V. That is, in case of sag in the input
voltage dips momentarily, the capacitors in the filter can maintain the voltage to UFSBI (4 Amp
load) in the operating range for about 20ms, assuming the steady state input voltage was 24V.

Calculations:

Cut-off Frequency= 1/( x (sqroot (CxL))) = 1/(x sqroot (18800x10 -6 x 10 x 10 -3 ))

= 23.12 Hz. where C= Capacitance in Farad, L = Inductance in Henry.

Sag:

I load x T = C x V ….from capacitor energy equation

I load = load current= 4 Amp for ACE

T= time

C= Capacitance

V = Sag

For 20ms, dV = (4 x 20 x 10 -3 )/(18800 x 10 -6 ) = 4.2V