DHA Suffa University

Department of Electrical Engineering

Spring Session 2018

EE 211 Digital Logic Design

Sessional Assignment 2
Instructor: Rooh-Ul-Amin Shaikh

Student Name:TAHA BIN TARIQ Total Marks: 5 | Obtained:

Roll Number: EE161090 Deadline: 30th April 2018
Date: 30th April 2018 Section: EE - 4B | 4C

CLO2 Assessment
1. Develop the truth table for the following circuit:

Truth Table

A B C D X
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

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 DHA Suffa University
Department of Electrical Engineering
Spring Session 2018
2. Develop and AND-OR Invert Circuit for a power saw that removes power (logic 0) if the guard is
not in place (logic 0) and the switch is on (logic 1) or the switch is on and the motor is too hot (logic1).
3. Use NAND gates, NOR gates or combination of both to implement the following logic expression:
̅ B + CD + (𝑨
X=𝑨 ̅̅̅̅̅̅̅̅ ̅̅̅̅)
+ 𝑩) (ACD+𝑩𝑬

4. Implement a logic circuit for the truth table given below:

S.O.P will be applied

(A+B+C’) (A+B’+C’) (A’+B+C’)

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 DHA Suffa University
Department of Electrical Engineering
Spring Session 2018
5. For the circuit shown, draw the waveforms at the numbered points in proper relationship to each
other:

Output

6. Show how two 74LS283 adders can be connected to form an 8- bit parallel adder. Show output bits
for the following 8-bit input numbers. 10111001 and 10011110

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 DHA Suffa University
Department of Electrical Engineering
Spring Session 2018
7. Demonstrate the application of encoder in keyboard.
ENCODER APPLICATION

8. The serial data-input waveform (Data in) and data select inputs (SO and S1) are shown in the figure
below. Determine the data output waveforms on DO through D3 for the de-multiplexer in the figure.

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 DHA Suffa University
Department of Electrical Engineering
Spring Session 2018
ANSWER:
The selected lines go through a binary sequence so that each successive input bit is routed to D0,D1,D2
and D3 in sequence, as shown in output waveforms.
9. A 4-bit synchronous binary counter is shown in the figure below: Each flip flop is negative edge
triggered and has a propagation delay for 10 (ns). Develop a timing diagram showing the Q output of
each flip flop and determine the total propagation delay time from the triggering edge of the clock
pulse until a corresponding change can occur in the state of Q3.Also determine the maximum clock
frequency at which the counter can be operated.

ANSWER: