DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING 18EC53

DESIGN OF FAULT TOLERANT SYSTEM FOR THE ON-BOARD COMPUTER

OF STUDSAT-2

Rithesh (4NM14EC120) Srinivas Pai A (4NM14EC160)

Sachin K (4NM14EC126) Vinod K (4NM14EC190)

Guide: Dr. SHIVAPRAKASHA K.S., Associate Professor, Dept. of E&C Engineering

ABSTRACT

Keywords: STUDSAT-2, Warm Redundancy, Fault Handling, Flash Integrity Check, Cyclic
Redundancy Check (CRC), In-Application Programming.

Introduction: STUDent SATellite (STUDSAT-2) is India’s first Twin-Nano satellite project which aims to
demonstrate in-orbit separation, inter-satellite communication and drag-sail mechanism. The mission
life of this type of satellites is less because of two main reasons. First reason is lower energy capacity
and the second is Commercial Off-The-Shelf components which are fault intolerant to withstand the
space environment. On-Board Computer (OBC) plays a vital role in functioning of the satellite. Even a
slight malfunction of OBC would result in failure of entire mission. Malfunction of OBC may be either
due to hardware or software flaws.

Objectives:
1. Periodic monitoring of Primary System by Redundant System for readiness.
2. Introducing redundancy to both software and hardware, along with Fault Handling techniques.
Thus, providing reliability to the whole system.
3. Flash Integrity Check using CRC and recovery of flash using In-Application programming (IAP).
4. Establishing inter-processor communication between the C&DH and ADCS with the help of
UART.
5. Optimising the power usage by reducing the operating frequency and hence increasing the
battery life.

Methodology: Initially the primary system will be in active state and the redundant system will be in
stand-by mode (lowest power consumption mode). The redundant system will wake up periodically
and will check for the readiness of the primary system. If it detects that the primary has failed, it will
take over the control of the satellite.
A periodic task whose sole function is to check the integrity of the flash memory will detect the
corruption of flash and will invoke a function which will re-program the corrupted flash. The function
which is used to re-program the flash will read the back-up copy of the flash from SD card and will
program the flash memory.
During eclipse period power generation is not possible and thus the system has to operate on battery
power. Hence decreasing the frequency of the clock which drives the microcontroller and its
peripherals to optimum value will decrease the power consumption. There by increasing the battery
life.
Results and Conclusions:
1. Reliability of the satellite is increased by introducing redundancy to the OBC of the system.
2. Corruption of the flash memory is detected by using CRC and the flash is recovered through IAP.
3. Sensor data present in different subsystems is transferred to the C&DH subsystem and is then
downlinked to the earth station.
4. The power consumption is found to be decreased to 50% of its nominal value by reducing the
run-time frequency to half the normal frequency of operation. Hence the battery-life of the satellite
is made longer.

N.M.A.M. Institute of Technology, Nitte; EXPRO 2018 Abstract Volume 18

18EC53