3/21/2018 Assignment 6

moodle_1702 Robin Bansal

ANALOG ELECTRONIC CIRCUITS

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Assignment 6

Started on Thursday, 21 September 2017, 10:41 PM

State Finished
Completed on Friday, 29 September 2017, 10:56 PM
Time taken 8 days
Grade 10.00 out of 10.00 (100%)
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Question 1 Consider the MOS differential pair in the circuit below. VC M is 2.1 volts, I0 is 4 milli-
Correct amperes, RD is 0.55 kilo-ohms. Further, the VT of the devices is 0.9 volts. What is the
minimum allowable supply voltage if the transistors must remain in saturation? Give your
Mark 1.00 out of
answer in volts.
1.00

Flag question

Answer:
2.3

Correct!
To maintain the devices in saturation, VDS ≥ VGS − VT . This means that the minimum
drain voltage is the gate voltage minus VT .
Therefore the minimum voltage at the drains is VC M − VT , that is 1.2 volts.
The current through the resistors is 2 milli-amperes. This means that the drop across the
resistors at DC is 1.1 volts. Therefore the minimum power supply voltage is 2.3 volts.

+
The correct answer is: 2.3 /- 0.115

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3/21/2018 Assignment 6
Question 2
In the circuit shown in the previous question, with RD , I0 and VT defined as earlier, the
Correct power supply voltage is fixed at 5 volts. Kn of the input devices are 40 milli-siemens per
Mark 1.00 out of volt, Kn of the device used to make the current source is 80 milli-siemens per volt.
1.00 What is the maximum input common mode swing that is allowed, such that all devices
Flag question remain in saturation? (Maximum VC M minus minimum VC M .) Give your answer in volts.

Answer:
3.45

Correct!

We need to find VC M max

and VC M min
to find the maximum input common mode swing.
The drain of the input NMOS is at VDD − I0 RD /2. Therefore, the gate voltage cannot go
above a VT higher than that. Therefore, VC M = VDD − I0 R D /2 + VT.
max

The drain voltage of the tail current source should be at least VOV for that NMOS to remain
in saturation. Therefore, the minimum voltage possible at the source of the input NMOS is
VOV . Now, the gate of the input NMOS should be VOV + VT higher than the source

voltage (notice that VOV is same for both NMOSs). Therefore, VC M = 2VOV + VT .
min

To find VOV , use the current equation of MOSFET for the tail current source: I0 = Kn V
2

OV

+
The correct answer is: 3.4527864045 /- 0.1

Question 3 In the circuit below, Kn is 2.6 milli-siemens per volt, Kp is 2.7 milli-siemens per volt. All the
Correct devices have a VT of 0.3 volts. The λ of all the devices are 0.1 per volt. I0 is 0.2 milli-
amperes. What should be R such that the differential gain of the circuit (differential output /
Mark 1.00 out of
differential input) is 31.5? Give your answer in kilo-ohms.
1.00

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3/21/2018 Answer: Assignment 6

80.8

Correct!

First the small signal parameters, gm and r o of the nMOS and the pMOS devices is to be
computed. The current through the devices is I0 /2 . Next, the small signal half circuit has to
be used. In the half circuit, the gate of the pMOS is at 0 volts, the source of the nMOS
device is also at 0 V. The resistor is between the output and ground.
The output impedance of such a structure is just r op ∥ r on . The short circuit
∥ R

transconductance is gm . This gives the differential gain as:

A v = gm (r op ∥ r on ∥ R)

Here, Av is given, R has to be evaluated.

+
The correct answer is: 81 /- 4.05

Question 4 In the earlier circuit, assume that the tail current source is actually designed with an nMOS
Correct device of the same λ as the others. What is the common mode gain? (Common mode gain
in this case is the sum of the outputs by the sum of the inputs.) Give your answer in
Mark 1.00 out of
decibels.
1.00
For reference, Kn is 2.6 milli-siemens per volt, Kp is 2.7 milli-siemens per volt, I0 is 0.2
Flag question milli-amperes, λ of all the devices is 0.1 per volt.

Answer:
-40.5

Correct!
The pMOS is effectively diode-connected, and has an impedence of 1/gmp . The effective
resistance of the current source, after breaking up the common-mode half circuit is r o . This
gives an overall common-mode gain of approximately:
−(1/gmp )/r o

The above has to be expressed in dB.

+
The correct answer is: -40.586909581612 /- 0.5

Question 5
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3/21/2018
Correct In the earlier circuit, suppose the two input nMOS 6devices are no longer identical, but are
Assignment

Mark 1.00 out of

mismatched by 2%. What this means is that Kn for the left side device is 0.99× 2.6 milli-
1.00
siemens per volt, while the Kn for the right side device is 1.01× 2.6 milli-siemens per volt.
All other circuit parameters are as earlier. The value of the resistor R being used is 81 kilo-
Flag question ohms.
What is the common-mode to differential-mode gain? (Difference of outputs / average of
inputs). Give your answer in decibels.

Answer:
-38.32

Correct!

The two devices will now have 1.01gm and 0.99gm. When excited by the same voltage at
the gate, the source voltage can be computed as approximately
vs = vcm 2gm /(2 + gm r o )

Now the differential current drawn on the drains is:

0.02gm /(2 + gm r o ) on each side.
This creates a differential voltage:
0.04gm (r o ∥ r o ∥ R)/(2 + gm r o ) = 0.04A v /(2 + gm r o )

The above is equal to -38.32343328386 dB. Av is the differential gain given earlier,
31.528288595499, r o is that of the individual devices, 100 kilo-ohms, gm is
1.0198039027186 milli-siemens. The value of the resistor, R was used as 81 kilo-ohms.

+
The correct answer is: -38.32343328386 /- 0.5

Question 6 In the differential circuit below, all the MOS devices are identical with a K of 2.71 milli-
Correct siemens per volt. Further, the devices have a λ of 0.18 per volt. The tail current source, I0
is of 665 micro-amperes, and also consists of a single MOS device with the same λ as
Mark 1.00 out of
above. RD and RS are 4.6 and 0.6 kilo-ohms respectively.
1.00

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3/21/2018 Assignment 6

The input is differential, with two input terminals, v1 and v2 . However, the output is single-
ended, with only one output voltage of interest, vout . What is the differential mode gain, i.e.,
v

v −v
? (Pay attention to the sign.)
out

1 2

Answer:
1.782

Correct!

I0 splits into two equal parts at the DC operating point, to bias the two input MOS devices.
This means, the current through each input MOS device is 332.5 micro-amperes. As a
result, gm and r o of these devices are:
−−−−
gm = 2√K ID = 1.9 milli-siemens, and
r o = 1/(λID ) = 16.32 kilo-ohms.
The differential mode half circuit can be drawn. It turns out to be a source degenerated
common-source amplifier. The output impedance is: RD ∥ (r o + RS + gm r o RS ). To
compute the short circuit current, we can first obtain the voltage at the source as
g g r
v1 . This gives us the short circuit transconductance as:
m m o

g +GS +g g ro RS +ro +RS

m o m

The voltage gain from any one input to its output is:
g ro RD
m
= 3.5548289337268 .
ro +RS +RD +g ro RS
m

Now this is the differential input to differential output gain. However, we do not seem to be
interested in the differential output. Instead, we are looking only at one of the two outputs. In
such a case, the gain will be half of the above, i.e., 1.7774144668634.
+
The correct answer is: 1.7774144668634 /- 0.17774144668634

Question 7 What is the common mode gain of the earlier circuit? Common mode gain in this case is
Correct defined as \frac{v_{out}}{(v_1+v_2)/2}. Assume that the tail current source has the same λ
as the other devices. Give your answer in decibels.
Mark 1.00 out of
1.00

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3/21/2018 Answer: Assignment 6

-11.8223

Correct!

As before:
g m = 2 KI 0 / 2 = 1.9 milli-siemens, and
√
\(r_o = 1/(\lambda I_0/2) = 16.32 kilo-ohms.
For the tail current source, \(r_o = 1/(\lambda I_0) = 8.16 kilo-ohms.
The common mode half circuit can be drawn. It turns out to be a source degenerated
common-source amplifier, where the resistance on the source is 16.92 kilo-ohms.
g m r oR D
The voltage gain from any one input to its output is: r o + R S + R D + g m r oR S
, where R S is no longer
the given R S, but 16.92 kilo-ohms.

Now this is the gain from one input to the corresponding output. This is the same as v out / v cm
, where v cm is the average of the two inputs.
+
The correct answer is: -11.917747145389 /- 0.1

Question 8 What is the CMRR (common mode rejection ratio)? Give your answer in decibels.
Correct
Answer:
Mark 1.00 out of
1.00 16.84

Flag question

Correct!

CMRR is differential gain divided by common mode gain.

In dB, differential mode gain minus common mode gain.
+
The correct answer is: 16.913521359158 /- 1

Question 9 A complete fully differential folded cascode amplifier is shown below. The circuit includes
Correct biasing circuits. The labels V1, V2, V3, V4 are used to avoid drawing wires that cross over
the entire circuit; i.e., if two nodes are labelled as V2, then it is to be understood that these
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two nodes are connected with a wire. Further, the numbers against the devices indicate
1.00
their \(W/L\) ratios.
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3/21/2018 Assignment 6

\(\mu_n C_{ox}'/2\) is given to be 1.235 milli-siemens per volt. \(\mu_p C_{ox}'/2\) is given to
be 0.6175 milli-siemens per volt. \(\lambda\) of all the devices is 0.43 per volt. \(V_T\) of
both nMOS and pMOS devices is 0.3 volts. \(R\) is 14.5 kilo-ohms.

What is the differential voltage gain? (Differential gain is defined as \((v_{out}^+ -

v_{out}^-)/(v_{in}^+ - v_{in}^-)\).) Use correct sign.

Answer:
-170.36

Correct!

+
The correct answer is: -170.32466302338 /- 8.516233151169

Question 10 In the earlier circuit, what is the common mode gain? (Common mode gain is defined as \
Correct ((v_{out}^+ + v_{out}^-)/(v_{in}^+ + v_{in}^-)\).) Use correct sign.

Mark 1.00 out of

Answer:
1.00
-8.109
Flag question

Correct!

+
The correct answer is: -8.1062741050761 /- 0.40531370525381

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3/21/2018 Assignment 6

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