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No.

0242
32LD8A20
32LD8A20A
37LD8A20
SERVICE MANUAL 37LD8A20A
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH

CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.

Data contained within this Service


manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité» Les données fournies dans le présent
et les «Notices de sécurité du produit» présentés dans le présent manuel. manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.

Die in diesem Wartungshandbuch


VORSICHT: enthaltenen Spezifikationen können sich
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise zwecks Verbesserungen ändern.
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.

Contents
1. Introduction 11. Service Menu Settings
2. Tuner 12. Block Diagrams
3. Audio Amplifier Stage 13. Troubleshooting Guide
4. Power Stage 14. Connectors
5. Microcontroller (VCTP) 15. Replacement Parts
6. DRX 3961A 16. Assembly Drawing
7. Serial 64K I2C EEPROM 17. Schematic Diagrams
8. Class AB Stereo Headphone 18. PCB Layout Diagrams
Driver
9. SAW Filter X6966M
10. IC Descriptions

SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT

Colour Television
December 2007
1. INTRODUCTION

17MB22 Main Board consists of Micronas concept , VCTP as controller. This IC is


capable of handling Audio processing, video processing, motion adaptive up
conversion(MAU), Scaling-Display processing and FPD control (DPS), unified memory
for audio video and Text, 3D comb filter, PC connectivity, OSD and text processing.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards
as B/ G, D/K, I/I’ and L/L’ including German and NICAM stereo.

Sound system output is supplying 2x 8W (10%THD) for stereo 8Ω speakers


Supported peripherals are:

1 RF input VHF1, VHF3, UHF @ 75Ohm


1 FAV input
2 SCART sockets
1 SVHS input
1 Stereo Headphone input
1 YPbPr
1 PC input
1 HDMI input
1 Stereo audio input for PC

2. TUNER
As the thickness of the TV set has a limit, a horizontal mounted tuner is used in the
product, which is suitable for CCIR systems B/G, H, L/ L’, I/I’ and D/ K. The tuning is
available through the digitally controlled I2C bus (PLL). Below you will find info on the
Tuner in use.

2.1 General description of UV1316


The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet
a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR
systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed for
direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.

2.2 Brief description


The DTT 713XX is designed for digital terrestrial reception in VHFIII and UHF, compliant
with the European digital terrestrial standard ETS 300744. In addition it covers all channels
from 44.25MHz to 863.25MHz. It is a two band concept, VHF and UHF, with VHF switched
between VHF low (VHFI) and VHF high (VHFIII). Optional an antenna loop through function,
a combiner to feed through an RF-modulator signal to the TV output, a buffered 4MHz
crystal oscillator output, a DC/DC converter to generate 32V tuning voltage can be provided.
Instead of RF modulator input, an antenna power supply input is possible.
The DTT 713XX has the possibility to activate an internal wide band RF AGC.
Tuning, band switching and internal RF AGC is controlled via I2C bus. The metal housing
is in world standard tuner size. The module complies with the requirements of radiation,
signal handling capability and immunity interference of CENELEC standards EN 55013
and EN 55020.
3. AUDIO AMPLIFIER STAGE WITH MP7722

3.1 General Description

The MP7722 is a stereo 20W Class D Audio amplifier, intended for use as low
frequency power amplifier in a wide range of applications in radio and TV sets.
It uses a minimum number of external components to complete a stereo Class D audio
amplifier.

3.2 Features

x 2 x 20W Output at VDD = 24V into a 4Ÿ load


x THD+N = 0.06% at 1W, 8Ÿ
x 93% Efficiency at 20W
x Low Noise (190μV Typical)
x Switching Frequency Up to 1MHz
x 9.5V to 24V Operation from a Single Supply
x Integrated Startup and Shutdown Pop Elimination Circuit
x Thermal and Short Circuit Protection
x Integrated 180mŸ Switches
x Mute/Standby Modes (Sleep)
x Thermally Enhanced 20-Pin TSSOP Package with Exposed Pad
3.3 Applications

x Surround Sound DVD Systems


x Televisions
x Flat Panel Monitors
x Multimedia Computers
x Home Stereo Systems

3.4 Absolute Ratings

3.5 Pinning

4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit and power interface board. The main power supply unit is
designed for 24V and 12V DC supply. Power stage which is on-chasis generates +24V
for audio amplifier, 1.8V and 3.3V stand by voltage and 8V, 12V, 5V and 3.3Vsupplies
for other different parts of the chassis.
5. MICROCONTROLLER (VCTP)

5.1 General Features


The VCT 6wxyP is dedicated to high-quality FPD and double-scan TV sets. The VCT
6wxyP family is based on functional blocks contained and approved in existing products
like VCT 49xxI, VSP 94x5B, and DPS 94xxA.
Each member of the family contains the entire audio, video, up-conversion processing
for 4:3 and 16:9 50/
60 Hz progressive or 100/120 Hz interlaced stereo TV sets and the control/data
interface for flat-panel displays. The integrated microcontroller is supported by a
powerful OSD and graphics generator with integrated teletext acquisition.
Controller:
x High-performance 8-bit microcontroller, 8051 compatible
x Up to 512 kByte in system program Flash
x WST, PDC, VPS, and WSS acquisition
x Closed caption and V-chip acquisition
x Up to 10 page on chip teletext memory
x Up to 1000 pages with internal memory
x Up to 30 GPIO
Audio:
x Multistandard TV-sound demodulation:
-All A2/NICAM standards
-BTSC/SAP with DBX
-EIA-J
x Baseband sound processing for loudspeaker channel:
-Volume, bass, treble, loudness, balance
-Spatial effect (e.g. pseudo stereo)
-Micronas AROUND
(Virtual Dolby Surround optional)
-Micronas BASS
-BBE
-SRS WOW
-SRS TruSurround XT
-Lipsync function
Video:
x CVBS, S-VHS, YCrCb and RGB inputs
x HDTV YPrPb and RGB inputs
x ITU656 input
x Linedoubling with vertical detail enhancement (without internal memory)
x State of the art motion adaptive up conversion (with internal memory)
x 4H adaptive comb filter for PAL/NTSC (without internal memory)
x 3D comb filter for PAL/NTSC (with internal memory) (Optional)
x Internal SDR RAM interface
x Powerful horizontal and vertical scaling inclusive
x Nonlinear horizontal scaling “panorama vision”
x picture adaptive image improvements (DCE, LSE, CTI, SCE, NCE)
x non-linear colorspace enhancement (NCE) with 32 programmable slopes and
sections per RGB component (blue stretch, static black stretch, gamma
correction).
x Dynamic contrast enhancement (DCE) (histogram based black stretch with peak
black and activity detection and contrast adaption)
x Luma sharpness enhancement (LSE)
x Colour transient improvement (CTI)
x Selective colour enhancement (SCE) for skin tone correction, blue and green
stretch

5.2 Multistandard Sound Processor (MSP) Features


The MSP receives the analog Sound IF signal from the tuner and converts it to digital
with its internal SIF-AD converter. The MSP is able to demodulate all TV sound
standards worldwide including the digital NICAM system. TV stereo sound standards
that are unavailable for a specific VCTP version are processed in analog mono sound of
the standard. In that case, stereo or bilingual processing will not be possible.

x Sound IF input
x Worldwide FM/AM-mono sound demodulation
x FM stereo sound demodulation (A2, EIA-J)
x BTSC/SAP demodulation with DBX
x NICAM demodulation
x FM radio & RDS/RBDS demodulation
x Automatic standard detection
x automatic volume correction (AVC)
x Automatic sound select
x Baseband processing for loudspeaker channel:
volume, bass, treble, loudness, balance
-spatial effect (e.g. pseudo stereo)
-Micronas AROUND
-Micronas BASS
-SRS WOW (optional)
-SRS TruSurround XT (optional)
-delayline for lipsync function (shared memory)
-Virtual Dolby Surround (optional)
x 1 I2S input for external ATSC/DVD decoder
x 1 I2S interface for audio delayline
x 1 SPDIF output
x Audio i/o switches
-4 analog stereo line inputs and 2 analog stereo line outputs (configurable 5
analog stereo line inputs and 1 analog stereo line output)
-1 analog stereo loudspeaker output
-1 analog subwoofer output
-1 analog stereo headphone output

5.3 Video Features


The TVT is a Teletext decoder for decoding World System Teletext data, as well as
Video Programming System (VPS), Program Delivery Control (PDC), and Wide-Screen
Signalling (WSS) data used for PALplus transmissions (line 23). The device also
supports Closed Caption acquisition and decoding.
The TVT provides an integrated general-purpose, fully 8051-compatible microcontroller
with television-specific hardware features. The microcontroller has been enhanced to
provide powerful features such as memory banking, data pointer, additional interrupts,
shared memory access etc.
The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB. For operation the
code is fetched from a 16bit FLASH, which can be addressed up to 1 MByte.
The controller with dedicated hardware does most of the internal TTX acquisition
processing, transfers data to/from external memory interface, and receives/transmits
data via I2C-bus interface. In combination with dedicated hardware, the slicer stores
TTX data in a VBI buffer of 1 KB. The microcontroller firmware performs all the
acquisition tasks (hamming and parity checks, page search, and evaluation of header
control bits) once per field. Additionally, the firmware can provide high-end Teletext
features like Packet-26 handling, FLOF/TOP and list-pages. The interface-to-user
software is optimised for minimal overhead. TVT is realised in deep submicron
technology with 1.8 V supply voltage and 3.3 V I/O (TTL compatible).

x 16 analog video inputs (4xCVBS/Y/C + 3xRGB/YCrCb/YPrPb)


x Video input switch matrix
x 3 analog video outputs (integrated Y+C adder)
x 24-bit RGB/H/V/clk input (e.g. ext. DVI decoder) or 656 8bit input
x 656 8bit input/output (e. g. for external high-end up conversion by FRCA)
x Multi-standard color decoder PAL/NTSC/SECAM including all substandards
x 2D adaptive comb filter for PAL/NTSC with vertical peaking
x 3D-comb filter for PAL/NTSC (Optional)
x Macrovision compliant multi-standard sync processing
x Trilevel sync slicer for HDTV
x Macrovision detection
x High-quality soft mixer controlled by Fast Blank (alpha blending)
x Fastblank monitor via I2C
x Noise measurement
x Letterbox detection (auto-wide)
x Split screen (OSD and video side by side) and AV PIP

5.4 Controller Features

The TVT is a Teletext decoder for decoding World System Teletext data, as well as
Video Programming System (VPS), Program Delivery Control (PDC), and Wide-Screen
Signalling (WSS) data used for PALplus transmissions (line 23). The device also
supports Closed Caption acquisition and decoding.
The TVT provides an integrated general-purpose, fully 8051-compatible microcontroller
with television-specific hardware features. The microcontroller has been enhanced to
provide powerful features such as memory banking, data pointer, additional interrupts,
shared memory access etc.

x High performance 8-bit microcontroller, 8051 instruction set compatible


x 81 MHz system clock, two machine cycles per instruction
x On-chip debug support (OCDS)
x Up to 512 kByte in system program Flash
x 256 byte on-chip program RAM
x 128 byte on-chip extended stack RAM
x 4-level, 24-input interrupt controller
x Patch module for 16 ROM locations
x Two 16-bit reloadable timers
x Capture compare timer for infrared decoding
x Watchdog timer
x Uart
x Real time clock
x PWM units (2 channels 14-bit, 6 channels 8-bit)
x 8-bit ADC (4 channels)
x I2C bus master/slave interface
x Up to 32 programmable I/O ports

5.5 OSD and Teletext Features


The on-chip display unit for displaying Level 1.5 Teletext data can also be used for
customer-defined onscreen displays.
The TVT has an internal XRAM of 32 KB and a BOOT ROM of 4 KB. For operation the
code is fetched from a 16bit FLASH, which can be addressed up to 1 MByte.
In combination with dedicated hardware, the slicer stores TTX data in a VBI buffer of 1
KB. The microcontroller firmware performs all the acquisition tasks (hamming and parity
checks, page search, and evaluation of header control bits) once per field. Additionally,
the firmware can provide high-end Teletext features like Packet-26 handling, FLOF/TOP
and list-pages. The interface-to-user software is optimised for minimal overhead.

5.6 Port Allocation


6. DRX 3961A

6.1 General Desription

The DSP-based Analog TV IF Demodulator DRX 396xA performs the entire


multistandard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation,
and generation of the sound IF (SIF), requiring only one SAW filter. The IC is designed
for applications in TV sets, VCRs, PC cards, and TV tuners.
The alignment-free DRX 396xA does not need special external components. All control
functions and status registers are accessible via I2C bus interface.

6.2 Features

x Multistandard QSS IF processing with a single SAW


x Highly reduced amount of external components (no tank circuit, no
potentiometers, no SAW switching)
x Programmable IF frequency (38.9 MHz, 45.75 MHz, 32.9 MHz, 58.75 MHz,
36.125 MHz etc.)
x Digital IF processing for the following standards: B/G, D/K, I, L/L’, and M/N
x Standard specific digital post filtering
x Standard specific digital video/audio splitting
x Standard specific digital picture carrier recovery:
-Alignment-free
-Quartz-stable and accurate
-Stable frequency lock at 100% modulation and overmodulation up to
150%
-Quartz-accurate AFC information
x Programmable standard specific digital group delay equalization
x Automatically frequency-adjusted Nyquist slope, therefore optimum picture and
sound performance over complete lock in frequency range
x Standard-specific digital AGC and delayed tuner AGC with programmable tuner
take-over point
x Fast AGC due to linear structure
x Adaptive back porch control, therefore fast positive modulation AGC
x No sound traps needed at video output
x SIF output with standard-dependent pre-filtering and amplitude-controlled output
level
x Optimal sound SNR due to carrier recovery without quadrature distortions
x FM radio capability without external components and with standard TV tuner
x Prepared for digital TV (DVB-C, DVB-T, ATSC)
x I2C bus interface

7. SERIAL 64K I2C EEPROM M24C64WBN6

7.1 General Description

M24C64WBN6 is a 64 Kbit Electrically Erasable PROM. These I2C-compatible


electrically erasable programmable memory (EEPROM) devices are organized as
8192x8 bits. It supports 400kHz Protocol I2C uses a two-wire serial interface,
comprising a bi-directional data line and a clock line.
The M24C64WBN6 is available in the standard 8-pin (Vcc, WC, SDA (I2C data), SCL
(I2C clock), Vss,E0,E1,E2). WC pin is critcal pin. If WP is high, writing is not possible to
EEPROM. If WP is low, writing is possible to EEPROM.

7.2 Features

x Two-Wire I2C Serial Interface Supports 400kHz Protocol


x Single Supply Voltage:
– 4.5 to 5.5V for M24Cxx
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
x Write Control Input
x BYTE and PAGE WRITE (up to 32 Bytes)
x RANDOM and SEQUENTIAL READ Modes
x Self-Timed Programming Cycle
x Automatic Address Incrementing
x Enhanced ESD/Latch-Up Protection
x More than 1 Million Erase/Write Cycles
x More than 40-Year Data Retention

7.3 Absolute Maximum Ratings

7.4 Pinning

8. CLASS AB STEREO HEADPHONE DRIVER TDA1308

8.1. General Description


The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8
or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has
been primarily developed for portable digital audio applications. It gets its input from two
analog audio outputs (DACA_L and DACA_R) of MSP 34x0G. The gain of the output is
adjustable by the feedback resistor between the inputs and outputs.

8.2 Features
x Wide temperature range
x No switch ON/OFF clicks
x Excellent power supply ripple rejection
x Low power consumption
x Short-circuit resistant
x High performance
x High signal-to-noise ratio
x High slew rate
x Low distortion
x Large output voltage swing.
x Power supply maximum 60 mW to 32Ÿ (THD<0.1%)
x 5V single supply
x SNR 110 dB
x Power supply ripple rejection
x Typically 3 mA supply current at no load

8.3. Pinning

9. SAW FILTER X6966M


9.1 Features:
- IF filter for digital cable TV
- Plastic package SIP5K
9.2 Pin configuration:
1 Input
2 Input - ground
3 Chip carrier - ground
4 Output
5 Output

9.3 Frequency response:


10. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM
LM1117
LM1086
MP1593
FDC642P
SIL9011
24LC02
μPA672T
M74HC4052
Max809
24LC21

10.1. LM1117
10.1.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at
800mA of load current. It has the same pin-out as National Semiconductor’s industry
standard LM317. The LM1117 is available in an adjustable version, which can set the
output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF
tantalum capacitor is required at the output to improve the transient response and
stability.

10.1.2. Features
x Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
x Space Saving SOT-223 Package
x Current Limiting and Thermal Protection
x Output Current 800mA
x Line Regulation 0.2% (Max)
x Load Regulation 0.4% (Max)
x Temperature Range
x LM1117 0°C to 125°C
x LM1117I -40°C to 125°C

10.1.3. Applications
x 2.85V Model for SCSI-2 Active Termination
x Post Regulator for Switching DC/DC Converter
x High Efficiency Linear Regulators 15
x 32” TFT TV Service Manual
x Battery Charger
x Battery Powered Instrumentation
10.1.4. Absolute Maximum Ratings

10.1.5. Pinning

10.2. LM1086
10.2.1. General Description
The LM1086 is a low dropout three terminal regulator with 1.5A output current capability.
The output voltage is adjustable with the use of a resistor divider. Dropout is guaranteed
at a maximum of 500 mV at maximum output current. It's low dropout voltage and fast
transient response make it ideal for low voltage microprocessor applications. Internal
current and thermal limiting provides protection against any overload condition
that would create excessive junction temperature.

10.2.2. Features
x Low Dropout Voltage 500mV at 1.5A Output Current
x Fast Transient Response
x 0.015% Line Regulation
x 0.1% Load Regulation
x Current Limiting and Thermal Protecion.
x Adjustable or Fixed Output Voltage(1.8, 2.5, 2.85, 3.0, 3.3, 3.45, 5.0V)
x Surface Mount Package SOT-223 & TO-263 (D2 Package)
x 100% Thermal Limit Burn-in

10.2.3. Applications

x Battery Charger
x Adjustable Power Supplies
x Constant Current Regulators
x Portable Instrumentation
x High Efficiency Linear Power Supplies
x High Efficiency "Green" Computer Systems
x SMPS Post-Regulator
x Power PC Supplies
x Powering VGA & Sound Card

10.2.4. Absolute Maximum Ratings

10.2.5. Pinning

10.3. MP1593
10.3.1. General Description
The MP1593 is a step-down regulator with an internal Power MOSFET. It achieves 3A
continuous output current over a wide input supply range with excellent load and line
regulation. Current mode operation provides fast transient response and eases loop
stabilisation. Fault condition protection includes cycle-by-cycle current limiting and
thermal shutdown. Adjustable soft-start reduces the stress on the input source at turn-
on. In shutdown mode the regulator draws 20μA of supply current. The MP1593
requires a minimum number of readily available external components to complete a 3A
step down DC to DC converter solution.
10.3.2. Features
x 3A Output Current
x Programmable Soft-Start
x 100mȍ Internal Power MOSFET Switch
x Stable with Low ESR Output Ceramic Capacitors
x Up to 95% Efficiency
x 20μA Shutdown Mode
x Fixed 385KHz Frequency
x Thermal Shutdown
x Cycle-by-Cycle Over Current Protection
x Wide 4.75 to 28V Operating Input Range
x Output Adjustable from 1.22V
x Under Voltage Lockout
x Available in 8-Pin SOIC Package

10.3.3. Applications
x Distributed Power Systems
x Battery Chargers
x Pre-Regulator for Linear Regulators
x Flat Panel TVs
x Set-Top Boxes
x Cigarette Lighter Powered Devices
x DVD/PVR Devices

10.3.4. Absolute Maximum Ratings


10.3.5. Electrical Characteristics

10.3.6. Pinning
Pin1:BS
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel
MOSFET switch. Connect a 10nF or greater capacitor from SW to BS to power the high
side switch.

Pin2:IN
Power Input. IN supplies the power to the IC, as well as the step-down converter
switches. Drive IN with a 4.75V to 28V power source. Bypass IN to GND with a suitably
large capacitor to eliminate noise on the input to the IC.
Pin3:SW
Power Switching Output. SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load. Note that a capacitor is required
from SW to BS to power the high-side switch.
Pin4:GND
Ground.
Pin5:FB
Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a
resistive voltage divider from the output voltage. The feedback threshold is 1.222V.
Pin6:COMP
Compensation Node. COMP is used to compensate the regulation control loop. Connect
a series RC network from COMP to GND to compensate the regulation control loop. In
some cases, an additional capacitor from COMP to GND is required.
Pin7:EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn
on the regulator, drive EN low to turn it off. An Under Voltage Lockout (UVLO) function
can be implemented by the addition of a resistor divider from VIN to GND. For complete
low current shutdown its needs to be less than 0.7V. For automatic startup, leave EN
unconnected.
Pin8:SS
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS
to GND to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 10ms.
To disable the soft-start feature, leave SS unconnected.

10.4. FDC642P
10.4.1. General Description
This p-channel 2.5V specified MOSFET is produced using Fairchild’s advanced
PowerTrench process that has been especially tailored to minimize on state resistance
and yet maintain low gate charge for superior switching performance.

10.4.2 . Features

10.4.3. Absolute Maximum Ratings

10.4.4. Pinning
10.5. SIL9011
The Sil 9011 is a third generation HDMI receiver compatible with the HDMI 1.1 specification.
Backwards compatibility with DVI 1.0 allows HDMI systems to connect to existing DVI 1.0
hosts over a single cable.
The Sil 9011 is capable of receiving and outputting 2 to 8 channels of digital audio of up to
192kHz. An industry-standard I2S port allows direct connection to low-cost audio DACs. An
S/PDIF port supports up to 96kHz audio.
Silicon Image’s HDMI receivers use the latest generation of PanelLink TMDS core technology.
These PanelLink cores pass all HDMI compliance tests.

10.5.1 Features

x HDMI 1.1, HDCP 1.1 and DVI 1.0 compliant receiver


x Integrated PanelLink core supports:
DTV resolutions (480i/576i/480p/576p/720p/1080i)
PC resolutions (VGA, SVGA, XGA, SXGA, UXGA) up to 165MHz.
x Digital video interface supports video processors:
24-bit and 48-bit RGB/ YCbCr 4:4:4
16/20/24-bit YCbCr 4:2:2
8/10/12-bit YCbCr 4:2:2 (ITU BT.656)
x S/PDIF output supports bothIEC 60958 and IEC 67937 for PCM, Dolby Digital,
DTS digital or any S/PDIF type audio transmission (32-96kHz Fs)

x Four Programmable I2S outputs for connection to low-cost audio DACs.


x Sample rates up to 192kHz
x Auto audio error detection with programmable soft mute.
x Integrated HDCP decryption engine for receiving protected audio and video
content
x Pre-programmed HDCP keys provide highest level of key security, simplifies
manufacturing

10.6. 24LC02
10.6.1. General Description
24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device is
organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby and active currents of only 1μA
and 1mA, respectively. The 24XX02 also has a page write capability for up to 8 bytes of
data.

10.6.2 Features
x Single supply with operation down to 1.8V
x Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
x Organized as 1 block of 256 bytes (1 x 256 x 8)
x 2-wire serial interface bus, I2C™ compatible
x Schmitt Trigger inputs for noise suppression
x Output slope control to eliminate ground bounce
x 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
x Self-timed write cycle (including auto-erase)
x Page write buffer for up to 8 bytes
x 2ms typical write cycle time for page write
x Hardware write-protect for entire memory
x Can be operated as a serial ROM
x Factory programming (QTP) available
x ESD protection > 4,000V
x 1,000,000 erase/write cycles
x Data retention > 200 years
x 8-lead PDIP, SOIC, TSSOP and MSOP packages
x 5-lead SOT-23 package
x Pb-free finish available
x Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C

10.6.3 Pinning

10.7. μPA672T
10.7.1. General Description

N-channel Mos-Fet array for switching.The μPA672T is a super-mini-mold device


provided with two MOS FET elements. It achieves high-density mounting and saves
mounting costs.
10.7.2. Features

x Two MOS FET circuits in package the same size as SC-70


x Automatic mounting supported

10.7.3 Absolute Maximum Ratings

10.7.4 Pinning

10.8. M74HC4052
10.8.1. General Description

The M74HC4052 is a dual four-channel analog MULTIPLEXER/DEMULTIPLEXER


fabricated with silicon gate C2MOS technology and it is pin to pin compatible with the
equivalent metal gate CMOS4000B series. It contains 8 bidirectional and digitally
controlled analog switches.

10.8.2. Features

x LOW POWER DISSIPATION: ICC = 4mA(MAX.) at TA=25°C


x LOGIC LEVEL TRANSLATION TO ENABLE 5V LOGIC SIGNAL TO
COMMUNICATE
x WITH ±5V ANALOG SIGNAL
x LOW "ON" RESISTANCE:
70W TYP. (VCC - VEE = 4.5V)
50W TYP. (VCC - VEE = 9V)
x WIDE ANALOG INPUT VOLTAGE RANGE: ±6V
x FAST SWITCHING:
tpd = 15ns (TYP.) at TA = 25 °C
x LOW CROSSTALK BETWEEN SWITCHES
x HIGH ON/OFF OUTPUT VOLTAGE RATIO
x WIDE OPERATING SUPPLY VOLTAGE RANGE (VCC - VEE) = 2V TO 12V
x LOW SINE WAVE DISTORTION: 0.02% at VCC - VEE = 9V
x HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
x PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4052

10.8.3 Absolute Maximum Ratings

10.8.4 Pinning
VEE supply pin is provided for analog input signals. It has an inhibit (INH) input terminal
to disable all the switches when high. For operation as a digital
multiplexer/demultiplexer, VEE is connected to GND.
A and B control inputs select one channel out of four in each section. All inputs are
equipped with protection circuits against static discharge and transient excess voltage.
10.9. Max809

10.9.1. General Description

The MAX809 and MAX810 are costíeffective system supervisor circuits designed to
monitor VCC in digital systems and provide a reset signal to the host processor when
necessary. No external components are required.
The reset output is driven active within 10 _sec of VCC falling through the reset voltage
threshold. Reset is aintained active for a timeout period which is trimmed by the factory
after VCC rises above the reset threshold. The MAX810 has an activeíhigh RESET
output while the MAX809 has an activeílow RESET output. Both devices are available
in SOTí23 and SCí70 packages.

10.9.2. Features
x Precision VCC Monitor for 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
x Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps
x Four Guaranteed Minimum PoweríOn Reset Pulse Width Available (1 ms, 20
ms, 100 ms, and 140 ms)
x RESET Output Guaranteed to VCC = 1.0 V.
x Low Supply Current
x Compatible with Hot Plug Applications
x VCC Transient Immunity
x No External Components
x Wide Operating Temperature: í40°C to 105°C
x PbíFree Packages are Available

10.9.3 Absolute Maximum Ratings


10.9.4 Pinning
10.10. 24LC21
10.10.1. General Description
The 24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8
bits.This device can operate in two modes: Transmit Only mode and I2C bidirectional mode.
When powered, the device is in Transmit Only mode with EEPROM data clocked out from the
rising edge of the signal applied on VCLK.

10.10.2. Features
x 1 MILLION ERASE/WRITE CYCLES
x 40 YEARS DATA RETENTION
x 2.5V to 5.5V SINGLE SUPPLY VOLTAGE
x 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE
x TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE
x PAGE WRITE (up to 8 BYTES)
x BYTE, RANDOM and SEQUENTIAL READ MODES
x SELF TIMED PROGRAMMING CYCLE
x AUTOMATIC ADDRESS INCREMENTING
x ENHANCED ESD/LATCH UP PERFORMANCES

10.10.3 Absolute Maximum Ratings


10.10.4 Pinning

11.SERVICE MENU SETTINGS

In order to reach service menu,


x First Press “MENU”
x Then press the remote control code, which is “4725”

11.1. Video Setup

x Picture Mute <.....>


If “Yes” selected, “Picture mute” feature is active.
x Blue Screen <.....>
If “Yes” selected, “Blue Background” item is seen in “Feature”
menu.
x YC Delay <...........>
ƒ Tuner PAL <.....> Value between -8 to+7
ƒ Ext PAL <.....> Value between -8 to+7
ƒ SECAM <.....> Value between -8 to+7
ƒ NTSC <.....> Value between -8 to+7
x AGC (dB) <.....> Value between 0 to+8

11.2. AudioSetup
x Equaliser <.....>
If “Yes” selected, “Equaliser” item is seen in “Sound” menu.
x BBE
x SRS WOW
x Virtual Dolby Surround <.....>
If “Yes” selected, Virtual Dolby Surround feature is seen in “Sound”
menu with selected Virtual Dolby Text.
x Virtual Dolby Text The selected item is seen as Virtual Dolby Srround Text.
ƒ 3DS
ƒ Virtual Dolby
ƒ 3D Panorama
x AVL <.....>
If “Yes” selected, “AVL” item is seen in “Sound” menu.
x Carrier Mute <.....>
If “Yes” selected, “Carrier mute” feature is active.
x Audio Delay Offset
x Prescale
ƒ FM Presc. AVL On <.......> Value between 0 to +127
ƒ AM Presc. AVL On <.......> Value between 0 to +127
ƒ NICAM Presc. AVL On <.......> Value between 0 to +127
ƒ I2S Presc. AVL On <.......> Value between 0 to +127
ƒ SCART Presc. AVL On <.......> Value between 0 to +127
ƒ FM Presc. AVL Off <.......> Value between 0 to +127
ƒ AM Presc. AVL Off <.......> Value between 0 to +127
ƒ NICAM Presc. AVL Off <.......> Value between 0 to +127
ƒ I2S Presc. AVL Off <.......> Value between 0 to +127
ƒ SCART Presc. AVL Off <.......> Value between 0 to +127
x Dynamic Bass <.....>
If “Yes” selected, “Dynamic Bass” item is seen in “Sound” menu.
x Subwoofer <.....>
If “Yes” selected, “Subwoofer” item is seen in “Sound” menu.

11.3. Options 1
x VCTP Version <.......>
ƒ Basic+
ƒ Basic
x Double Digit <.....>
If “Yes” selected, “Double Digit” button is active for channel
selection.
x TEA6415C Available <.....>
If “Yes” selected, video switch IC is active on hardware.
x TEA642X Available<.....>
If “Yes” selected, audio switch IC is active on hardware.
x Power-Up Mode <.......>
ƒ StandBy If selected, TV opens in stand by mode.
ƒ L.State If selected, TV opens in Last State mode.
x TV Open Mode <.......>
ƒ Source
ƒ 1st TV
ƒ Last TV
x Select Languages <.......> “Yes” selected languages are seen as option under
the “Language” item in “Feature” menu
ƒ Language Set 1
o German <.......>
o French <.......>
o Spanish <.......>
o Italian <.......>
o Danish <.......>
o Finnish <.......>
o Swedish <.......>
ƒ Language Set 2
o Greek <.......>
o Norwegian <.......>
o Dutch <.......>
o Portuguse <.......>
o Polish <.......>
o Turkish <.......>
o Russian <.......>
o Czech <.......>
ƒ Language Set 3
o Hungarian <.......>
o Slovak <.......>
o Slovenian <.......>
o Romanian <.......>
o Bulgarian <.......>
o Croatian <.......>
o Serbian <.......>
o Hebrew <.......>

x First APS <.......>


If “Yes” selected, first time TV opens by asking APS.
x APS Volume <.......> value between 0 to+63
x Burn In Mode <.......>
If “Yes” selected, TV opens with Burn-In mode. This mode is
used in manufacturing.
x APS Test
x HDMI WP <.......>
If “Yes” selected, HDMI EDID ROM is write protected.

11.4. Options 2

x Autostore <.......>
If “Yes” selected, Channel is automatically stored.
x Led Type <.............................>
ƒ 1 Led 1 Colour
ƒ 1 Led 2 Colours
ƒ 2 Led 2 Colours
x PC PIP <.......>
x PC Stand By <.......>
11.5. Service Scan/Tuning Setup

x Search for L/L’ <.......>


x Pref. Search Standard <...........>
ƒ BG, DK, I
ƒ L/L’
ƒ M
x Station Ident <.......>
x ATS Delay Time (ms) <.......> Value between 20 to 250
x Color Killer Threshold <.......> Value between 0 to +255
x Tuner Options <.......>
ƒ Control Byte <.......> Value between 0 to +255
ƒ Low-Mid – Low Byte <.......> Value between 0 to +255
ƒ Low-Mid – High Byte <.......> Value between 0 to +255
ƒ Mid-High – Low Byte <.......> Value between 0 to +255
ƒ Mid-High – High Byte <.......> Value between 0 to +255
ƒ BSW1 <.......> Value between 0 to +255
ƒ BSW2 <.......> Value between 0 to +255
ƒ BSW3 <.......> Value between 0 to +255

11.6. External Source Settings


x DTV <.......>
x DVD <.......>
x Ext 2 S-Video <.......>
x Ext 3 <.......>
x Ext 3 S-Video <.......>
x FAV <.......>
x BAV <.......>
x S-Video <.......>
x HDMI 1 <.......>
x HDMI 2 <.......>
x YPbPr <.......>
x PC <.......>

11.7. Picture Mode


x Sources <.......>
ƒ Tuner
ƒ CVBS
ƒ RGB
ƒ SVHS
ƒ HDMI
ƒ YPbPr
ƒ PC
ƒ PIP
x Picture Mode <.......>
ƒ Dynamic
ƒ Natural
ƒ Cinema
x Colour Temp <.......>
 Cool
 Normal
 Warm
x Contrast <.......> Value between 0 to +63
x Brightness <.......> Value between 0 to +63
x Sharpness <.......> Value between 0 to +15
x Colour <.......> Value between 0 to +63
x Backlight <.......> Value between 0 to +255
x R <.......> Value between -63 to +63
x G <.......> Value between -63 to +63
x B <.......> Value between -63 to +63

11.8. Reset TV-Set


x Initialise NVM from ROM
Press green button to reset the NVM from ROM
12. TROUBLESHOOTING GUIDE
NO DEFECT APPEARANCE DEFECT IDENTIFICATION AND SOLUTIONS

When the TV is operated for the first time, IC403 E2Epron is plugged empty, after the programming process of the first values has finished, TV will switch on by itself.
1
STANDBY LED lights but the TV switches on
Standby LED does not ligh ever. Are there 3.3V on IC001's bottomright pin? If no, 3.3V are not drawing in, there can be an error in PW board; underneath VCTP, SMD material can be disintegrated.
Are there 1.8V in IC001 solder area? If no,1.8V are not drawing in; IC001 can be defective or underneath VCTP, SMD material can be disintegrated.
2 Are there 3.3V on IC406's top left pin? If no, IC406 can be defective.
Are there 1.8V on S719? If no, IC001 can be defective.
Are there 3.3V on S700? If no, there can be an error in PW board.

Are there 5V on pin PL409 5? If no, there can be a problem in PW board or SMD material can be disintegrated.
3 Standby LED does not light and/or IR receiver
does not work.
Picture is available but there is no sound. Are there 24V on the pin, which is indicated as number 1, of PL001 socket. If no, there can be a problem in PW board. L603 can be cold soldering.
4
Sound is available but there is no picture. PL406 can be cold soldering.
5 Is there display voltage in Q005's top points? (for LG 12V, for other displays 5V). If no; L007 for LG, L006 for other displays can be unplugged.
Q005 can be defective.

Neither picture nor sound is available. Are there 5V in 7th pin of tuner? If no, IC007 and surrounding equipment can be defective, L101 can be defective.
Are there 33V in 9th pin of tuner? If no, there can be a problem in PW board.
Are there 3.3V in L104 inductor? If no, there can be a problem in PW board.
6 Are there 12V in pin 8 of the PL003 socket? If no, there can be a problem in PW board.
Q410 and Q411 can be defective.
Are there 10V in the mid pin of IC004? If no, IC004 can be defective.
Are there 8V on L200? If no, there can be a problem in D004, D005, D006 or there could be cold soldering.

TV switches on but constantly switches to HDMI Are there 1.8V on S719? If no, IC001 can be defective.
input. While trying to tune a channel, always Are there 3.3V on S700? If no, PW board can be defective.
7
switches to C05. IC702 can be defective.
S705 and S706 can be cold soldering.

No sound from PC or YPbPr. IC905 or surronding equipment can be defective.


8
IC 905 supply voltage may not be drawing in 10V.

TFT backlight level cannot be controlled, it's level


9
is fixed. Q002, Q003, 1006 or surrounding eqipment can be defective or SMD material can be disintegrated.

TV switches on; however, after a short break, it When the TV is switched on; there should be displayed voltages as following: 5V on C074, 3.3V on PL004 pin 4, 8V on IC004 mid pin and Q005 top points. If one is missing, TV may shut
10 switches off again by itself.
down after a short while after it is switched on.
13. BLOCK DIAGRAMS
13.1. General Block Diagram
13.2. Power Management
13.3. DRX (IF Demodulator) Block Diagram
13.4. VCTP
14.4.1. General Block Diagram
13.4.2. MSP Block Diagram
13.4.3 Video Processor of VCT 6wxyP Block Diagram
14. CONNECTORS

14.1. POWER Connector

Pin Description
1 +12/24V
2 +12/24V
3 GND
4 GND

14.2. EMMA2LL JTAG Connector

Pin Description
1 GND
2 JTCLK
3 3.3V
4 JTDO
5 NC
6 JTMS
7 NC
8 JTRST
9 GND
10 JTDI

14.3. ANALOG AV Connector

Pin Description Pin Description


1 DVB_SCL 13 GND
2 DVB_SDA 14 GND
3 GND 15 DVB_R_AUDIO
4 GND 16 DVB_L_AUDIO
5 IRQ 17 GND
6 DVB_RX 18 DVB_IN_CVBS
7 DVB_TX 19 GND
8 GPIO4 20 DVB_IN_B / DVB_IN_C
9 GPIO3 21 GND
10 GPIO2 22 DVB_IN_G / DVB_IN_Y
11 GPIO1 23 GND
12 IF_AGC_DVB 24 DVB_IN_R
14.4. IF Connector
Pin Description
1 IF +
2 IF -
3 GND

14.5. PROGRAMMING Connector


Pin Description
1 TXD
2 GND
3 RXD

14.6. S/PDIF Connector

Pin Description
1 S/PDIF
2 GND

14.7. DIGITAL AV Connector

Pin Description Pin Description


1 I2S Word Select 11 GND
2 I2S Serial Clock 12 Digital Video Pixel Clock
3 I2S Serial Data 13 Digital Video Y/Cb/Cr DATA7
4 GND 14 Digital Video Y/Cb/Cr DATA6
5 GND 15 Digital Video Y/Cb/Cr DATA5
6 GND 16 Digital Video Y/Cb/Cr DATA4
7 Internal Vertical SYNC 17 Digital Video Y/Cb/Cr DATA3
8 Internal Horizontal SYNC 18 Digital Video Y/Cb/Cr DATA2
9 GND 19 Digital Video Y/Cb/Cr DATA1
10 GND 20 Digital Video Y/Cb/Cr DATA0
14.8. PCMCIA Connector

Pin Signal Description Pin Signal Description


1 GND Ground 35 GND Ground
2 D3 Data bit 3 36 CD1# Card Detect
3 D4 Data bit 4 37 MDO3 MPEG Data Out 3
4 D5 Data bit 5 38 MDO4 MPEG Data Out 4
5 D6 Data bit 6 39 MDO5 MPEG Data Out 5
6 D7 Data bit 7 40 MDO6 MPEG Data Out 6
7 CE1# Card Enable 41 MDO7 MPEG Data Out 7
8 A10 Address bit 10 42 CE2# Card Enable
9 OE# Output Enable 43 VS1# Voltage Sense 1
10 A11 Address bit 11 44 IORD# I/O Read
11 A9 Address bit 9 45 IOWR# I/O Write
12 A8 Address bit 8 46 MISTRT MPEG Data In Start
13 A13 Address bit 13 47 MDI0 MPEG Data In 0
14 A14 Address bit 14 48 MDI1 MPEG Data In 1
15 WE# Write Enable 49 MDI2 MPEG Data In 2
16 IREQ# Interrupt Request 50 MDI3 MPEG Data In 3
17 VCC Supply Voltage 51 VCC Supply Voltage
Programming and Programming and
18 VPP Peripheral Supply 52 VPP Peripheral Supply
19 MIVAL MPEG Data In Valid 53 MDI4 MPEG Data In 4
20 MCLKI MPEG Data Clock Input 54 MDI5 MPEG Data In 5
21 A12 Address bit 12 55 MDI6 MPEG Data In 6
22 A7 Address bit 7 56 MDI7 MPEG Data In 7
23 A6 Address bit 6 57 MCLKO MPEG Data Clock Output
24 A5 Address bit 5 58 RESET Card Reset
25 A4 Address bit 4 59 WAIT# Extend bus cycle
26 A3 Address bit 3 60 INPACK# Input Port Acknowledge
Register select & I/O
27 A2 Address bit 2 61 REG# Enable
28 A1 Address bit 1 62 MOVAL MPEG Data Out Valid
29 A0 Address bit 0 63 MOSTRT MPEG Data Out Start
30 D0 Data bit 0 64 MDO0 MPEG Data Out 0
31 D1 Data bit 1 65 MDO1 MPEG Data Out 1
32 D2 Data bit 2 66 MDO2 MPEG Data Out 2
33 IOIS16# I/O Port Is 16-bit 67 CD2# Card Detect
34 GND Ground 68 GND Ground
15. REPLACEMENT PARTS

THE UPDATED PARTS LIST

FOR THIS MODEL IS

AVAILABLE ON ESTA
16. ASSEMBLY DRAWING [For 37 inch models ONLY]

21
24

26

16

15

17

18
25

19
13

11

12

10

20

23 3
2
14 7
5

22 1

No. 0242 EXPLODED VIEW


[For 32 inch models ONLY]

28

29

19
18

25 17 21
20
26 24
27

17

13
23

11 15 14

31
12
22

31 17
7 10

6
33
16 3
34

2
8
5
30
4

33

No. 0242 EXPLODED VIEW


17. SCHEMATIC DIAGRAMS

L103
330R_100MHZ_3A 3V3_DRX
VCC_5V
10u L114

3V3_DRX
5V_DRX

R108

R110

R111

R112
6k2

6k2

6k2

6k2
L117

100n
C115
C116
50V 47u

16V
L112

C123

C124
R138

27p

27p
1k2
50V
10u SHEET 8
VCC_12V 12V_IF
10u
VGA_MUX_SW

100n

100u
C139

C140
25V
PL100
L116 DIGITAL IF CONNECTOR X100 YPBPR_MUX_SW
L104 3V3_DRX C134

L108

_ DR RX
10u
10u 1 2 3

12V_IF

12V_IF
R139 VCC_3V3 AUDIO_MUX_SW

5 3_ _D
N.C. S100 10u 20.25MHz

X
5V_TUNER 3k3 L102 5V_TUNER DRX_CLK

V 3

X
1n

R
PTC RES 50V SYNC_SW1

100n

3
C114

C117

D
47u
50V

10V
C101 10u

3
VCC_5V

V
16V
SHEET3

100n

100n

100n
10V C110

C111

C122

C125
47u
50V

16V
DRX POWER SUPPLY
1UF 16V

10n
TU100 50V N.C. SHEET3 VCTP PIN80

R130
R128
47k

47k

44

43

42

41

40

39

38

37

36

35

34

R116

R117

R118
R102

6k2

6k2

6k2
AGC 1 5k1 50V Q102 Q103 50V
SHORT 1n BF799 BF799 1n

XTALIN
SGND

PORT3
PORT5

PORT2
DVDD_ADC

PORT4
DVSS_ADC
VREF

ADR_SEL
XTALOUT
R103 R106 50V 50V

C130
C138 C137

33n
50V
TU 2 5k1 5k1 1n 1n
R136 R135

10n
25V
C100
N.C. 47R 47R

100n
C118
S101

10V
1UF 16V

1 AVSS_ADC TUNER_AGC 33

R127
C135 C136

47k
L105 L106

R132
470R

R131
470R

R129
S102

47k
AS 3 5V_DRX 2 AVDD_ADC PORT1 32 SYNC_SW2 SHEET 3

S111

S112
39p 10u
50V
3 ANATSTX PORT0 31 SW_ENABLE2
TECH2949PG40B

C102 R104
SCL 4 100R 4 ANATSTY DVSS_CAP 30

5V_DRX 5 AVDD_FE8 DVSS 29

100n
C129
C120

100n
16V

16V
IC100 L110 3V3_DRX

100n
C132
R125
150R
R126
150R
R105

16V
SDA 5 100R S117 16V 6 AVSS_FE8 DVDD 28
39p
16V
Z100
AN_IF 100n

7 AVSS_FE401
DRX3960A DVDD_CAP 27
C127
L111
3V3_DRX
50V 1u
R123 X6966M R119
C103 C119
NC 6 150R 8 IFINX SCL 26 33p 100R SCL_3V3_IC
1 IN1 OUT1 4 600R_100MHZ_200mA 25V R120
C107

C104
100n

16V

R100 5V_DRX 9 AVDD_FE40 SDA 25 100R SDA_3V3_IC

C141

100n
16V
L113
3k3 R140 L101 R124
2 IN2 OUT2 5 SHEET 3,5,6
VS 7 5V_TUNER 150R GND 10 IFINY RESETQ 24 25V
PTC RES BLM21A601S
5k1 IF_AGC S119 3 33p 3V3_DRX
11 AVSS_FE402 TEST_EN 23 C128

21 AVDD_DAC

22 AVSS_DAC
13 AVSS_SYN
S113

R121
12 AVDD_SYN

19 REF_SW

1k
14 SHIELD
NC/ADC 8 AN_IF

15 TEST0

16 TEST1

17 TEST2

18 CVBS
100n
C108

C109

R101
47u
16V

50V
4k7 5V_TUNER

20 SIF
R107
VST 9 1k
VCC_33V

100n
C131
S103 S118 R122

16V
Q101
IF_AGC BC848B 470R

100n
RESET_IC

C133

16V
IF2 10

S115

S116
L107

L109
SHEET3
L100

1u

C126
IF1 11
C121
100n

3V3_DRX
16V
100n

VCC_8V_VIDEO
16V

5V_DRX
QSS

R137
47R
5V_DRX C142

R109 10u
100R 16V
SHEET 3
Q100
BC848B R114
75R
TUNER_CVBS_IN

IC101

R113
1k
R115
SCL_DVB 1 2Y1 VCC 16 5V_TUNER 75R
TUNER_CVBS_SW

SHEET 8
SCL_5V_IC
2 2Y0 S105 2Z 15
SHEET3

S120
AGC_DVB 3 3Y1 1Z 14
S121
IF_AGC

4 3Z 1Y1 13 SDA_DVB
S109
S104

TUNER/DRX
5 3Y0 1Y0 12 SDA_5V_IC
S110

S106 R134

DEMODULATOR
6 E S1 11 5V_TUNER 4k7 5V_TUNER
100n
C113

S107
10V

7 VEE S2 10
S108

Q104 R133
BC848B 1k

TV/DVB_SWITCH S114
8 GND S3 9 SYNC_SW2
100n
C112

10V

74HCT4053
AGC_TV

17MB22-2 MAIN BOARD CIRCUIT - SHEET 1


R332 R333
VCC_8V 47R VCC_8V 47R

VCC_5V_VIDEO
C208

C256
47u

47u
50V

50V

R293
1k
R221
1k
C266
C229 SC3_AUDIO_R_OUT
SC2_AUDIO_R_OUT

R259

R269

C250
470R

100n
22u

18k
TO SHT7

10V
22u R290 50V
50V 100R BC858B C267
R206
BC858B Q208

TO SHT3
100R SC1_AUDIO_R_OUT

IR_DMP/DVD
Q201

DMP_DVD_G
DMP_DVD_R

DMP_DVD_B
BC858B

DMP_DVD_AUDIO_R_IN
22u

R295
Q207

VCC_5V
1k
C218

TO SHT7
SHT3 R232 L211 VCTP_AOUT1R 50V

DMP/DVD_SWITCH

TO SHT3
330R LINE_R_OUT
Q205 SHT3 C268

C223

C227
22u BC848B

50V

50V
1n

1n
VCTP_AOUT2R 50V VCTP_AOUT1L SC3_AUDIO_L_OUT

R218
R273 R278

1k
150R 75R 22u
SC2_CVBS_OUT R291 50V
VCTP_AOUT2L 100R BC858B
R326

VCC_5V_VIDEO
C231 Q209 C269 75R

150R
R270
SC1_

L235

10u
SC2_AUDIO_L_OUT BC858B AUDIO_ R327
L_OUT
22u 22u 75R
Q202
R207 50V 50V R328
100R BC858B 75R
Q200
C219

11

13

15

17

19
R233 L212

9
330R LINE_L_OUT DMP CON
PL210

C228
C224
22u

10

12

20
16

18
14
50V

50V

8
4
1n

1n

TO SHT3
50V VOUT2
TO SHT3

R267
470R

100n
R260

C249
18k

10V
VOUT1

R325
SW_UPDATE_EN

75R

C281
47u
50V
BC858B
Q206

3V3_STBY

UART_RX
VCC_3V3

UART_TX
Q204 R324

DMP_DVD_CVBS_IN

DMP_DVD_AUDIO_L_IN
BC848B

SC3_CVBS_IN
75R

SC3_PIN8

IRQ
TO SHT7
R271 R274

TO SHT7
TO SHT3
150R 75R

SC3_AUDIO_R_IN

SC3_AUDIO_L_IN
SC1_CVBS_OUT
BC858B

150R
SC3_AUDIO_R_OUT

R268
SC3_AUDIO_L_OUT
Q203

S210

S209
R275
75R

SC3_SVHS_C

TV_LINK_3V3
TO SHT7
Q213

R237
SC3_CVBS_OUT

47R

SC2_PIN8
BSN20

SC2_FB

TO SHT3
BSN20

R321
3k3
C213 C220 TO SHT7 Q214 Q212

R253
47R
BSN20

IDTV_AUDIO_R_IN
IDTV_CVBS_IN

IDTV_AUDIO_L_IN
IDTV_G
1n 1n

IDTV_R

IDTV_B

TO SHT1
SC2_R/C ILE PARALEL

AGC_DVB
50V 50V C225 Q211

R238D209
330R

R228
330R

R243
C5V6
R219

5k6

IF_AGC
100n R331 BSN20

3V3_STBY
16V TO SHT1
75R

D217
S200

R323
C5V6
C201 C204

75R
15k
C214 C221

SDA_DVB
1n 1n

SCL_DVB
R254

R301

R313
R330

5V_STBY
47R

47R

47R
50V 50V 75R
C233 R303
L201 27p 3k3

D214

R322
R200

C5V6
1n 1n R329

75R
330R 50V 50V 50V 75R C5V6

L206

L210
C203

50V

D228

R251
C235
1n

75R
27p

D224
100n
C265

R298

R314
C5V6
Q210

47R
5k6
L208

16V

SC3_SVHS_C
50V

R302

R309
C205

15k

4k7
PL207
1n BSN20
50V

12
41 39 37 35 33 31 29 27 25 23

21

11
13
23

15
22

20

19

10
17
18

16

14
24
R201 R304 R315

1
3
5
9

2
8

4
330R 100R 75R
L202
42 40 38 36 34 32 30 28 26 24 22 L224
IDTV_FFC_CON[ANALOG]
PL203

C5V6
PL208
C206
C200

50V

L209
50V

1n
1n

D218 L221
R256 R261 2 4 6 8 10 12 14 16 18 20
330R 20 18 16 14 12 10 8 6 4 2 47R 47R SC1_CVBS_IN

C254

50V
L203

1n
R203 1 3 5 7 9 11 13 15 17 19 21
TO SHT3 SHT7 [TO VIDEO SW]
R204 21 19 17 15 13 11 9 7 5 3 1
330R L222

R285
330R
C236
L204 27p
C207

R252
75R
50V
1n

50V
27p
C222

C257
R234

R241

R246

R250

R297

C270

R305

C273

R310

C274
L205

L207

L223

L226
C230 C232 C234

27p

27p

27p
75R

75R

75R

75R

75R
15k

50V

50V

50V

50V
75R

1n
C202 27p 27p 27p
R229

R230

C277

R318

C280
C226

27p

27p
75R

47R

75R
50V

50V

50V
50V 50V 100n 50V 50V 50V

50V
1n 1n 16V
1n

1n
50V

R248

R286
330R
47R
D208

R239

R244
C216
C5V6

C215
47R

47R

50V
C259
50V

C263
1n

1n
D207

D210

D213
R217
330R

R222
330R

R292
330R

330R

R306

R311
C5V6

C5V6

C5V6

R294

R319
47R

47R

47R
R231

R299
47R

47R
C253
50V
C210 1n

D215

D216
C5V6

C5V6
R235

R236

R240

R245

R249
47R

47R

47R

47R
5k6

D229

D230
C260

C5V6

C5V6
1n C217

50V

50V
1n

1n
C264
50V

D225

D226

D227
C5V6

C5V6

C5V6
C255
50V
1n

R320
47R
R300

R307

R312
47R

47R

47R
BAV_CVBS_IN
SC1_AUDIO_R_OUT

SC1_AUDIO_L_OUT

SC1_G
SC1_PIN8
SC1_B

SC1_FB

SC1_CVBS_OUT
SC1_R
SC1_AUDIO_L_IN
SC1_AUDIO_R_IN

FAV_CVBS SVHS_Y PARALEL

SC2_AUDIO_L_OUT
SC2_AUDIO_R_IN

SC2_AUDIO_L_IN
R255

SC2_AUDIO_R_OUT

SC2_CVBS_IN
SC2_G
SC2_B

SC2_R/C

SC2_CVBS_OUT
C239

75R
27p C5V6
50V
PL204
R265 D220 R276 TO SHT3
BAV99 TO SHT3 1 47R 47R FAV_CVBS_IN
TO SHT3 D205 C237
S201

27p
VCC_5V 2 50V
BAV99
D203 3 TO SHT3 VCTP
BAV99 4
4

D200 FAV SVHS/C SC2 RED ILE PARALEL

TO SHT7
R202

R205

R208

C211

27p
75R

75R

75R

50V

5
NC3

NC2

NC1
VSS

L215

SCART, VGA,
ST24LC21

PL200 6 330R FAV_AUDIO_R_IN


IC200

R213 R223 R272


1 47R 47R PC_R 7
TO SHT7
R214 R224 L216 R264

DMP, IDTV, FAV


2 47R 47R PC_G 8 330R FAV_AUDIO_L_IN

YPBPR_AUDIO_R_IN

YPBPR_AUDIO_L_IN
TO SHT7
C241

C243

C246

C248
R215 R225
50V

50V

50V

50V
1n

1n

1n

1n
FAV VIDEO TO SHT7
3 47R 47R PC_B

PC_AUDIO_R_IN
PC_AUDIO_L_IN
VCLK

VCC_5V
SDA

VCC
SCL

YPBPR_PR
YPBPR_PB
4

YPBPR_Y
CONNECTORS
C209

27p
50V

TO SHT7 SHT4
RGB SW
5
5

BAV_R_IN

BAV99

HP_OUT_R
C212

HP_OUT_L
D221
27p
50V

6 VCC_5V BAV_L_IN
D219
BAV99

7 PL205
D212

R279

R282

R287
D206

47R

47R

47R
L218

BAV99
8 1 LINE_R_OUT

D222
DDC_5V
BAV99

9 2
D201

S208
L217
10 3 LINE_L_OUT C261 C271
PC_VSYNC

DDC_5V

S207

BAV_R_IN
BAV99
VCC_5V

D223
4

BAV_L_IN
11 1n 1n
C275 C278
DDC_SDA
50V 50V
R280

R283

R288

330R
R296
R209 R226

330R
R308
47R

47R

47R
FAV AUDIO
12 47R 47R L219 R262 1n 1n
330R SUBW 50V 50V

R316
330R

R317
330R
R210
13 1k PC_HSYNC C262 C272
C242

C247
50V

50V
1n

1n

TO SHT3 TO SHT3
R211 R281 R284 R289
SYNC SW
14 1k PC_VSYNC 75R 75R 75R 1n 1n
C276 C279
50V 50V

S205

L228
R212 R227

L227
C251 C252 C258
15 47R 47R

S206
1n 1n
DDC_SCL
50V 50V

L231
L229

L230
DSUB_VGA_CONN

L225
27p 27p 27p
FAV_HP 50V 50V 50V
C238

C244
R216
R220
3k3

10k

50V

50V
1n

1n

PL206
VCC_3V3 L213 2 3 1 2 3 1 2 3 1
PC VIDEO GND TO CHASIS GND
BAV99 1 HP_OUT_R
TO SHT4

D204
S202

S203

S213 A A S204 A 2 3 1 1 2 3 2 3 1
2
D211
C5V6

JK200 WHITE_FAV YELLOW_FAV HEADPHONE JACK PC


S211 L214 JK201 JK202 A A
1P_RED_FAV
BAV99 TO SHT3 VCTP
3 HP_OUT_L
1P_RED_FAV WHITE_FAV
D202 BAV_CVBS_IN
C240

C245

S212 R242 R247 JK205 JK206


50V

50V

JACK-AK16
4
1n

1n

HP_DETECT 47R 47R JK204


YPBPR AUDIO
YPBPR/LINE_IN[R/L] CVBS JACK

17MB22-2 MAIN BOARD CIRCUIT - SHEET2


_IN
VGA_DVDDMP_R_IN

VGA_DVDDMP_B_IN

VSUP_3V3_CO M
SHEET 1,2,8

VGA_DVDDMP_G
TUNER_CVBS_IN
L415

BACKLIGHT_DIM
PIP_CVBS_OUT

PR_IDTV_R_IN

PB_IDTV_B_IN
SC1_CVBS_IN

Y_IDTV_G_IN
2 5V_COM VCC_5V

VCTP_VIN2

VCTP_VIN5
KEYBOARD R543 R487

PC STANDBY MODE

PARITY
SC2_R/C
47R 47R 1

100n

C492

C493
SC1_FB

SC2_FB

10V

1kV
PDP_GO/BL_ON_OFF

1n
VOUT1

VOUT2

SC1_G

SC2_G
SC1_R

SC1_B

SC2_B

D406
100n
C487

C5V6
16V
SYNC DETECTION PL403

VSUP_3V3_COM E2EPROM
R467
PL402 1k5
IDTV DIGITAL INTERFACE [FFC TYPE]
IC405

SDA_3V3
SCL_3V3
VSUP_3V3_COM
KEYBOARD CONN.

R545
10k
5V_STBY

11
13
20

19

15

12

10
18

17

16

14
IRQ_PDP

1
3
9

2
8

VSUP_3V3_COM
KEYBOARD IDTV_HSYNC 1 Y0 VCC 16 5V_COM

S414

S415
SHEET POWER

VSUP_3V3_COM
AC_INFO

VSUP_3V3_COM
S409

S410

C501

27p

SDA_3V3_IC
1 R1 8

R1 8

SCL_3V3_IC
R430

R550

R552

R547
R441
R431
SHEET 2

47R

75R

75R

75R
R2

R3

R4

R2

R3

R4

50V
HDMI_HSYNC 2 Y2 X2 15 HDMI_VSYNC

R442

R443

R549
R544

75R

75R

75R

SC1_PIN8

SC2_PIN8
10k

S461
2

VSUP_3V3_COM
VSUP_3V3_COM

S462
R402
10k

IDTV_ODD
KEYBOARD

D401

C5V6
R432
PIP_CLK 10k HSYNC 3 COM_Y_OUT_IN X1 14 PC_VSYNC

IDTV_HSYNC

D403
C496
R554

C5V6
27p

R551
PC_HSYNC 10k KEYBOARD

S456
C500

R456

R461

R464
R433

27p
75R

10k

10k

10k
DMP/DVD_SWITCH

50V
R420 PIP_DATA7 10k
Q404

50V
10k

S444
R548
BC848B R434 R505

75R
PIP_DATA6 10k 1k 4 Y3 COM_X_OUT_IN 13 VSYNC

R445

50V

50V
75R
PL407

5
C497

C498

C499
R553 R435

27p

27p

27p
50V
Q419

HSYNC
PC_VSYNC 10k PIP_DATA5 10k

D400
C495

C5V6
BC848B

10u
50V

VSUP_3V3_VO

D402
R436

C5V6
PIP_DATA4 10k PC_HSYNC 5 Y1 X0 12 IDTV_VSYNC

R471
1k8
S412

S413
220n

220n

220n

220n
C476

C478

C480

C483
R437
10k PIP_DATA3 10k

16V
R426

16V

16V

16V
HDMI_DETECT

VSUP_3V3_DAC
VSUP_3V3_COM

220n

220n
S427

C468

C470
R438 R472 R528

3V3_STBY
PIP_DATA2 10k 1k 6 INH X3 11 1k

220n
C485
R403 R495

VSUP_3V3_FE16V
Q401

16V

16V
VCC_3V3 10k R439 4k7 VSUP_3V3_COM
BC848B R423

VSUP_1V8_FE

VSUP_1V8_FE
PIP_DATA1 10k