EE - PS EC-1 Micro-1 De-2 CS-2 - Solutions - 2451

Detailed Solutions
ESE-2018 Electrical Engineering

Mains Test Series Test No : 3
Section A : Power Systems
Q.1 (a) Solution:

Schematic arrangement of a Hydroelectric plant
Reservoir Surge Tank
DAM
Valve house
II I II I I II III III
Pressure tunnel
I I I I I I I I I I I I I I I I I I I I I I II
I III I Penstock
I
I I II
I II
III
III
I II Power station
III
III
III
I II
III Tail
I II
II I
II II Race
II I I
I II I
I I III
I I II
II I I
I
The chief requirements for hydroelectric power plant is the availability of water in huge
quantity at sufficient head and this requirement can be met by constructing a dam across
a river or a lake.
An artificial storage reservoir is formed by constructing a dam across a river (or) a lake
and a pressure tunnel is taken off from the reservoir to the valve house at the start of the
penstock. The valve house contains mains sluice valves for controlling water flow to the
power station and automatic isolating valves for cutting off water supply in case the
Test No : 3 ELECTRICAL ENGINEERING | 11
penstock bursts. A surge tank is also provided just before the valve house for better
regulation of water pressure in the system.
From the reservoir the water is carried to valve house through pressure tunnel and from
valve house to the water turbine through pipes of large diameter made of steel or
reinforcement concrete, called the penstock.
The water turbine converts hydraulic energy into mechanical energy and the alternator
coupled to the water turbine converts mechanical energy into electrical energy.
Water after doing useful work is discharged to the tail race.
Q.1 (b) Solution:

Quantity of water available for utilization per second
Catchment area in km 2 × 106 × average annual rainfall in m × yield factor

=
365 × 24 × 60 × 60
200 × 106 × 1.25 × 0.75

= = 5.95 m3
8760 × 3600
Available head, H = 30 m
Overall efficiency of power plant,
η = Penstock efficiency × turbine efficiency × generator efficiency
= 0.95 × 0.85 × 0.9 = 0.72675
Average power, P = WQH × 9.81 × η × 10–6 MW
= 1000 × 5.95 × 30 × 9.81 × 0.72675 × 10–6
= 1.272 MW
P 1.272
Capacity of power station = =
Load factor 0.4
= 3.18 MW
Q.1 (c) Solution:

A power of 100 MW flows from Bus 1 to Bus 2 and causes a loss of 10 kW.
So, 10 × 10–3 = B11 × 1002
⇒ B11 = 1 × 10–6 MW–1
Also, since there is no load at Bus 1,
B12 and B22 are zero
−6 2
PL = 1 × 10 PG 1
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12 | ESE 2018 : MAINS TEST SERIES
∂PL
and = 0
∂PG 2
1 1
Penalty factor for plant 1, L1 = =
∂PL 1 − 2 × 10 −6 PG 1
1−
∂PG 1
1
Penalty factor for plant 2, L2 = =1
1−0
The generation at each plant is required to be determined for λ = Rs 25/MWh
dF1
⋅ L1 = dF2 ⋅ L2 = λ
dPG 1 dPG 2
0.02 PG 1 + 16
So, = 25
1 − 2 × 10 −6 PG 1
(or) 0.02 PG1 + 16 = 25 – 50 × 10–6 PG1
(or) PG1 = 448.87 MW
dF2
and ⋅ L2 = 25
dPG 2
(or) (0.04 PG2 + 20) × 1 = 25
25 − 20
PG2 = = 125 MW
0.04
Power loss, B11 PG21 = 1 × 10–6 × (448.87)2 MW
= 0.2015 MW
Power received by load = 448.87 + 125 – 0.2015
= 573.67 MW
Q.1 (d) Solution:
1.9
Conductor radius = cm = 0.95 cm
2
Spacing of conductor, d = 3.81 m = 381 cm
Dielectric strength of air, g0 = 21.1 kV/cm (rms) (assumed)
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3.92 b 3.92 × 73.7

Air density factor, δ = = = 0.91
273 + t 273 + 44
Irregularity factor, m0 = 0.85
Critical disruptive voltage to neutral,
⎛ d⎞
V d0 = g0 δm0 r ln ⎜⎝ ⎟⎠
r
⎛ 381 ⎞
= 21.1 × 0.91 × .85 × 0.95ln ⎜
⎝ 0.95 ⎟⎠
= 92.94 kV (rms)
Line-to-line disruptive critical voltage
= 3 × 92.94 = 160.97 kV
Visual critical voltage to neutral:
⎡ 0.3 ⎤
V v0 = g0 δ mvr ⎢1 + ln( d / r )
⎣ δr ⎥⎦
⎛ 0.3 ⎞ ⎛ 381 ⎞
= 21.1 × 0.91 × 0.8 × 0.95 ⎜ 1 + ⎟ ln ⎜ ⎟
⎝ 0.91 × 0.95 ⎠ ⎝ 0.95 ⎠
= 115.7 kV
Line-to-line visual critical voltage= 3 × 115.7
= 200.39 kV
Q.1 (e) Solution:

Choose 1000 MW as base power
The parameter B on 5000 MW base,
B 2 = 5B1 = 5 × 0.01 = 0.05 p.u. MW/Hz
The parameter R on 5000 MW base,
1 2
R2 = R1 = = 0.4 Hz/p.u. MW
5 5
Now the static deviations in frequency
ΔPD1 + ΔPD2
Δf0 = − [ΔPD2 = 0]
⎛ 1⎞ ⎛ 1 ⎞
⎜⎝ B1 + R ⎟⎠ + ⎜⎝ B2 + R ⎟⎠
1 2
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−0.05
=
⎛ 1⎞ ⎛ 1 ⎞
⎜⎝ 0.01 + ⎟⎠ + ⎜⎝ 0.05 + ⎟
2 0.4 ⎠
= –0.0163 Hz
Q.2 (a) Solution:
1.2
Conductor radius, r = cm = 0.6 cm (or) 6 mm
2
Geometric mean radius, r′ = 0.7788 × 6 mm = 4.6728 mm
In equilateral arrangement of line conductors as shown in figure below:
m A
3.5
3.5
B C
3.5 m
Spacing of conductors, d = 3.5 m = 3500 mm

Inductance per phase, L = 2 × 10–7 ln (d/r′) H/m
⎛ 3500 ⎞
= 2 × 10 −7 ln ⎜ ⎟ = 1.324 × 10–6 H/m
⎝ 4.6728 ⎠
In the arrangement of conductors horizontally spaced.
A B C
d d
Flux linkages of conductor a due to Ia, Ib and Ic are:
−7 ⎡ ⎛ 1⎞ ⎛ 1 ⎞ ⎛ 1 ⎞⎤
λa = 2 × 10 ⎢ I a ln ⎜⎝ R′ ⎟⎠ + I b ln ⎜ D ⎟ + Ic ln ⎜ D ⎟ ⎥
⎣ ⎝ ab ⎠ ⎝ ac ⎠ ⎦
−7 ⎡ ⎛ 1 ⎞ ⎛ 1⎞ ⎛ 1 ⎞⎤
λb = 2 × 10 ⎢ I a ln ⎜ D ⎟ + I b ln ⎜⎝ R′ ⎟⎠ + Ic ln ⎜ D ⎟ ⎥
⎣ ⎝ ab ⎠ ⎝ bc ⎠ ⎦
⎡ ⎛ 1 ⎞ ⎛ 1 ⎞ ⎛ 1 ⎞⎤
λc = 2 × 10 −7 ⎢ I a ln + I ln + I ln
c ⎜⎝ ⎟⎥
⎜⎝ D ⎟⎠ b ⎜
⎝ Dbc ⎟⎠ R′ ⎠ ⎦
⎣ ac
Taking Ia as reference, Ib = α2 Ia,
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Ic = αIa
Where, α = –0.5 + j 0.866
−7 ⎡ ⎛ 1⎞ ⎛ 1 ⎞ ⎛ 1 ⎞⎤
λa = 2 × 10 × I a ⎢ln ⎜ ⎟ + ( −0.5 − j 0.866)ln ⎜ + ( − 0.5 + j 0.866)ln ⎥
⎣ ⎝ R′ ⎠ ⎝ Dab ⎠⎟ ⎝⎜ Dac ⎠⎟ ⎦
λa
La = I , similarly we calculate Lb and Lc
a
Transmission line as transposed, the average inductance

La + Lb + Lc
L =
3
1⎡ −7 ⎛ ⎛ 1⎞ ⎛ 1 ⎞ 3 ⎞⎤
= 3 ⎢ 2 × 10 ⎜ 3ln ⎜ ⎟ − ln ⎜⎝ D D D ⎟⎠ − j ln 1⎟⎥
⎝ ⎝ R′ ⎠ 2 ⎠ ⎦⎥
⎣⎢ ab bc ac
−7
⎛ 3 Dab Dbc Dac ⎞
L = 2 × 10 ln ⎜ ⎟ Henry/meter
⎝ R′ ⎠
Dab = d
Dbc = d
Dac = 2d
−7 ⎛ 3 d ⋅ d ⋅ 2d ⎞
LH = 2 × 10 ln ⎜
R′ ⎟ ...(i)
⎝ ⎠
for equilateral arrangement,
−7 ⎛ D ⎞
LΔ = 2 × 10 ln ⎜⎝ ⎟⎠ ...(ii)
R′
Where, D = 3.5 m
Equating both (i) and (ii),
d3 2 3.5
=
R′ R′
3.5
d = 3 = 2.78 m
2
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Q.2 (b) Solution:
The powers at the various points in the fundamental (two-bus) system are defined as in
figure below.
G1 G2
SG1 = PG1 + jQG1 SG2 = PG2 + jQG2
⎪V1⎪∠δ1 ⎪V2⎪∠0°
SS = PS + jQS SR = PR + jQR
SD1 = PD1 + jQD1 SD2 = PD2 + jQD2
Cable impedance = j 0.05 p.u.

Since cable resistance is zero, there is no real power loss in the cable.
Hence PG1 + PG2 = PD1 + PD2 = 40 p.u.
For equalization of static loads,
PG1 = PG2 = 20 p.u.
Equalization means that, PS = PR = 5 MW
The voltage of bus 2 is taken as reference, i.e. V2∠0° and voltage of bus 1 is V1∠δ1.
Further, for voltage profile to be flat,
⎪V1⎪ = ⎪V2⎪ = 1
V1 V2
Now, PS = PR = sin δ 1
X
1×1
5 = sin δ 1
0.05
or, δ 1 = 14.5°
∴ V 1 = 1∠14.5°
2
V1 V V
and, QS = − 1 2 cos δ 1
X X
1 1
= − × 0.968 = 0.64 p.u.
0.05 0.05
and QR = –QS = –0.64 p.u.
Reactive power loss in the cable is:
QL = QS – QR = 2QS = 1.28 p.u.
Total load on station 1 = (15 + j5) + (5 + j0.64)
= 20 + j5.64
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⎛ 5.64 ⎞ ⎞
Power factor at station 1 = cos ⎜ tan −1 ⎛⎜ = 0.9624 lagging
⎝ ⎝ 20 ⎟⎠ ⎟⎠
Total load on station 2 = (25 + j15) – (5 – j0.64)
= 20 + j15.64
⎛ −1 ⎛ 15.64 ⎞ ⎞
Power factor at station 2 = cos ⎜ tan ⎜ = 0.788 lagging
⎝ ⎝ 20 ⎟⎠ ⎟⎠
G1 SG1 = 20 + j 5.64 G2 SG2 = 20 + j 15.64
1 V1 = 1.0∠14.5° 2 V2 = 1.0∠ 0°
SS = 5 + j0.64 SR = 5 – j 0.64
SD1 = 15 + j 5 SD2 = 25 + j 15
The station load, load demands and line flows are as shown in figure above.
To maintain a flat voltage profile, the generators are required to supply reactive powers
QG1 = 5.64 p.u.
and QG2 = 15.64 p.u.
Q.2 (c) (i) Solution:

A smart grid is an electricity network that can intelligently integrate the actions of all
users connected to it - generators, consumers and those that do both - in order to efficiently
deliver sustainable, economic and secure electricity supplies.
A smart grid employs innovative products and services together with intelligent
monitoring, control, communication and self healing technologies to:
1. Facilitate in a better way the connection and operation of generators of all sizes and
technologies.
2. Allow consumers to play a part in optimizing the operation of the system.
3. Provide consumers with greater information and choice of supply.
4. Significantly reduce the environmental impact of the whole electricity supply system.
5. Deliver enhanced levels of reliability and security of supply.
Q.2 (c) (ii) Solution:

Fault current, If = 5000 A
CT ratio = 500 : 1
If 5000
Relay current, IR = = = 10 A
(CT )ratio 500
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Pick up value of relay = Current setting × Rated secondary current of CT
125
= × 1 = 1.25 A
100
Plug setting multiplier of the relay,
Fault current in relay coil 10

PSM = =
Pick-up value of relay 1.25 = 8
Time corresponding to the PSM of 8 from given data is 3.5 seconds

So, actual operating time = 3.5 × time setting multiplier
= 3.5 × 0.3 = 1.05 seconds
Q.3 (a) (i) Solution:

Let the base MVA be 10 and base kV be 13.8
MVA × 1000 10000
Base current, IB = = = 418.37 A
3 × 13.8 3 × 13.8
Now, Zn = j 0.7 Ω
10
Zn (p.u.) = j 0.7 × = j 0.03675 p.u.
(13.8)2
Z 0 = Zg0 + 3Zn
= j 0.05 + 3 × j0.03675
= j 0.16 p.u.
Ea
Also, Ia1 =
Z Z
Z1 + 2 0
Z2 + Z0
13.2
Ea = p.u. = 0.9565 p.u.
13.8
0.9565
Ia1 = j 0.15 × j 0.16 = –j4.206 p.u.
j 0.15 +
j 0.15 + j 0.16
Now, Va0 = Va2 = Va1 = Ea – Ia1Z1

= 0.9565 – (–j4.206) × j 0.15
= 0.3256 p.u.
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−Va2 −0.3256
Ia2 = =
Z2 j0.15 = j2.171 p.u.
−Va0 −0.3256
Ia0 = =
Z0 j 0.16 = j2.035 p.u.
Initial symmetrical rms current in line b,
Ib = a2Ia1 + aIa2 + Ia0
= –j 4.206 (–0.5 – j0.866) + j 2.171 (–0.5 + j 0.866) + j 2.035
= –5.52 + j 3.0525
= 6.3∠151.06 p.u.
= 2635.73∠151.06° A
Initial symmetrical rms current in ground wire
= 3 Ia0 = 3 × j 2.035 × 418.37
= 2554.15∠90° A
Q.3 (a) (ii) Solution:

Spacing of conductor, d = 5 m = 500 cm
2.0
Radius of each conductor, r = = 1.0 cm
2
2 π ∈0 2 π × 8.854 × 10 −12
Capacitance of the line = F/m =
⎛ d⎞ ⎛ 500 ⎞
ln ⎜ ⎟ ln ⎜
⎝ r⎠ ⎝ 1 ⎟⎠
= 8.951 × 10–12 F/m
Capacitance of a 100 km long line = 8.951 × 10–12 × 100 × 103
= 0.8951 μF
Q.3 (b) Solution:

The value of Pmax before fault = 2.0 p.u.
Power delivered, PE = 1.0 p.u.
Since PE = Pmax sin δ
⎛ P ⎞ ⎛ 1⎞
Load angle, δ0 = sin −1 ⎜ E ⎟ = sin −1 ⎜ ⎟ = 30 electrical degrees
⎝ Pmax ⎠ ⎝ 2⎠
GH 7.5 × 1 1
M = = = p.u.
180 f 180 × 50 1200
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Average accelerating power during the first interval of T = 0 to T = 0.1 second,
1+0
PAG = = 0.5 p.u.
2
PAG 0.5
Average acceleration, α1 = = 2
M 1 = 600 electrical degrees/s
1200
Change in angular velocity = α1Δt = 600 × 0.05 = 30 electrical degrees/second
dδ 1
So, = 0 + α1Δt = 0 + 30 = 30 electrical degrees/second
dt
The corresponding change in rotor angle during first interval of 0.05 s,
Δδ 1 = 30 × 0.05 = 1.5 electrical degrees
So rotor angle at the end of period of 0.05 seconds,
δ 1 = δ0 + Δδ1 = 30 + 1.5 = 31.5 electrical degrees
Since,Pmax after the fault is cleared= 1.5 p.u.
So, PE = Pmax sin δ1 = 1.5 sin 31.5 = 0.78375 p.u.
Since Pmax during fault is zero,
0 + 0.78375
Average accelerating power = = 0.391875 p.u.
2
0.391875
Average acceleration, α2 = = 470.25 electrical degrees/sec2
1
1200
Change in angular velocity during second interval of 0.05 second
α2 Δt = 470.25 × 0.05
= 23.5125 electrical degrees/second
dδ 2 dδ 1
So, = + α 2 Δt = 30° + 23.5125°
dt dt
= 53.5125 electrical degrees/second
So, change in rotor angle during second interval of 0.05 second
Δδ 2 = 53.5125 × 0.05
= 2.675 electrical degrees
Rotor angle at the end of second interval of 0.05 second
δ 2 = δ1 + Δδ2 = 31.5 + 2.675
= 34.175 electrical degrees
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Maximum demand, MD = 1500 W = 1.5 kW
Connected load = 10 × 60 + 2 × 1000
= 2600 W
Daily energy consumption = Number of lamps used × Wattage of each lamp × working
hours per day + Number of heaters × Wattage of each heater × working hours per day
= 8 × 60 × 5 + 2 × 1000 × 3
= 8400 Wh = 8.4 kWh
Daily energy consumption in Wh
Average load =
24
8400
= = 350 W
24
Monthly energy consumption = Daily energy consumption × 30
= 8.4 × 30 = 252 kWh
Monthly energy consumption
Monthly load factor =
MD × 24 × 30
252
= = 0.233 (or) 23.33%
1.5 × 24 × 30
1. Costly terminal equipment. The converters required at both ends of the line have
proved to be reliable but they are much more expensive than the conventional ac
equipments.
2. The converters have very little overload capacity and absorb considerable reactive
power - the reactive power can be as high as 25% of true power.
3. Converters produces lot of harmonics both on dc and ac sides which may cause
interference with the audio frequency communication lines.
4. HVDC converters need complex cooling systems.
5. Maintenance of insulators in HVDC transmission line is more.
6. Circuit breaking in multiterminal dc systems is difficult and costlier.
7. Voltage transformation is not easier in case of dc and hence it has to be accomplished
on the ac side of the system. DC system cannot be employed for distribution, sub-
transmission and transmission.
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Q.4 (a) (i) Solution:
Current loading, i = 1 A/m
Resistance per meter run, r = 2 × 10–5 Ω
length of the distributor, l = 500 meters
Distance of the point, at which voltage drop is to be determined from feeding point,
x = 400 meters
Voltage drop at distance of 400 meters from the feeding point
⎛ x2 ⎞
= ir ⎜ lx − ⎟
⎝ 2⎠
⎡ 400 × 400 ⎤
= 1 × 2 × 10 −5 ⎢ 500 × 400 − ⎥⎦ = 2.4 V
⎣ 2
Q.4 (a) (ii) Solution:

6.6 × 1000
Voltage per phase, VP = = 3810.5 V
3
Voltage induced in the unprotected portion (10%) of the winding
10
= 3810.5 × = 381.05 V
100
Impedance offered by 10% of winding (unprotected winding) to earth fault current
10
= 5 + j2 × = (5 + j0.2)Ω
100
The earth fault current caused by voltage induced in the unprotected winding
381.05
= = 76.15∠–2.29 A
5 + j 0.2
MVA rating × 106

Full load current =
3 KVrating × 1000
10 × 10 6
= = 874.77 A
3 × 6.6 × 1000
Earth fault current
Relay setting = × 100
Full load current
76.15
= × 100 = 8.7%
874.77
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Q.4 (b) (i) Solution:

Incident voltage, E = 100 kV Z1
IT1
Surge impedance of overhead line, Zc= 500 Ω ZL
Surge impedance of branched lines, Z1 = 40 Ω I IR IT2
and Z 2 = 60 Ω Z2
2E ⎛ Z × Z2 ⎞
Transmitted voltage, ET = ×⎜ 1
ZC + 1
Z × Z2 ⎝ Z1 + Z2 ⎟⎠
( Z1 + Z2 )
2 × 100 ⎛ 40 × 60 ⎞
= ×⎜ ⎟
⎛ 40 × 60 ⎞ ⎝ 40 + 60 ⎠
500 + ⎜
⎝ 40 + 60 ⎟⎠
= 9.16 kV
ET 9.16 × 1000
Transmitted current, IT1 = = = 229 A
Z1 40
ET 9.16 × 1000
IT2 = Z = 60 = 152.67 A
2
Reflected voltage, ER = ET – E = 9.16 – 100
= –90.84 kV
E 100 × 1000
Incident current, I = Z = 500 = 200 A
C
Reflected current, IR = I T1 + I T2 – I
= 229 + 152.67 – 200
= 181.67 A
Q.4 (b) (ii) Solution:

(a) Voltage across the circuit breaker contacts after the interruption of 10 A current.
L 5
v = i = 10 = 158.11 kV
C 0.02 × 10 −6
(b) Value of resistance to be used across the contacts to suppress restriking voltage.
L 5
R = 0.5 = 0.5 = 7.9 kΩ
C 0.02 × 10 −6
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Motor Input 75
Input to motor = = = 83.33 kW
η 0.9
Initial power factor, cos φ = 0.75 (lag)

Power factor after improvement,
cos φ2 = 0.95 (lag)
kVAR rating of capacitor bank = P(tan φ1 – tan φ2)
= 83.33 [tan (cos–1 0.75) – tan(cos–1 0.95)]
= 46.10 kVAR
Since reactive kVA output of the capacitors when connected in delta is given by
3 × (2πf)CVL2 × 10–9, where C is the capacitance in μF, Vi is the line voltage in volts and f
is supply frequency in Hz,
46.10 × 10 3
∴ C = = 305.71 μF
6 π × 50 × 400 2
The bank of capacitors used to improve the pf is connected in delta so phase voltage is
400 V and therefore each phase of bank will have 4 capacitors connected in series.
So, capacitance of each unit = 4 × 305.71
= 1222.84 μF

Number of units = 4
Voltage across the second unit, V2 = 13.2 kV
Voltage across the third unit, V3 = 18.2 kV
We know, V 3 = (1 + 3K + K2)V1
V 2 = (1 + K)V1
Shunt capacitance between links
Where, K = Mutual capacitance between links
18.2 1 + 3K + K 2
(or) =
13.2 1+K
18.2 + 18.2 K = 13.2 + 39.6 K + 13.2 K2
⇒ 13.2 K2 + 21.4 K – 5 = 0
On solving above equation,
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K = 0.207
V2 13.2
Voltage across top unit, V1 = = = 10.936 kV
1 + K 1 + 0.207
Voltage across the bottom most unit,
V 4 = (1 + 6K + 5K2 + K3)V1
= [1 + (6 × 0.207) + 5 × (0.207)2 + (0.207)3] 10.936
V 4 = 26.96 kV
Voltage between conductor and earth,
V = V1 + V2 + V3 + V4
= 10.936 + 13.2 + 18.2 + 26.96
= 69.296 kV
Line voltage = 3 × 69.296 = 120.02 kV
Section B : Electrical Circuits-1 + Microprocessor-1 + Digital Electronics-2 + Control Systems-2

Q.5 (a) Solution:
The given circuit can be equivalently drawn as follows:
a 4Ω
I
6Ω Ra 3Ω
Rb Rc
12 Ω
20 V –+ 8Ω 2Ω
4Ω
Rd Re
Rf
10 Ω 8Ω
Req b
From the properties of star-delta transformation,

6×3 6×3 6 6 × 12 24 3 × 12 12
Ra = Ω= Ω = Ω ; Rb = Ω= Ω ; Rc = Ω= Ω
6 + 3 + 12 21 7 21 7 21 7
4 × 10 4 × 10 20 4×8 16 8 × 10 40
Rd = Ω= Ω= Ω ; Re = Ω= Ω ; Rf = Ω= Ω
4 + 10 + 8 22 11 22 11 22 11
By replacing the delta network portions with their star equivalents, the given network
can be equivalently drawn as follows:
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I a 4Ω
6 6
Ω Ω
7 a 4Ω 7
24 12
Ω Ω
7 7
1020 398
Ω Ω
20 V + 77 77
20 V –+ 8Ω 2Ω –
40
Ω
20 16 11
Ω Ω
11 11
b
40 Req
Ω
11
b
Req
6 40 ⎛ 1020 398 ⎞
Req = 4 + + + Ω = 12.21 Ω
7 11 ⎝⎜ 77 77 ⎠⎟
20 V 20
I = = A = 1.64 A
Req 12.21
Q.5 (b) Solution:

Considering the currents entering into network A and network B as IA and IB respectively
as shown in the figure below.
IA Z IB
+ +
Network Network
VA VB
A B
– –
VA − VB 120∠30° − 120∠0°
IB = = A (rms)
Z j1
= 62.117∠15° A (rms)
VB − VA 120∠0° − 120∠30°
IA = = A (rms)
Z j1
= 62.117∠–165° A (rms)
• The average power absorbed by the network A will be,
PA = VA I A cos( θVA − θI A )
= 120 × 62.117 cos(30° + 165°)
= – 7200 W
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The sign of PA is negative. It indicates that, in the actual circuit, the network A is
delivering the power.
• The average power absorbed by the network B will be,
PB = VB I B cos( θVB − θI B )
= 120 × 62.117 cos(0° – 15°)
= 7200 W
The sign of PB is positive. It indicates that, in the actual circuit, the network B is
absorbing the power.
• The average power delivered by network A = 7200 W
The average power absorbed by network B = 7200 W
The average power loss in the cables = 0 W
• So, the network A is acting as a source and network B is acting as a load.
Q.5 (c) Solution

• Excitations of the flip flops are,
T 2 = Q1
T 1 = Q2 + Q1
T 0 = Q1
• The sequence table of the given counter circuit can be given by,
Present state Excitations Next state

+ + +
Q2 Q1 Q0 T2 T1 T0 Q2 Q1 Q0
0 0 0 1 0 0 1 0 0
0 0 1 1 0 0 1 0 1
0 1 0 0 1 1 0 0 1
0 1 1 0 1 1 0 0 0
1 0 0 1 1 0 0 1 0
1 0 1 1 1 0 0 1 1
1 1 0 0 1 1 1 0 1
1 1 1 0 1 1 1 0 0
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• The complete sequence diagram of the given counter circuit is,
000
111
011 100
(Q2 Q1 Q0)
010
101
110
001
• The modulus of the counter = 6

• Number of unused states = 2
• There is no lock out problem for the given counter.
Q.5 (d) Solution:

8086 has a 16-bit flag register which is divided into two parts, viz. (a) condition code or
status flags and (b) machine controls flags. The condition code flag register is the lower
byte of the 16-bit flag register along with overflow flag. This part is identical to the 8085
flag register, with an additional overflow flag, which is not present in 8085. This part of
the flag register of 8086 reflects the results of the operations performed by ALU. The
control flag register is the higher byte of the flag register of 8086. It contains three flags,
viz. direction flag (D), interrupt flag (I) and trap flag (T).
The complete bit configuration of 8086 flag register is shown below.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X O D I T S Z X AC X P X CY
O - Overflow flag
D - Direction flag
I - Interrupt flag
T - Trap flag
S - Sign flag
Z - Zero flag
AC - Auxiliary carry flag
P - Parity flag
CY - Carry flag
X - Not used
The description of each flag bit is as follows:
Sign Flag (S) : This flag is set when the result of any computation is negative. For signed
computations, the sign flag equals to the MSB of the result.
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Zero Flag (Z) : This flag is set if the result of the computation or comparison performed
by the previous instruction/instructions is zero.
Parity Flag (P) : This flag is set to 1 if the lower byte of the result contains even number of 1s.
Carry Flag (CY) : This flag is set when there is a carry out of MSB in case of addition or a
borrow in case of subtraction.
Trap Flag (T) : If this flag is set, the processor enters the single step execution mode. In other
words, a trap interrupt is generated after execution of each instruction. The processor executes
the current instruction and the control is transferred to the Trap interrupt service routine.
Interrut Flag (I) : If this flag is set, the maskable interrupts are recognised by the CPU,
otherwise they are ignored.
Direction Flag (D) : This is used by string manipulation instructions. If this flag bit is ‘0’,
the string is processed beginning from the lowest address to the highest address, i.e.
autoincrementing mode. Otherwise, the string is processed from the highest address
towards the lowest address, i.e. autodecrementing mode.
Auxiliary Carry Flag (AC) : This is set if there is a carry from the lowest nibble, i.e. bit
three, during addition or borrow for the lowest nibble, i.e. bit three, during subtraction.
Overflow Flag (O) : This flag is set if an overflow occurs, i.e. if the result of a signed
operation is large enough to be accomodated in a destination register. For example, in
case of the addition of two signed numbers, if the result overflows into the sign bit, i.e.
the result is of more than 7-bits in size in case of 8-bit signed operations and more than
15-bits in size in case of 16-bit signed operations, then the overflow flag will be set.
Q.5 (e) Solution:
• For the purpose of frequency domain analysis, the transfer function of the compensator
can be modified by replacing “s” with “jω” as follows:
1 + jω
Gc ( jω) =
3 + jω
• The phase of this compensator can be given by,
−1 −1 ⎛ ω ⎞
φ = tan ( ω) − tan ⎜ ⎟
⎝3⎠
ω
• For any positive value of ω, ω is greater than
. So, the value of φ is always positive.
3
Hence, the given compensator is a lead compensator.
To determine the maximum phase lead provided by the compensator:
• Let us assume that, φ will be maximum at ω = ωm.
dφ
So, = 0
d ω ω = ωm
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1 3
2
− 2 = 0
1 + ωm 9 + ωm
2 2 = 0
9 + ωm − 3 − 3 ωm
2 = 6
2 ωm
ωm = 3 rad/sec
φ m = maximum phase lead provided
= φ ω=ω m
⎛ 1 ⎞
= tan −1 ( 3) − tan −1 ⎜ ⎟ = 60° – 30° = 30°
⎝ 3⎠
• So, the given compensator is a phase lead compensator and it provides a maximum
phase lead of 30°.
Q.5 (f) Solution:

• The transfer function of a system can be given by,
Y ( s)
T(s) = = C [ sI − A]−1 B
U (s)
⎡ −2 −1⎤
Where, A = ⎢3 0⎥
⎣ ⎦
⎡1⎤
B = ⎢0 ⎥
⎣ ⎦
C = [0 1]
⎡s + 2 1⎤
[sI – A] = ⎢ ⎥
⎣ −3 s ⎦
1 ⎡ s −1 ⎤
[sI – A] –1 = ⎢ ⎥
s 2 + 2s + 3 ⎣ 3 s + 2 ⎦
1 ⎡ s −1 ⎤ ⎡1⎤ 1 ⎡s⎤
T(s) = 2
[0 1] ⎢ ⎥ ⎢0 ⎥ = 2 [0 1] ⎢ ⎥
s + 2s + 3 ⎣3 s + 2 ⎦ ⎣ ⎦ s + 2s + 3 ⎣3⎦
3
= 2
s + 2s + 3
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Q.6 (a) Solution:

(i) By considering the given circuit in frequency domain, we get,
1
jωC1
+
+
Vm∠0° 1
R jωL V0
(peak) – jωC2
–
Figure-1
By applying the source transformation to the portion of network in the dotted box, we get,
+
jVmωC1∠0°
1 1
(peak) R jωL V0
jωC1 jωC2
–
Figure-2
The above circuit can be further simplified as,

+
jVmωC1∠0°
1
(peak) R jωL V0
jω(C1 + C2)
–
Figure-3
For simplifying the calculations, let us take C1 + C2 = Ce.
+
jVmωC1∠0°
1
(peak) R jωL V0
jωCe
–
Figure-4
The above simplified circuit can’t be used for direct calculation of the resonant frequency,
as the amplitude of the source is a function of frequency.
By applying source transformation to the network portion given in the dotted box, we
get,
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1
I1 jωCe
a
+
+
VmC1
∠0° R jωL V0
Ce –
(peak)
–
Zab b
Figure-5
Now the amplitude of the source, in the above simplified circuit, is independent of the
frequency.
1 1
So, Zab = +
jωC e 1 + 1
R j ωL
1 j
+
−j R ωL
= +
ωC e ⎛ 1 ⎞ 2 ⎛ 1 ⎞ 2
⎜ ⎟ +⎜ ⎟
⎝ R ⎠ ⎝ ωL ⎠
...(i)
When ω = ω0 (resonant frequency in rad/sec), the imaginary part of Zab will be zero.
1
ω0L 1
So, 2 2 = ω C
⎛1⎞ ⎛ 1 ⎞ 0 e
⎜ ⎟ +⎜ ⎟
⎝ R ⎠ ⎝ ω0L ⎠
2 2
⎛1⎞ ⎛ 1 ⎞ Ce
⎜ ⎟ +⎜ ⎟ = ...(ii)
⎝ R ⎠ ⎝ ω0L ⎠ L
2
1 ⎛ Ce ⎞ ⎛ 1 ⎞
= ⎜ ⎟−⎜ ⎟
ω02 L2 ⎝ L ⎠ ⎝R⎠
1
ω0 =
2
⎛C ⎞ L
L2 ⎜ e ⎟ − 2
⎝ L ⎠ R
1 1 1
ω0 = =
L LC e L
LC e 1 − 2 1− 2
R Ce R Ce
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1 1
In Hz, f0 =
2 π LC e L
1− 2
R Ce
(ii) Given that, Vm = 10 V, R = 1 kΩ, C1 = 2 nF, C2 = 8 nF and L = 5 mH

So, Ce = C1 + C2 = 10 nF
At resonance, ω = ω0 and f = f0.
⎛1⎞
⎜ ⎟
Zab ω = ω ⎝R⎠
= 2
0 2
⎛1⎞ ⎛ 1 ⎞
⎜ ⎟ +⎜ ⎟
⎝ R ⎠ ⎝ ω0L ⎠
From equation (ii), we get,
⎛1⎞
⎜ ⎟ 5 × 10−3
Zab ω = ω ⎝R⎠ = L = Ω = 500 Ω
=
0 ⎛ C e ⎞ RC e 10 3 × 10 × 10 −9
⎜ ⎟
⎝ L ⎠
The effective value of the current I1 shown in figure-5, at resonance, will be,
⎛C ⎞
Vm ⎜ 1 ⎟
I1 ω = ω ⎝ C e ⎠ ∠ 0°
0
=
2 Zab ω = ω
0
⎛ 2 ⎞
10 ⎜ ⎟
= ⎝ 10 ⎠ ∠0° = 2 2 ∠0° mA (rms)
2 (500)
The effective value of voltage V0 can be given as,
V 0 = I 1 ( R jω0 L )
1 1
ω0 = rad/sec
5 × 10 −3 × 10 × 10−9 5 × 10 −3
1−
106 × 10 × 10 −9
2
= × 106 rad/sec = 2 × 105 rad/sec
50
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ω0L = 2 × 105 × 5 × 10–3 Ω = 1000 Ω
(R⎥⎥ ω0L) = (1000⎥⎥ j1000) Ω
(1000) ( j 1000) j 1000
= 1000 + j 1000 Ω = 1 + j 1 Ω
= 500 2 ∠45° Ω
2 2
So, V0 = × 500 2 ∠45° V (rms)
1000
V 0 = 2∠45° V (rms)
Q.6 (b) Solution
• Let us assume that the binary logic values (1 or 0) are represented as b7, b6, b5, .... b1, b0.
⎧VR ; for bi = 1
So, di = ⎨
⎩ 0 ; for bi = 0
di = VRbi
• Considering the given circuit by modifying di = VRbi as shown below.
R
VR b7
2R RF
VR b6
4R Iin
VR b5 –
V0
8R +
VR b4
R
VR b3
2R Rx
VR b2
4R
VR b1
8R
VR b0
V 0 = –IinRF
• For a digital-to-analog converter,
V 0 ∝ [decimal equivalent of input binary code]
V 0 = –IinRF
So, Iin ∝ [decimal equivalent of input binary code]
• Let, Iin = I0 when (b7 ... b0) = (0000 0001)
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and Iin = I4 when (b7 ... b0) = (0001 0000)

(0000 0001)2 = (1)10 and (00010000)2 = (16)10
So, I4 = 16I0 ...(i)
To calculate I4 :
• When (b7 ... b0) = (0001 0000), the given circuit can be equivalently drawn as,
R 0A
0V
2R RF
0A
0V
4R 0A VR/8R I4 0 A
0V
–
0V V0
8R VR/8R +
VR 0V 0A
R 0A
0V
2R Rx
0A 0V
4R 0A
0V
8R 0A
0V
VR
So, I4 = ...(ii)
8R
To calculate I0 :
• When (b7 ... b0) = (0000 0001), the given circuit can be equivalently drawn as,
R 0A
0V
2R RF
0A
0V
4R 0A 0V 0A I0
–
0V V0
8R 0A +
0V I0
2R Rx
4R
8R
VR
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• The above circuit can be further reduced as,
RF
8R Rx
A
VR –
I0 0V
+ V0
RP
By applying KCL at node ‘A’, we get,
VR − VA V V −0 4R
= A+ A ; RP = R 2 R 4 R =
8R RP Rx 7
⎛ 1 7 1 ⎞ V
VA ⎜ + + ⎟ = R
⎝ 8R 4 R Rx ⎠ 8R
VA(Rx + 14Rx + 8R) = VRRx

VR Rx
VA =
8 R + 15 Rx
VA − 0 VA VR
and, I0 = = = ...(iii)
Rx Rx 8R + 15Rx
• From equations (i), (ii) and (iii),
VR ⎡ VR ⎤
= 16 ⎢ ⎥
8R ⎣ 8R + 15Rx ⎦
15Rx + 8R = 128R
15Rx = 120R
R x = 8R
• So, when Rx = 8R, the given circuit can be used as an 8-bit (binary) digital-to-analog
converter.
(ii) When the given circuit is used as a 2-decade BCD digital-to-analog converter,
I4 = 10I0 ...(iv)
• From equations (ii), (iii) and (iv), we get,
VR ⎡ VR ⎤
= 10 ⎢ ⎥
8R ⎣ 8R + 15Rx ⎦
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15 Rx + 8 R = 80R
15Rx = 72R
72
Rx = R = 4.8R
15
• So, when Rx = 4.8R, the given circuit can be used as a 2-decade BCD digital-to-analog
converter.
Q.6 (c) Solution:

• The open-loop transfer function of a standard second order system with unity negative
feedback can be given by,
ωn2
G(s) =
s(s + 2ζωn )
• By comparing the open-loop transfer function of the given system with that of
standard second order system, we get,
ωn2 = 16 ⇒ ωn = 4 rad/sec
1.6
2ζω n = 1.6 ⇒ ζ = = 0.20
2×4
• The block diagram representation of the given system with derivative rate feedback
control can be drawn as shown below.
16
R(s ) + + C(s)
– – s(s + 1.6)
Kt s
• The open-loop transfer function of the system with controller can be given by,
16 16
G′(s) = =
s( s + 1.6) + 16Kt s s[s + (16Kt + 1.6)]
• By comparing G′(s) with that of standard second order system, we get,
ωn2 = 16 ⇒ ωn = 4
2ζ′ωn = 16Kt + 1.6 ⇒ ζ′ = 2Kt + 0.20
• The desired value of damping ratio is 0.80. So, the desired value of Kt is,
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2Kt + 0.20 = 0.80
K t = 0.30
For the system without controller:
ωn = 4 rad/sec
ζ = 0.20
ωd = ωn 1 − ζ 2 ≈ 3.92 rad/sec
π
• Peak time, tp = = 0.80 sec
ωd
• Maximum peak overshoot,
ζπ
−
1−ζ 2
%Mp = e × 100
0.2 π
−
1 − 0.04
= e × 100 = 52.6%
• Steady state error for unit ramp input,
1 1 1
ess = = = = 0.10
lim sG(s) 16/1.6 10
s→0
For system with controller:

ωn = 4 rad/sec
ζ = 0.80
ωd = ωn 1 − ζ 2 = 2.40 rad/sec
π π
• Peak time, tp = = = 1.31 sec
ωd 2.40
• Maximum peak overshoot,
− ζπ
0.8 π
1−ζ 2 −
%Mp = e × 100 = e 0.6 × 100 = 1.52%
• Steady state error for unit ramp input,

1 1
ess = = = 0.40
lim G′(s ) 16/6.4
s→0
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The parameters of system with and without controller can be compared by placing
in a tabular form as shown below:
Parameter Without controller With controller

Damping ratio (ζ) 0.20 0.80
Peak time (t p ) 0.80 sec 1.31 sec
%Maximum peak overshoot (%Mp ) 52.6% 1.52%
Steady state error for unit ramp input (ess ) 0.10 0.40
• So, the derivative rate feedback controller improved the value of ζ, decreased the
values of tp , Mp but it increased the value of ess.
Q.7 (a) Solution:

• The two port network-A is made up of only resistors. Hence, reciprocity theorem
will be satisfied by the network-A.
1 2 1 2
Network Network
V1 –+ I1 I2 +
– V2
"A" "A"
1′ 2′ 1′ 2′
Figure-a Figure-b
For the given two port network-A, according to reciprocity theorem,

I1 I2
V1 = V2
To determine the Norton’s equivalent across RL of the circuit given in figure-2 of the
question:
• To determine the Norton’s equivalent current IN,
1 2
IN Network +
"A " – 40 V
1′ 2′
From the circuits given in figure-1, figure-a and figure-b, according to reciprocity theorem,
we can conclude that,
IN I 2 I1 3A
= = =
40 V V2 V1 10 V
40 V
So, IN = × 3 A = 12 A
10 V
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• To determine the Norton’s equivalent resistance RN,
Ix 1 2
Network
Vx –+
1′ "A "
Vx 2′
RN =
Ix
From the circuit given in figure-1 of the question and according to the homogeneity
property of the linear networks, we can conclude that,
Vx 10 V
Ix = 4A
Vx
So, RN = = 2.5 Ω
Ix
To determine the maximum power that can be delivered to RL using the Norton’s
equivalent circuit:
The Norton’s equivalent circuit across RL of the circuit given in figure-2 of the question
can be given as
IL 1
RL RN = 2.5 Ω IN = 12 A
1′
According to maximum power transfer theorem, maximum power will be delivered to

RL when RL = RN = 2.5 Ω.
So, when RL = RN = 2.5 Ω,
I N 12
IL = = A=6A
2 2
Maximum power that can be delivered to RL can be given as,
2
PL (max) = I L RL = (6)2 (2.5) W = 90 W
RL = RN
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Q.7 (b) Solution:

2Ω i1 i2 2Ω
(i)
+ iL + +
vi 2H 1F vC v0
1 2
– – –
The basic voltage current relations of inductor and capacitor are,

di
For induction, vL = L L
dt
dvc
For capacitor, iC = C
dt
State variables are associated with energy storing elements and they always present
with their derivatives in the basic equations of the element.
So, the state variables associated with an inductor is current flowing through it and
that of for a capacitor is the voltage across it.
For the given circuit iL and vC are the state variables.
Let us take, x1 = iL
x2 = vC
dx
x =
dt
x1, x2 are state variables.
By writing kVL in loop-1, we get,
diL
vi = 2 i1 + 2
dt
But, i1 = iL + i2
dvc dvc
and i2 = C =
dt dt
di
So, vi = 2( iL + i2 ) + 2 L
dt
dvc di
= 2 iL + 2 +2 L
dt dt
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diL dvc v
+ = −iL + i
dt dt 2
v
x 1 + x 2 = − x1 + i ...(i)
2
By writing kVL in loop-2, we get,
diL
2 i2 + vc − 2 = 0
dt
di dv
2 L − 2 c = vc
dt dt
x
x 1 − x 2 = 2 ...(ii)
2
By adding equations (i) and (ii), we get,
x2 vi
2x 1 = − x1 + +
2 2
x1 x2 vi
x 1 = − + + ...(iii)
2 4 4
By subtracting equation (ii) from equation (i), we get,
vi x2
2x 2 = − x1 + −
2 2
x1 x2 vi
x 2 = − − + ...(iv)
2 4 4
The output variable v0 can be expressed as,
v0 = vc = x2 ...(v)
From equations (iii), (iv) and (v), we can write the state model of the given network
as,
⎡ 1 1 ⎤ ⎡1⎤
x
⎡ i⎤ ⎢− 2 4 ⎥ ⎡ x 1 ⎤ ⎢4⎥
⎢ x ⎥ = ⎢ 1 ⎥ ⎢ ⎥ + ⎢ ⎥ vi ⇒ state equation
1 x 1
⎣ 2⎦ ⎢− − ⎥⎣ 2⎦ ⎢ ⎥
⎢⎣ 2 ⎥
4⎦ ⎢
⎣ 4 ⎥⎦
⎡ x1 ⎤
v0 = [0 1] ⎢ x ⎥ ⇒ output equation
⎣ 2⎦
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⎡ 1 1 ⎤
⎢− 2 4 ⎥
State (or) system matrix, [A] = ⎢ ⎥
⎢− 1 −
1⎥
⎣⎢ 2 4 ⎦⎥
⎡1⎤
⎢4⎥
Input matrix, [B] = ⎢ 1 ⎥
⎢ ⎥
⎣⎢ 4 ⎦⎥
Output matrix, [C] = [0 1]
(ii) Kalman’s test for controllability:

QC = [B AB A2B ..... An–1B]
n = no. of state variables = 2
So, for the given network,
[QC ] = [B AB]
⎡ 1 1 ⎤⎡1⎤ ⎡ 1 1 ⎤ ⎡ 1 ⎤
⎢− 2 − + −
4 ⎥ ⎢ 4 ⎥ = ⎢ 8 16 ⎥ = ⎢ 16 ⎥
[AB] = ⎢ 1 ⎥⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢− 1⎥⎢1⎥ ⎢ 1 1 ⎥ ⎢ 3 ⎥
− − − −
⎣⎢ 2 4 ⎦⎥ ⎣⎢ 4 ⎦⎥ ⎣⎢ 8 16 ⎦⎥ ⎣⎢ 16 ⎦⎥
1 1
−
4 16 3 1 2 1
⎥ QC ⎥ = = − + =− =− ≠0
1 3 64 64 64 32
−
4 16
1 1
−
2 4 = 1+1 = 1 ≠0
⎪A⎪ =
1 1 8 8 4
− −
2 4
So, rank of [QC] = rank of [A] = n = 2
Hence, the given network is said to be controllable.
Kalman’s test for observability:
T T T T 2 T T n −1 T
[QO] = ⎡⎣C A C ( A ) C ... ( A ) C ⎤⎦
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For the given network,
T T T
[QO] = ⎡⎣C A C ⎤⎦
⎡ 1 1⎤ ⎡ 1⎤
⎢− 2 − ⎥ 0 ⎢− ⎥
2 ⎡ ⎤ 2
⎡ ATCT ⎤ = ⎢ 1 ⎥⎢ ⎥ = ⎢ ⎥
1 1 1
⎣ ⎦ ⎢ − ⎥ ⎣ ⎦ ⎢− ⎥
⎢⎣ 4 4⎦⎥ ⎢
⎣ 4 ⎥⎦
1
0 −
⎥QO⎥ = 2 = 1≠0
1 2
1 −
4
So, rank of [QO] = rank of [A] = n = 2
Hence, the given network is said to be observable.
Q.7 (c) Solution

Main Program:
LXI D, 2050H ; Point index to readings
LXI H, 2090H ; Point index to maximum limits
MVI C, 05H ; Set up C as a counter with a count value of 5
NEXT: CALL SBTRAC ; Call the subroutine to perform 16-bit subtraction to
determine the difference between a reading and its
maximum limit
INX D ; Increment the contents of DE pair to point the location of
next reading
INX H ; Increment the contents of HL pair to point the location of
maximum limit corresponding to the next reading
DCR C ; Decrement the count value after completion of the process
corresponding to each reading
JNZ NEXT ; Jump to the location labeled as "NEXT" till the count value
of the counter becomes zero, to start the process
corresponding to the next reading
HLT ; Halt the execution
Subroutine:
SBTRAC: MOV A, M ; Load the accumulator with lower byte of the maximum
limit corresponding to the reading
XCHG ; Exchange the contents of HL and DE pairs
SUB M ; Subtract lower byte of the reading from the lower byte of
the corresponding maximum limit
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MOV M, A ; Store the lower byte of the difference in the location

corresponding to the lower byte of the reading
MOV A, M ; Load the accumulator with higher byte of the maximum
limit corresponding to the reading
SBB M ; Subtract (with borrow) higher byte of the reading from the
higher byte of the corresponding maximum limit
CC INDCTR ; Call the indicator subroutine if the value of reading is higher
than the corresponding maximum limit
MOV M, A ; Store the higher byte of the difference in the location
corresponding to the higher byte of the reading
RET ; Return to the Main Program
Q.8 (a) Solution
• The total delay produced by the given subroutine program can be calculated by
determining the total number of T-states required to execute the program.
• The total number of T-states required to execute the program can be determined by
analyzing the given program as shown in the following table:
Instruction Number of times executed Number of T-states

for one time execution
Delay : MVI B, 02H 1 7
LOOP2 : MVI C, FFH (1 × 2) = 2 7
LOOP1 : DCR C (255 × 2) = 510 4
(254 × 2) = 508 ⇒ true 10 ⇒ true

JNZ LOOP1 7 ⇒ false
(1 × 2) = 2 ⇒ false
DCR B 2 4
JNZ LOOP2 1 ⇒ true 10 ⇒ true

1 ⇒ false 7 ⇒ false
RET 1 10
• The total delay produced by the program in terms of T-states can be given by,
Delay = (1 × 7T) + (2 × 7T) + (510 × 4T) + (508 × 10T) + (2 × 7T) + (2 × 4T) + (10T + 7T)
+ (10T)
= 7T + 14T + 2040T + 5080T + 14T + 8T + 17T + 10T
= 7190T
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• The time delay corresponds to one T-state is,
1 1
T = = μs = 0.5 μs ∵ given that, fclk = 2 MHz
f clk 2
• So, the total delay produced by the program is,
7190
Delay = μs = 3595 μs 3.6 ms
2
Q.8 (b) (i) Solution:
(a)
J2 K2 J1 K1 J0 K0
Q2 Q1 Q0 Q1 Q0 Q2 Q2 Q1 Q1 Q′2 Q1′ Q0′
0 0 1 1 1 0 1 0 1 1 0 0
1 0 0 1 0 1 0 0 1 1 1 0
1 1 0 0 0 1 0 1 0 1 1 1
1 1 1 0 1 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 0 0 0 1
Thus there are five states
001
100
011
110
111
(b)
J2 K2 J1 K1 J0 K0
Q2 Q1 Q0 Q1 Q0 Q2 Q2 Q1 Q1 Q2′ Q1′ Q0′
1 0 1 1 1 1 0 0 1 0 1 0
0 1 0 0 0 0 1 1 0 0 0 1
0 0 1 1 1 0 1 0 1 1 0 0
1 0 0 1 0 1 0 0 1 1 1 0
1 1 0 0 0 1 0 1 0 1 1 1
1 1 1 0 1 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 0 0 0 1
The state provided as an initial condition will make the counter go into the lock state
after two state as shown below in the state diagram. Thus the number of state in the lock
cycle is five. Hence, the Mod of the counter is five.
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N = 5 states
101 010
001
100
011
110
111
Q.8 (b) (ii) Solution:

State Diagram:
0000
1001 0001
1000
0010
0111
0011
0110
0101 0100
Number of flip-flops required is ≥ log2 N = log210 = 4
Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ T3 T2 T1 T0

0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 1
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K-map for T3, T2, T, 1, T0 :
T3 T2
Q1 Q0 Q1 Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10
00 00 1
01 1 01 1
11 X X X X 11 X X X X
10 1 X X 10 X X
T3 = Q2Q1Q0 + Q3Q1Q0 T2 = Q1Q0
T1 T0
Q1 Q0 Q1 Q0
Q3Q2 00 01 11 10 Q3Q2 00 01 11 10
00 1 1 00 1 1 1 1
01 1 1 01 1 1 1 1
11 X X X X 11 X X X X
10 X X 10 1 1 X X
T1 = Q3Q0 T0 = 1
Thus, decade counter can be realized by T-flip flop and basic gates as given below
Q2
Q1
Q0 Q1 Q3
Q0 Q0
Q3
Q1
T3 Q3 T2 Q2 T1 Q1 1 T0 Q0
Q0
Q3 Q2 Q1 Q0
CLK
Q.8 (c) Solution:

• For the given system, the control input and the plant output are not in same
energy domain. Hence, the error signal will be,
E(s) = R(s) – H(s) C(s)
K 1K 2 K2
C(s) = (s + 2) E(s ) + (s + 2) D(s )
K 1K 2 ( s + 1) K 2 (s + 1)
So, E(s) = R( s) − ( s + 2) E( s) − (s + 2) D( s )
⎡ K1K 2 ( s + 1) ⎤ K 2 ( s + 1)
⎢1 + ⎥ E(s) = R(s ) − (s + 2) D(s )
⎣ (s + 2) ⎦
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(s + 2) R(s ) K 2 (s + 1) D(s )
E(s) = (s + 2) + K K (s + 1) − (s + 2) + K K (s + 1)
1 2 1 2
• Given that, both the input and the disturbance are unit step signals.
1
So, R(s) = D( s ) =
s
• The steady state error will be,
⎡ (s + 2) K2 (s + 1) ⎤
ess = lim sE(s) = lim ⎢ − ⎥
s→0 s → 0 ⎣ (s + 2) + K1K 2 (s + 1) (s + 2) + K1K 2 (s + 1) ⎦
2 − K2
ess =
2 + K1K 2
• The sensitivity of ess for changes in K1 will be,
e ∂ ess K 1 −(2 − K 2 )K 2 K 1 K 1K 2
SKss = × = × = −
1 ∂ K1 ess (2 + K1K 2 )2 ess 2 + K1K 2
• The sensitivity of ess for changes in K2 will be,
e ∂ ess K 2 ⎡ −(2 + K1K 2 ) − K 1 (2 − K 2 ) ⎤ K 2

SKss = × =⎢ ⎥×
2 ∂ K 2 ess ⎢⎣ (2 + K1K 2 )2 ⎥⎦ ess
2( K 1 + 1)K 2
= −
(2 − K 2 )(2 + K1K 2 )
• When K1 = 100 and K2 = 0.1,
e (100)(0.1) 10
SKss = − =− = − 0.833
1 2 + (100 × 0.1) 12
e 2(100 + 1)(0.1) 0.2 × 101

SKss = − (2 − 0.1)(2 + 100 × 0.1) = − 1.9 × 12 = − 0.886
2

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EE - PS EC-1 Micro-1 De-2 CS-2 - Solutions - 2451

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EE - PS EC-1 Micro-1 De-2 CS-2 - Solutions - 2451

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Detailed Solutions

ESE-2018 Electrical Engineering

Section A : Power Systems

Q.1 (a) Solution:

Q.1 (b) Solution:

Catchment area in km 2 × 106 × average annual rainfall in m × yield factor

200 × 106 × 1.25 × 0.75

Q.1 (c) Solution:

(or) (0.04 PG2 + 20) × 1 = 25

Power loss, B11 PG21 = 1 × 10–6 × (448.87)2 MW

Q.1 (d) Solution:

3.92 b 3.92 × 73.7

Q.1 (e) Solution:

Q.2 (a) Solution:

Spacing of conductors, d = 3.5 m = 3500 mm

Taking Ia as reference, Ib = α2 Ia,

Transmission line as transposed, the average inductance

for equilateral arrangement,

Cable impedance = j 0.05 p.u.

G1 SG1 = 20 + j 5.64 G2 SG2 = 20 + j 15.64

Q.2 (c) (i) Solution:

Q.2 (c) (ii) Solution:

Fault current in relay coil 10

Time corresponding to the PSM of 8 from given data is 3.5 seconds

Q.3 (a) (i) Solution:

Now, Va0 = Va2 = Va1 = Ea – Ia1Z1

Q.3 (a) (ii) Solution:

Q.3 (b) Solution:

Q.3 (c) (i) Solution:

Q.4 (a) (ii) Solution:

MVA rating × 106

Q.4 (b) (i) Solution:

Q.4 (b) (ii) Solution:

Initial power factor, cos φ = 0.75 (lag)

Q.4 (c) (ii) Solution:

Line voltage = 3 × 69.296 = 120.02 kV

Section B : Electrical Circuits-1 + Microprocessor-1 + Digital Electronics-2 + Control Systems-2

From the properties of star-delta transformation,

Q.5 (b) Solution:

Q.5 (c) Solution

Present state Excitations Next state

• The modulus of the counter = 6

Q.5 (d) Solution:

Q.5 (f) Solution:

Q.6 (a) Solution:

The above circuit can be further simplified as,

For simplifying the calculations, let us take C1 + C2 = Ce.

(ii) Given that, Vm = 10 V, R = 1 kΩ, C1 = 2 nF, C2 = 8 nF and L = 5 mH

and Iin = I4 when (b7 ... b0) = (0001 0000)

By applying KCL at node ‘A’, we get,

VA(Rx + 14Rx + 8R) = VRRx

Q.6 (c) Solution:

For system with controller:

• Maximum peak overshoot,

• Steady state error for unit ramp input,

Parameter Without controller With controller

Q.7 (a) Solution:

For the given two port network-A, according to reciprocity theorem,

According to maximum power transfer theorem, maximum power will be delivered to

Q.7 (b) Solution:

The basic voltage current relations of inductor and capacitor are,

Output matrix, [C] = [0 1]

(ii) Kalman’s test for controllability: