energies

Article
An Innovative Dual-Boost Nine-Level Inverter with
Low-Voltage Rating Switches
Meysam Saeedian 1 , Edris Pouresmaeil 1, * , Emad Samadaei 2 ,
Eduardo Manuel Godinho Rodrigues 3 , Radu Godina 4 and Mousa Marzband 5
1 Department of Electrical Engineering and Automation, Aalto University, 02150 Espoo, Finland;
meysam.saeedian@aalto.fi
2 Department of Electronics Design (EKS), Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden;
emad.samadaei@miun.se
3 Management and Production Technologies of Northern Aveiro—ESAN, Estrada do Cercal 449, Santiago de
Riba-Ul, 3720-509 Oliveira de Azeméis, Portugal; emgrodrigues@ua.pt
4 Research and Development Unit in Mechanical and Industrial Engineering (UNIDEMI), Department of
Mechanical and Industrial Engineering, Faculty of Science and Technology (FCT), New University of Lisbon,
2829-516 Caparica, Portugal; rd@ubi.pt
5 Department of Maths, Physics and Electrical Engineering, Faculty of Engineering and Environment,
Northumbria University, Newcastle upon Tyne NE1 8ST, UK; mousa.marzband@northumbria.ac.uk
* Correspondence: edris.pouresmaeil@aalto.fi; Tel.: +358-505-984-479




Received: 3 December 2018; Accepted: 4 January 2019; Published: 9 January 2019


Abstract: This article presents an innovative switched-capacitor based nine-level inverter employing
single DC input for renewable and sustainable energy applications. The proposed configuration
generates a step-up bipolar output voltage without end-side H-bridge, and the employed capacitors
are charged in a self-balancing form. Applying low-voltage rated switches is another merit of the
proposed inverter, which leads to extensive reduction in total standing voltage. Thereby, switching
losses as well as inverter cost are reduced proportionally. Furthermore, the comparative analysis
against other state-of-the-art inverters depicts that the number of required power electronic devices
and implementation cost is reduced in the proposed structure. The working principle of the proposed
circuit along with its efficiency calculations and thermal modeling are elaborated in detail. In the
end, simulations and experimental tests are conducted to validate the flawless performance of the
proposed nine-level topology in power systems.

Keywords: power conversion; multilevel inverter; improved switched-capacitor module; multi

carrier based modulation

1. Introduction
In recent years, extensive research has been carried out on multilevel inverters (MLIs) due to their
potential in various industrial applications, particularly grid-connected renewable energy sources,
machine drives, and high-voltage direct current transmission systems. Improved output waveforms
quality, reduced device stress (dv/dt), and increased efficiency are some merits of the MLIs in
comparison with the standard two-level inverter [1–4]. The most popular traditional/basic multilevel
topologies are CHB, NPC, and FC, which have widely been put into commercial use in high/medium
voltage systems (above 3 kV). Nonetheless, high control/modulation technique complexity and
large power electronic device count (dc power supplies, semiconductors, and capacitors) are cited as
demerits of the aforementioned topologies [5–7].
To overcome these drawbacks, researchers and industrialists all around the world are contributing
to present innovative topologies with the ability to produce more voltage levels with reduced device

Energies 2019, 12, 207; doi:10.3390/en12020207 www.mdpi.com/journal/energies

Energies 2019, 12, 207 2 of 15

count and to further improve energy efficiency. Apart from that, it has tried to develop MLIs with
lower voltage-rating switches and to cope with the voltage unbalancing problem in NPC and FC. These
attempts lead not only to reducing filter requirement and simplicity, but also cost/volume reduction of
the conversion system [8–10].
Despite a plethora of multilevel topologies that have been presented, intensive effort has been
devoted to introduce promising topologies. For example, ref. [11,12] presented novel MLIs employing
the technique of switched-capacitor. Although a substantial reduction in the device count is achieved
in these topologies as compared to the conventional ones, they however require H-bridge circuits to
generate bipolar voltages. This weakness leads to a sharp increase in total standing voltage (TSV)
and thereupon switches cost. A single source nine-level (9 L) inverter has been proposed in [13],
which applies semiconductors with the same Peak inverse voltage (PIV) equal to input voltage level.
Nevertheless, this topology utilizes numerous insulated-gate bipolar transistors (IGBTs) and gate
drivers, which enlarge the system. A hybrid cascaded MLI with improved symmetrical sub-module
was introduced in [14]. It employs four dc sources and ten switches with high PIVs to produce a 9 L
voltage waveform. Furthermore, [15] introduced a single source inverter which is comprised of an
H-bridge inverter and two switched-capacitor modules. It employs sixteen IGBTs with low voltage
ratings for generating a 7 L output voltage. Yet, these presented MLIs in the literature suffer from
either a large number of circuit elements or relatively high PIVs.
In summary, the main contribution of this paper is the development of a modified 9 L inverter
for single phase systems, which is superior to all the earlier topologies. The switches employed in
the proposed configuration enjoy low PIVs. At the same time, a further reduction in device count
and implementation cost is attained in the proposed circuit compared to the traditional/cutting-edge
ones. Moreover, there is no difficulty in the capacitors’ charging process since the inverter is inherently
self-balanced. Due to the voltage boosting capability, this inverter is proposed for grid-connected
renewable energy sources (such as solar and wind farms), uninterruptible power supplies, and
electric vehicles in which low input DC voltages are required to be boosted to an acceptable range for
these systems.
The rest of this article is structured into five sections. Following the introduction, Section 2
presents the operating principle and a detailed comparative study of the proposed topology in order to
demonstrate the superiority of the proposed inverter against newest 9 L topologies. Section 3 describes
PWM strategy applied to the proposed inverter. Efficiency calculations and thermal analysis are carried
out in Section 4. The simulation and experimental results are brought in Section 5 in order to prove
the feasibility and effectiveness of the presented topology. Eventually, conclusions are presented in
Section 6.

2. Analysis of the Proposed Nine-Level Inverter

2.1. Circuit Description

Figure 1 depicts the proposed switched-capacitor based inverter with the potential of generating
a 9 L staircase waveform (±2VIN , ±3VIN /2, ±VIN , ±VIN /2 and 0). As demonstrated in Figure 1,
it comprises twelve power switches, two capacitors (C1 , C2 ), and only one input DC source with the
advantage of regenerative capability. The output voltage can be boosted up to 2VIN by connecting the
input source with pre-charged capacitors in series. It should be underscored that the blocking voltage
of all switches employed in the proposed inverter is equal to the input DC source (i.e., VIN ), with the
exception of S7 , S8, and S12 which block only half the VIN . In other words, it generates a bipolar output
voltage without using end-side H-bridge. This ability is considered a beneficial feature of the proposed
circuit since the lower switch voltage rating, the cheaper switch.
The working principle of the proposed inverter is illustrated in Figure 2. As can be observed,
C1 and C2 are charged up to VIN /2 by turning S3 and S4 on during 0 and ±1VIN levels. Then, the
capacitors are connected in parallel at ±VIN /2 and ±3VIN /2 levels. Thereby, the voltage across them
Energies 2019, 12, x FOR PEER REVIEW 3 of 15

Energies 2019, 12, 207 3 of 15

S1 S3 S5 S9
C1
S7
is balanced. Finally, they areAdischarged across the load during ±VIN /2 and B ±2VIN levels. Relying on
VIN S11 S12
this simple switching plan, the
Energies 2019, 12, x FOR PEER REVIEW
proposed inverter does not require any external balancer circuit.3 of 15
S8
C2
S2 S4 S6 S10
S1 S3 S5 S9
C1
ILoad R LS7
+ -
A B
VIN S11VLoad=VA-VB S12
Figure 1. The proposed 9 L topology.
S8
C2
The working principle of S 2 proposed
the S4 inverterS6 is illustrated inSFigure
10 2. As can be observed, C1
and C2 are charged up to VIN/2 by turning S3 and S4 on during 0 and ±1VIN levels. Then, the capacitors
ILoad R L
are connected in parallel at ±VIN/2 and ±3V+ IN/2 levels. Thereby,
- the voltage across them is balanced.
Finally, they are discharged across the loadVduring
Load=VA-V
±VBIN/2 and ±2VIN levels. Relying on this simple
switching plan, the proposed inverter
Figuredoes
Figure 1. not
1. The
The require99any
proposed
proposed external balancer circuit.
LL topology.
topology.

SThe
1
working
S3 S5 principle ofS9 the proposed
S1 Sinverter
3 S5 is illustrated
S9
in Figure 2. As can be observed, C1
S1 S3 S5 S9
and C2 are chargedS7up to CV1 IN/2 by turning S3 and S4 on S7
C1 0 and ±1VIN levels. Then, the capacitors
during S7
C1
are
A
connected in parallel at ±VIN/2 Aand ±3V IN/2 levels. Thereby, the voltage across them is balanced.
V INS11 S12 B V S11 S12 B A
IN V S11 S12 B IN

Finally, they are discharged across the load during ±VIN/2 and ±2VIN levels. Relying on this simple
S8 S8 S8
switching plan, the proposed C2 inverter does not require anyC2external balancer circuit. C2
S2 S4 S6 S10 S2 S4 S6 S10 S2 S4 S6 S10

(a) (b) (c)

S1 S3 S5 S9 S1 S3 S5 S9 S1 S3 S5 S9
C1 C1 C1
S1 S3 S5 S7 S9 S7 S7
C1 S1 S3 S5 S9 S1 S3 S5 S9
S7 C1 C1
A VIN S11 S12 B A VIN S11 S7 S12 B A VIN S11 S7 S12 B
A VIN S11 S8 S12 B S8 S8
A VIN S11 S12 B A VIN S11 S12 B
C2 C2 C2
S2 S4 S6 S 8 S10 S2 S4 S6 S8 S10 S2 S4 S6
S8 S10
C2
S2 S4 S6 S10 C2 C2
(a) S2 S4 S6
(b) S10 S2 S4 S6
(c) S10

S1 S3 S5 S9
(d) C1 S1 S3 S(e)
5 S9 S1 S3 S(f)
5 S9
S7 C1 C1
S7 S7
S1 S3 S5 S9 S1 S3 S5 S9
A S1 VIN S3S11 S5 S12 S9 B C1 C1
C1 A VIN S11 S7 S12 B A VIN S11 S7 S12 B
S7
S8
C2 A VIN S11 S8 S12 BA VIN S11 S8 S12 B
A S2 VIN S4 S11 S6 S12 S10 B C2 C2
S2 S4 S6 S8 S10 S2 S4 S6 S8 S10
S8 C2 C2
C2 S2 S4 S6 S10 S2 S4 S6 S10
S2 S4 S6
(d) S10 (e) (f)

S1 S3 S5 S9 S1 S3 S5 S9
S1 S3 S(g)
5 S9 (h) C1 (i) C1
C1 S7 S7
S7
Figure 2.
Figure 2. Switching
Switching states
states of of the
the proposed
A proposed
inverter,(a)
inverter, (a)+2V
+2VIN
IN,, (b)
(b) +3V
+3VIN
IN/2,
/2,(c)
(c)V+V
+V , (d)
ININ , (d)+V+V
IN/2, (e) (e)
IN /2, 0; (f)
0;
V S11 IN S12 BA S11 S12 IN B
A V
−V−
(f) IN/2,
IN S 11
VIN(g) /2,−V IN,−
(g) (h)
VIN S
−3V 12
, (h) IN/2,
−3VB
(i)IN
−2V . −2VIN .
/2,IN(i)
S8 S8
S8 C2 C2
2.2. C2 S2 S4 S6 S10 S2 S4 S6 S10
2.2.SComparative
Comparative
2 S4
Assessment
S6 AssessmentS10
Table
Table 11 compares
compares the
the presented
presented circuit
circuit with other
with(h)other recently-introduced
recently-introduced topologies
topologies in
in terms
terms of of the
the
(g) (i)
number
number of required semiconductors/DC sources and switches voltage rating. As observed from the
of required semiconductors/DC sources and switches voltage rating. As observed from the
table, ref.
[14] [14]
table,Figure the the proposed
2. Switching
proposed states circuit
of
circuit the employs
proposed
employs the least
theinverter,
least (a) number
number+2VofIN, (b)of switches
+3V and
IN/2, (c) +V
switches capacitors
IN, (d)
and capacitors +VIN /2, (e)compared
compared 0; (f)to the
to
other IN/2, (g)
the−Vones.
other −VINThese
ones.
These , (h) −3V IN/2, (i) −2VIN. result in simpler control and a higher degree of compactness.
minimizations
minimizations result in simpler control and a higher degree of compactness. Apart
Apart
from this, the table depictsdepicts
from this, the table a fourfolda fourfold
increase increase in the number
in the number of required
of required DC power DC supplies
power supplies
for [14]
2.2.
for Comparative
[14] and Assessment
conventional CHB, while the others and proposed inverter utilize only one DC source.
and conventional CHB, while the others and proposed inverter utilize only one DC source.
Applying
Table
Applying switches
1 compares
switches with
the lower
lower PIV
presented
with is
is also
circuit
PIV with
also aa distinct advantage
advantage of
other recently-introduced
distinct of the
the proposed
topologies
proposed inverter.
in terms
inverter. In
Inofother
the
other
words,
number it enjoys
words, itofenjoys the
required lowest level
semiconductors/DC
the lowest of TSV.
level of TSV. To To prove
sources
proveandthis, the number
this,switches
the number of
voltage employed IGBTs
rating. AsIGBTs
of employed with
observed the
the same
with from the
same
voltage
table, [14]rating for each structure
the proposed is presented
circuit employs the leastin number
the following table.and
of switches For capacitors
instance, the proposed
compared 9L
to the
other ones. These minimizations result in simpler control and a higher degree of compactness. Apart
from this, the table depicts a fourfold increase in the number of required DC power supplies for [14]
and conventional CHB, while the others and proposed inverter utilize only one DC source.
Applying switches with lower PIV is also a distinct advantage of the proposed inverter. In other
words, it enjoys the lowest level of TSV. To prove this, the number of employed IGBTs with the same
Energies 2019, 12, 207 4 of 15

inverter needs nine and three switches with the PIV of 1VIN and VIN /2 respectively, while [13] requires
nineteen IGBTs with the voltage ratings of VIN . Thereby, the proposed inverter can be an acceptable
alternative to the topologies listed in Table 1.

Table 1. Comparison of the proposed topology with other recently presented inverters.

Comparison Item CHB (Con.) [11] (2010) [12] (2017) [13] (2018) [14] (2018) [15] (2018) Proposed
Level 9 9 9 9 9 7 9 8M * + 1
Switch 16 13 12 19 10 16 12 12M
Capacitor - 3 4 3 - 2 2 2M
DC source 4 1 1 1 4 1 1 M
4 × 4VIN
4 × 4VIN 4 × 4VIN 9 × VIN 9M × VIN
N * × PIV 16 × 1VIN 19 × 1VIN 2 × 3VIN 16 × 1VIN
9 × 1VIN 8 × 1VIN 3 × VIN /2 3M × VIN /2
4 × 1VIN
TSV 16VIN 25VIN 24VIN 19VIN 26VIN 16VIN 21VIN /2 M × (21VIN /2)
M *: Number of cascaded modules.

Furthermore, the single-source topologies are also compared in terms of total implementation cost
(see Table 2). It should be noted that CHB and [14] are not considered in the cost-comparative analysis
since they require four DC power supplies. For a fair comparison, power rating (i.e., volt/ampere
rating) of all the MLIs are assumed to be equal to 5 kW/30.7 A. Moreover, a 50% voltage rating margin
is considered for the selection of switches and capacitors. It is observed from Table 2 that the proposed
inverter requires the least implementation cost compared to the other ones.

Table 2. Price Comparison of the Single-Source MLIs.

Voltage Rating Unit Price *

Part Part Number [11] [12] [13] [15] Proposed
(V) (€)
STW40NF20 200 3.53 9 8 19 - 3
SUP40N25-60-E3 250 4.43 - - - 16 9
MOSFETs
FQL40N50 450 7.73 - - - - -
SIHG47N60AEFGE3 600 7.82 4 4 - - -
E32D151HPN472TEE3M 150 23.00 3 2 4 - 2
Capacitors B43713F2478M000 250 39.39 - - - 2 -
ALS31A472NF350 350 48.83 - 2 - - -
Gate driver IRS21271SPBF - 1.34 13 12 19 14 12
Total cost (€) 149.47 219.26 184.53 168.42 112.54
* Source: www.mouser.com.

3. Multicarrier PWM Strategy

Therein, phase disposition PWM technique is applied to control each IGBT of the proposed
topology. To do this, eight triangular carriers (Vt1 to Vt8 ) arranged with shifts in amplitudes are
required (see Figure 3a). It should be noted that they are the same in amplitude (At ), frequency (ft ) and
phase [16,17]. The carriers are compared to a reference waveform (Vref ) which results in generating
appropriate fire pulses for all switches. For instance, S11 is turned on when Vref > Vt1 or Vt2 < Vref < Vt1
or Vt8 < Vref < Vt7 or Vref <Vt8 . In other words, S11 must be turned on when S1 : ON, S4 : ON, S3 : OFF
(or S2 : ON, S3 : ON, S4 : OFF), which can be observed in Figure 2. Similarly, S12 is turned on when Vref >
Vt1 or Vt3 < Vref < Vt2 or Vt5 < Vref < Vt4 or Vt7 < Vref < Vt6 or Vref < Vt8 . In other words, S12 must be
turned on when S7 and S8 are OFF (see Figure 2). Further clarification concerning switching strategy is
brought up in Figure 3b and Table 3.
Energies 2019, 12, 207 5 of 15

Energies 2019, 12, x FOR PEER REVIEW 5 of 15

Vref
Are f 4At
Vt1
3At
Vt2
2At
Vt3
At
Vt4
Vt5
-At
Vt6
-2At
Vt7
-3At
Vt8
-4At

2VIN
3VIN/2
VIN
VIN/2
0
-VIN/2
-VIN
-3VIN/2
-2VIN

0 t1 t2 t3 t4 t5 t6 π t7 t8 t9 t10 t1 1 t12 2π
(a)
S12
Vref

N OT
N OT
AND
N OT
OR S 7 & S8
AND
+
Vt1 -
AND
OR S6
+
Vt2 - AND
OR S5
Vt3 +
- OR S4

Vt4 + S1
-
N OT
AND
N OT
S2
Vt5 + N OT
-
N OT
AND

Vt6 + OR S3
-
AND
Vt7 +
-
N OT
AND
Vt8 +
-
N OT OR S11
N OT

S10
N OT
S9
(b)
Figure3.3.(a)
Figure (a) PWM
PWM technique,
technique, (b)
(b)Logic
Logicschematic.
schematic.

Table 3. On-State
Table3. IGBTs for
On-State IGBTs for Each
EachLevel.
Level.

Relationship
Relationship between
between the the Carriers
Carriers and and
Vref Vref ON-State
ON-StateIGBTs
IGBTs Levels
Levels
Vref V
>refV>t1
Vt1 S1S -S1-S 4-S5-S10-S11-S12
4 -S5 -S10 -S11 -S12
+4V IN
+4V IN
Vt2 <VV
t2 < V
ref < ref
V <t1 Vt1 S1S-S1-S 4-S5-S7-S8-S10-S11
4 5 -S7 -S8 -S10 -S11
-S +3V IN
+3V IN
Vt3 <VV
t3 < V
ref <refV< t2 Vt2 S1S-S1-S
3 -S3-S
4 -S4-S-S
5 5-S 6-S10
6 -S 10 -S -S1212 +2V
+2V
IN
IN
Vt4 <VV <V
t4 ref <refV<t3 Vt3 S1S-S1-S 3-S
3 -S 5-S
5 -S 7-S
7 -S 8-S
8 -S 1010 +1V
+1V
IN IN

Vt5 <VV <V

t5 ref <refV<t4 Vt4 S2S-S2-S
3 -S 4 -S
3-S 5 -S
4-S 5-S6 -S
6-S1010-S-S1212 0 0
Vt6 <VV <V
t6 ref <refV<t5 Vt5 S2S-S2-S
4 -S4-S6 -S 7 -S
6-S 7-S8 -S
8-S99 −1V
−1V IN IN
Vt7 <VV <V
t7 ref
<refV<t6 Vt6 S2S-S2-S
3 -S 4 -S
3-S 4-S5 -S
5-S6 -S
6-S9 -S
9-S 1212 −2V
−2V IN IN
Vt8 < Vref < Vt7
Vt8 < Vref < Vt7 S2 -S3 -S6 -S7 -S8 -S9 -S11
S2-S3-S6-S7-S8-S9-S11 −3V
−3V IN
IN
Vref < Vt8 S2 -S3 -S6 -S9 -S11 -S12 −4VIN
Vref < Vt8 S2-S3-S6-S9-S11-S12 −4VIN
Energies 2019, 12, 207 6 of 15

4. Loss Distribution and Thermal Modeling

4.1. Power Loss Analysis

The power loss for a multilevel inverter is composed of three parts including PC , PS and PR which
are elaborated as follows:

4.1.1. Conduction Loss (PC )

PC is caused by parasitic resistance (i.e., ON-state resistance of the switch (RS ) and its parallel
diode (RD ), capacitor internal resistance (RC )) involved in the current paths [18]. Table 4 shows the
equivalent value of the parasitic resistance (Req ) existing in each voltage level. It should be noted that
in the present work RS , RD, and RC are considered equal to 0.27 Ω, 0.05 Ω, and 0.03 Ω, respectively.

Table 4. Req in Each Step.

Output Level Req (Ω)

0 2RS + 2RD = 0.64
±VIN /2 3RS + 2RD + RC = 0.94
±VIN 3RS + RD = 0.86
±3VIN /2 5RS + RD + RC = 1.43
±2VIN 6RS + 2RC = 1.68

If |Vref | < At , the output voltage switches between 0 and +VIN /2 (see Figure 3a). Consequently,
the output current passes through two switches and two diodes (three switches, two diodes, and one
capacitor) during 0 (+VIN /2) level, as depicted in Table 4. In this case, the energy dissipated within
0 < t < t1 (t6 < t < t7 or t12 < t < 2π) is attained by Equation (1) in which At , Aref , and fref are considered
equal to 0.25, 0.9, and 50 Hz, respectively [18]. Moreover, t1 is calculated as follows:

Rt1h  i2  A sin(2π f t)


Are f sin(2π f re f t)

E0&VI N /2 = ILoad sin 2π f re f t × (3RS + 2R D + RC ) re f At re f +(2RS + 2R D ) 1 − dt
0
At (1)
= 2.04 × 10−5 × ( Pout/VI N )2

sin−1 ( At/Are f ) sin−1 (0.25/0.9)

t1 = = = 9 × 10−4 sec. (2)
2π f re f 100π
Similarly, the energy losses that occurred in other time intervals are calculated by Equations (3)–(8).

Rt2h  i2  A sin(2π f re f t)− At


Are f sin(2π f re f t)− At

EVI N /2 &VI N = ILoad sin 2π f re f t × (3RS + R D ) re f +( 3R S + 2R D + R C ) 1− dt
t1
At At (3)
2
= 2.03 × 10−4 × ( Pout/VI N )

sin−1 (2At/Are f ) sin−1 (0.5/0.9)

t2 = = = 1.87 × 10−3 sec. (4)
2π f re f 100π

Rt3h  i2  A sin(2π f re f t)−2At


Are f sin(2π f re f t)−2At

EVI N &3VI N /2 = ILoad sin 2π f re f t × (5RS + R D + RC ) re f +(3RS + R D ) 1 − dt
t2
At At (5)
2
= 7.2 × 10−4 × ( Pout/VI N )

sin−1 (3At/Are f ) sin−1 (0.75/0.9)

t3 = = = 3.1 × 10−3 sec. (6)
2π f re f 100π

Rt4h  i2  A sin(2π f re f t)−3At


Are f sin(2π f re f t)−3At

E3VI N /2 &2VI N = ILoad sin 2π f re f t × (6RS + 2RC ) re f +( 5R S + R D + R C ) 1− dt
t3
At At (7)
2
= 0.0051 × ( Pout/VI N )
Energies 2019, 12, 207 7 of 15

π − sin−1 (3At/Are f ) π − sin−1 (0.75/0.9)

t4 = = = 6.86 × 10−3 sec. (8)
2π f re f 100π
Due to quarter-wave symmetry of the output voltage, the total conduction loss for the proposed
9 L topology is:

PC = 4E0 &VI N /2 + 4EVI N /2 &VI N + 4EVI N &3VI N /2 + 2E3VI N /2 &2VI N × f re f = 0.69 × ( Pout/VI N )2


(9)

4.1.2. Switching Loss (PS )

The overlap of switch voltage and current during rise and fall times (i.e., ton and toff ) leads to PS ,
which is highly proportional to the fS . The turn-on and turn-off power loss of the switch S are attained
by [19]:
Zton Zton   on
IS

VS 1
PS, on = f S vS (t) iS (s) dt = f S t − (t − ton ) dt = f S VS ISon ton (10)
ton ton 6
0 0
t t
Zo f f Zo f f of f
! !
VS I   1 of f
PS,o f f = f S vS (t) iS (t) dt = f S t − S t − to f f dt = f V I t (11)
to f f to f f 6 S S S of f
0 0
on off )
In which IS (IS is the switch current after (before) turning on (off). Considering ton = toff =
58 ns and ft = 4 kHz, PS for all the switches is obtained as follows:

ILoad
PSj,on = PSj,o f f = 1
6 × 12 × 4 × 103 × VI N × π × 58 × 10−9 = 6.15 × 10−6 × Pout , j = 1, 2, 9, 10, 11 (12)

1 I
PSj,on = PSj,o f f = × 4 × 103 × VI N × Load × 58 × 10−9 = 12.3 × 10−6 × Pout , j = 3, 4, 5, 6 (13)
6 π
1 1 V I
PSj,on = PSj,o f f = × × 4 × 103 × I N × Load × 58 × 10−9 = 3.07 × 10−6 × Pout , j = 7, 8 (14)
6 2 2 π
1 1 V I
PS12,on = PS12,o f f = × × 4 × 103 × I N × Load × 58 × 10−9 = 3.07 × 10−6 × Pout (15)
6 2 2 π
Consequently, the total switching loss for the presented 9 L inverter is calculated by:

Nswitch
∑ PSj, ON + PSj ,OFF = 178 × 10−6 × Pout


PS = (16)
j =1

4.1.3. Power Loss Generated by Capacitor Voltage Ripple (PR )

PR is due to the voltage difference between the capacitor and input DC source during the charging
periods. Generally, the maximum discharging value of each capacitor in a switched-capacitor circuit is
attained by [13,18]:
Ztd
∆QC = ILoad Sin(2π f re f t)dt (17)
tc

where [tc , td ] is the discharging interval of each capacitor. According to Figures 2a and 3a, the maximum
discharging period of C1 (or C2 ) is equal to [t3 , t4 ]. Thus, considering maximum acceptable voltage
drop across C1 (or C2 ) equal to ∆Vripple , the capacitance of each capacitor is calculated by [13,18]:

∆QC
C≥ (18)
∆Vripple × 0.5VI N
where [tc, td] is the discharging interval of each capacitor. According to Figures 2a and 3a, the
maximum discharging period of C1 (or C2) is equal to [t3, t4]. Thus, considering maximum acceptable
voltage drop across C1 (or C2) equal to ΔVripple, the capacitance of each capacitor is calculated by
[13,18]:
Energies 2019, 12, 207 8 of 15
Δ QC
C≥ (18)
ΔV ripple × 0.5V IN
For example, considering Pout = 1.4 kW (ILoad = 7 A, VIN =200 V) and ∆Vripple = 10%, the capacitances
For
for the example,
proposed considering
inverter Pout = 1.4askW
are obtained (ILoad = 7 A, VIN=200 V) and ΔVripple = 10%, the capacitances
follows:
for the proposed inverter are obtained as follows:
0.00686
R 0.00686
7 × Sin(100πt)dt
0.0031 
7 × Sin( 100π t )dt 0.024
C1 = CC2 = 0.024
= = 2400 µF (19)
(19)
= = = 10= 2400 μ F
0.0031
1 C 2 0.1 × 100 0.1 × 100 10
ItItalso
alsoshould
shouldbe
benoted
notedthat
thatnominal
nominalvoltage
voltageofofthe
thecapacitors
capacitorsisisequal
equaltotoVV
ININ/2
/2 (see
(see Figure
Figure 2).
2).
Consequently, P for the proposed topology is attained as follows:
Consequently, PRR for the proposed topology is attained as follows:

 0.00686  = 0.088 × ∆V
!
PRP== re2ffref ∑ Ci C
2
2 0.00686
 2 
2

2   ( )
f
ΔV × 0.5V
∆Vripple = 50 × 
I Loadsin(100π t )dt × ΔVripple× 0.5V I N = 0.088 × ΔV ripple
∆V × P × Pout (20)
R
× 0.5V = 50 × I sin (  0.0031
100πt ) dt × × 0.5V

R i ripple
IN
IN  Load ripple IN ripple out (20)
i =1
i =1   0.0031 
Therefore,
Therefore,considering
consideringEquations
Equations(9),
(9),(16),
(16),and
and(20),
(20),the
theefficiency
efficiencyisiscalculated
calculatedby
byEquation
Equation(21).
(21).
PoutP PPoutout
η = η = out
== (21)
(21)
P +
Pin P Pout
in
PC++PP+
+P S+
outP PR C S R

Theoretical
Theoreticalefficiency
efficiencyofofthe
theproposed
proposedinverter
inverterhas
hasbeen
beencalculated
calculatedatatdifferent
differentoutput
outputpower
powerand
and
presented
presented in Figure 4. It is observed that there is a marked rise in the efficiency by increasing the
in Figure 4. It is observed that there is a marked rise in the efficiency by increasing the
output
outputpower.
power.

100

98

96
EFFICIENCY (%)

94

92

90

88

86

84
0 250 500 750 1000 1250 1500 1750 2000 2250
POUT (W)

Figure4.4. Inverter
Figure Inverter efficiency
efficiencyat
atdifferent
differentpower
poweroutput.
output.

4.2.
4.2.Thermal
ThermalModel
Model
Heat
Heatdistribution
distribution through
throughsemiconductor
semiconductor components
components is is caused
caused by by power
power loss,
loss,which
whichleads
leadstoto
an
an increasing of Tj [20]. This temperature, for safety reasons, should be monitored and kept withinaa
increasing of Tj [20]. This temperature, for safety reasons, should be monitored and kept within
specified
specifiedrange
rangeduring
duringthe theinverter
inverter operation.
operation.Figure
Figure5a 5a
illustrates thethe
illustrates thermal model
thermal implemented
model implemented for
afor
single semiconductor, in which the thermal impedance between junction
a single semiconductor, in which the thermal impedance between junction and and case (Z th ) is considered
case (Zth) is
aconsidered
four-layer afoster network (see Figure 5b) [21,22]. It should be noted that Zc and
four-layer foster network (see Figure 5b) [21,22]. It should be noted that Zc and Z s are the thermal
Zs are
impedances from the case to the heat sink and from the heat sink to the ambient,
the thermal impedances from the case to the heat sink and from the heat sink to the ambient, respectively. These
are found on the
respectively. manufacturer
These are found on datasheet.
the manufacturer datasheet.
Energies 2019,
Energies 2019, 12, x
207 999of
of 15
15
Energies 2019,12,
12, xFOR
FORPEER
PEERREVIEW
REVIEW of 15

TTj j ZZthth TTcc ZZcc TTss ZZss TTaa

ΔP
ΔP CCthth CCss

Sem
Semiconductor
iconductor Sem iconductor Heat
Semiconductor HeatSink
Sink
Case
Case
(a)
(a)

RRth1
th1 RRth2
th2 RRth3
th3 RRth4
th4
TTj j
CCth1 CCth2 CCth3 CCth4
ΔP

th1 th2 th3 th4

ΔP

ZZthth
TTaa TTcc
(b)
(b)

Figure
Figure 5.5.(a)
Figure5. (a)Semiconductor
(a) Semiconductorthermal
Semiconductor thermal model;
thermalmodel; (b)
model;(b) foster
(b)foster network
fosternetwork of
networkof ZZth
ofZ th..
th.

Modelling
Modellingloss dissipationof
lossdissipation ofthe proposed99LLinverter
theproposed inverterin inMATLAB/Simulink
MATLAB/Simulinkyields yields the
yieldsthe
the
◦
junction
junction
junction
temperature of the power electronic devices [23–25]. Herein, T a is
temperature of the power electronic devices [23–25]. Herein, Ta is considered equal to 40 °C andthe
is considered equal to 40 °CC and the
PM75CLA060
PM75CLA060switch producedby
switchproduced byMitsubishi
MitsubishiElectric
Electricisischosen
chosenininthe thethermal
thermalestimation.
estimation.
The estimated
Theestimated of
estimatedTTjj jof some
ofsome power
somepower switches
powerswitches employed
switchesemployed
employedin in the
inthe proposed
theproposed inverter
proposedinverter at
inverteratat20
20kWkWoutput
output
in Figure 6. can be observed that S has the lowest (approximately 43.9 ◦ C),
power is illustrated It
power is illustrated in Figure 6. It can be observed that S12 has the lowest Tj (approximately 43.9°C),
12 has
12 the lowest T jj (approximately 43.9 °C),
◦
while thistemperature
whilethis temperatureapproaches
approaches46.7 46.7°CC for
°C forSS11
11..
11.

45
45
j, S1
j, S1

44.5
44.5
TT

44
44

45
45
j, S9
j, S9

44.5
44.5
TT

44
44

47
47
j, S11
j, S11

46.5
46.5
TT

46
46

44.5
44.5
j, S12
j, S12

44
44
TT

43.5
43.54 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
Time (sec)
Time (sec)
Figure
Figure6. The
Theestimated
estimatedT j at 20 kW output power.
Figure 6.6.The estimated TTj j at
at 20
20 kW
kW output
output power.
power.

5. Simulation and Experimental Results

Simulations have been conducted in MATLAB for steady-state and transient modes, as presented
below. Figure 7 shows the inverter output voltage/current and capacitors voltage at resistive-inductive
load (ft = 4 kHz, C1 = C2 = 2300 µF, R = 100 Ω, L = 100 mH). These results confirm the flawless
performance and self-balanced ability of the presented 9 L inverter. Moreover, the value of the input
DC source is selected at 200 V. Thus, the capacitors and output voltages reach 100 V and 400 V,
 Energies 2019, 12, 207 10 of 15

respectively.
Energies ThePEER
2019, 12, x FOR proposed topology has also been simulated under step change in the load, and the
REVIEW 10 of 15
results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors rises
promptly from
5. Simulation 3.5% to 7.2% byResults
and Experimental decreasing the load impedance. Once again, these figures verify the
inherent capacitor voltage balancing ability during inverter operation.
Simulations have the
Figure 9 shows been conducted
voltage waveforms in across
MATLAB some for powersteady-state and transient
switches employed modes, as
in the proposed
presented below.
topology. Figure
It is clear that S 73 ,shows
S5, and the inverter
S11 (also S1 , S2 ,output
S4 , S6 , S9voltage/current and capacitors
and S10 ) must withstand voltage
voltages equal to at
resistive-inductive
the input DC sourceload(i.e.,
(ft =200
4 kHz, C1 = switches
V). Other C2 = 2300 (S7µF,
, S8 Rand= 100
S12 ),Ω, L = 100block
however, mH). These equal
voltages results
to confirm
half
the flawless
the inputperformance
DC source (i.e., and100 self-balanced
V). To sum up, ability
unlike oftopologies
the presented with 9end
L inverter. Moreover,
side H-bridge, thethe
none of value
of theswitches
input DCrequired
source foristhe proposed
selected inverter
at 200 tolerate
V. Thus, themaximum
capacitorsoutput voltagevoltages
and output (i.e., 400 V).
reach 100 V and
Furthermore,The
400 V, respectively. the effect of different
proposed modulation
topology has also indexes
beenand switching
simulated frequencies
under on the operation
step change in the load,
of the proposed inverter is shown in Figure 10. It is observed that the inverter
and the results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors output voltage has
lower THD at higher modulation index (and higher switching frequency). Moreover, the fundamental
rises promptly from 3.5% to 7.2% by decreasing the load impedance. Once again, these figures verify
component of output voltage is decreased at lower modulation index.
the inherent capacitor voltage balancing ability during inverter operation.

400
modulation index=0.9
200
VIN
VLoad (V)

-200

-400

2
ILoad (A)

-2

-4

6
IInput (A)

100
VC1 (V)

98

96
0 96 0 97 0 98 0 99 1

100
VC2 (V)

98

96
0.96 0.97 0.98 0.99 1
Time (sec)

Figure 7. Operation
Figure 7. Operationofofthe
thepresented modelunder
presented model underconstant
constant load.
load.
 400

200

VLoad (V)
0
Energies 2019, 12, 207 11 of 15
-200 REVIEW
Energies 2019, 12, x FOR PEER 11 of 15
-400
400

8
200 Load reduction at VLoad=0

VLoad (V)
4
0

ILoad (A)
0
-200

-4
-400
R=100 , L=0.1 H R=50 , L=0.05 H
-88
Load reduction at VLoad=0
84
Load reduction at VLoad=2VIN
ILoad I(A) (A)

40
Load

0
-4

-4 R=100 , L=0.1 H R=50 , L=0.05 H

-8

-88
08 09 1 11
Load reduction at VLoad=2VIN
100
4
V (V)
ILoadC1(A)

95
0
90
-4
100
-8
VC1 (V) VC2 (V)

08 09 1 11
95
100
90
0.8
95 0.9 1 1.1 1.2
Time (sec)
90
Figure 8. Operation of the presented model under sudden load reduction.
100
VC2 (V)

Figure 9 shows the voltage waveforms across some power switches employed in the proposed
95
topology. It is clear that S3, S5, and S11 (also S1, S2, S4, S6, S9 and S10) must withstand voltages equal to
90
the input DC source (i.e.,
0.8 200 V). Other 0.9 switches (S7, S
1 8 and S12), however,
1.1 block voltages
1.2 equal to half
Time (sec)
the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the
switches requiredFigure
for the
Figure 8.8.proposed
Operation inverter
Operationof
of the tolerate
the presented
presented maximum
model
model output
undersudden
under sudden voltage
load
load (i.e., 400 V).
reduction.
reduction.

Figure 9 shows200the voltage waveforms across some power switches employed in the proposed
topology. It is clear that S3, S5, and S11 (also S1, S2, S4, S6, S9 and S10) must withstand voltages equal to
VS3 & VS5

the input DC source (i.e., 200 V). Other switches (S7, S8 and S12), however, block voltages equal to half
100 S3
the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the
S5
switches required for the proposed inverter tolerate maximum output voltage (i.e., 400 V).
0
200

200
& VS5

S11
100 S3 S7
VS7 &VVS11
S3

100 S5

0
200
0.96 0.97 0.98 0.99 1
Time (sec)
S11
S
VS7 & VS11

7
Figure9.
Figure Voltages
9.Voltages across
across the
theswitches.
switches.
100

0
0.96 0.97 0.98 0.99 1
Time (sec)

Figure 9. Voltages across the switches.

Energies 2019, 12, x FOR PEER REVIEW 12 of 15

Furthermore, the effect of different modulation indexes and switching frequencies on the
operation of the proposed inverter is shown in Figure 10. It is observed that the inverter output
Energies 2019,
voltage has12, 207 THD at higher modulation index (and higher switching frequency). Moreover,
lower 12 of 15
the
fundamental component of output voltage is decreased at lower modulation index.
400 400
Ma= 1 Ma= 1
fsw= 4 kHz fsw= 7 kHz
200 200
VLoad (V)

VLoad (V)
0 0

-200 -200

-400 -400
0.96 0.97 0.98 0.99 1 0.96 0.97 0.98 0.99 1

10 10
Mag (% of Fundamental)

Mag (% of Fundamental)
Fundamental (50Hz) = 399.5 Fundamental (50Hz) = 399.9
8 THD= 13.79% 8
THD= 13.64%
6 6

4 4

2 2

0 0
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Frequency (Hz) Frequency (Hz)
400 400
Ma= 0.8 Ma= 1
fsw= 4 kHz fsw= 2 kHz
200 200

VLoad (V)
VLoad (V)

0 0

-200 -200

-400 -400
0.96 0.97 0.98 0.99 1 0.96 0.97 0.98 0.99 1

10
Mag (% of Fundamental)

Mag (% of Fundamental)

Fundamental (50Hz) = 319.8 Fundamental (50Hz) = 399.4

10 THD= 17.29% 8
THD= 13.75%
6

5 4

0 0
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Frequency (Hz) Frequency (Hz)
400 400
Ma= 0.7 M a= 1
fsw= 4 kHz fsw= 1 kHz
200 200
VLoad (V)
VLoad (V)

0 0

-200 -200

-400 -400
0.96 0.97 0.98 0.99 1 0.96 0.97 0.98 0.99 1

10
Mag (% of Fundamental)
Mag (% of Fundamental)

Fundamental (50Hz) = 400

15 Fundamental (50Hz) = 280
8 THD= 14.05%
THD= 21.38%
10 6

4
5
2

0 0
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Frequency (Hz) Frequency (Hz)

(a) (b)

Figure10.
Figure 10.The
Theeffect
effectof
of(a)
(a)modulation
modulationindex
indexon
onthe
theVVLoad
Load, (b) switching frequency on the VLoad
Load..

To validate
validatethe
thehigh performance
high performance of the
of proposed model,model,
the proposed a low-power prototype
a low-power of the proposed
prototype of the
inverter has
proposed been implemented
inverter and tested. Accordingly,
has been implemented and tested. aAccordingly,
Texas Instruments
a Texas(TMS320F28335)
Instruments
fixed-point DSP control
(TMS320F28335) boardDSP
fixed-point generated
controlgate pulses
board for employed
generated switches
gate pulses for(IRFP460
employed500 switches
V/20 A).
Moreover,500
(IRFP460 theV/
value of capacitances
20 A). Moreover, the and inputofDC
value source are and
capacitances selected at DC
input 2300source
µF andare140 V, respectively.
selected at 2300
Figure
µF and11 140
illustrates the results obtained
V, respectively. Figure from the hardware
11 illustrates the implementation
results obtained of the proposed
from inverter
the hardware
model under steady-state
implementation and transient
of the proposed operating
inverter modelconditions. These figures and
under steady-state fully transient
confirm the flawless
operating
performance
conditions. of thefigures
These proposed
fullyinverter.
confirm the flawless performance of the proposed inverter.
Energies 2019,2019,
Energies 12, x12,
FOR207 PEER REVIEW 13 of 15
13 of 15

VLoad

ILoad

ZLoad1=50 Ω + 100 mH

(a)

VLoad

Load reduction

ILoad

ZLoad2=ZLoad1 || 75 Ω + 100 mH

(b)
Figure 11. 11.
Figure Output voltage/current
Output voltage/currentunder,
under, (a) constant
constantload;
load;(b)(b) step
step change
change in the
in the load.load.

6. Conclusions
6. Conclusions
Herein, the operating principle of a new 9 L inverter has been discussed and confirmed
Herein, the operating principle of a new 9 L inverter has been discussed and confirmed
experimentally. The comparative analysis depicted that the presented topology not only reduces the
experimentally. The comparativelinks
number of semiconductors/DC analysis depicted
required that thea presented
for generating 9 L voltage topology
waveform,notbut only reduces the
also employs
number
IGBTsofwith
semiconductors/DC
lower PIV. These meritslinksleadrequired
to a highfor generating
compactness anda cost
9 Lreduction
voltage ofwaveform, but also
the conversion
employs IGBTs with lower PIV. These merits lead to a high compactness and cost
system. Due to the intrinsic self-voltage balancing ability, there is no need for complex modulationreduction of the
conversion
methods. system. Due to
Thereupon, the intrinsic
it enjoys simple self-voltage balancing ability,
control and implementation. there is no the
Furthermore, need for complex
theoretical
modulation
efficiencymethods. Thereupon,
demonstrated it enjoysconfiguration
that the presented simple control has and
higherimplementation. Furthermore,
efficiency by increasing output the
power (up to 2000 W). Eventually, the feasibility and effectiveness of the proposed
theoretical efficiency demonstrated that the presented configuration has higher efficiency by model was verified
by the simulation
increasing output powerand experimental
(up to 2000 W). results.
Eventually, the feasibility and effectiveness of the proposed
model wasContributions:
Author verified by theAll simulation and experimental
authors contributed results.
equally to this work and all authors have read and approved the
final manuscript.
Author Contributions:
Funding: Allreceived
This research authorsno
contributed equally to this work and all authors have read and approved the
external funding.
final manuscript.
Conflicts of Interest: The authors declare no conflicts of interest.
Funding: This research received no external funding.

Conflicts of Interest: The authors declare no conflicts of interest.

Energies 2019, 12, 207 14 of 15

Nomenclature
MLIs Multilevel inverters
CHB Cascaded H-bridge
NPC Neutral point clamped
FC Flying capacitor
TSV Total standing voltage (V)
PIV Peak inverse voltage (V)
PWM Pulse width modulation
DSP Digital signal processor
VIN and IIN Input voltage (V) and current (A) of the inverter
VLoad and ILoad Maximum load voltage (V) and current (A)
Vt Triangular carrier of the PWM modulation
Vref Reference waveform of the PWM modulation
VS and IS Voltage (V) and current (A) of the switch S
∆Vripple Voltage ripple across each capacitor (V)
∆QC Maximum discharging value of the capacitor C
N Number of power switches with the same PIV
M Number of cascaded modules
At and ft Amplitude and frequency of the triangular carriers (Vt )
Aref and fref Amplitude and frequency of the reference waveform (Vref )
PC Conduction loss (W)
PS Switching loss (W)
PR Power loss caused by capacitor voltage ripple (W)
PS, on and PS, off Turn-on and turn-off power loss of the switch S (W)
Pout Inverter output power (W)
RS and RD ON-state resistance of the switch S and its parallel diode (Ω)
RC Capacitor internal resistance (Ω)
Req Equivalent value of the parasitic resistance in each voltage level (Ω)
R and L Resistance (Ω) and inductance (H) of the load
ton and toff Rise and fall times of the switch S (s)
fS Switching frequency (Hz)
Tj Semiconductor junction temperature (◦ C)
Tc Semiconductor case temperature (◦ C)
Ts Heat sink temperature (◦ C)
Ta Ambient temperature (◦ C)
Zth Thermal impedance between junction and case of the semiconductor
Zc Thermal impedance between semiconductor case and its heat sink
Zs Thermal impedance between heat sink and ambient

References
1. Kouro, S.; Malinowski, M.; Gopakumar, K.; Pou, J.; Franquelo, L.G.; Wu, B.; Rodriguez, J.; Perez, M.A.;
Leon, J.I. Recent Advances and Industrial Applications of Multilevel Converters. IEEE Trans. Ind. Electron.
2010, 57, 2553–2580. [CrossRef]
2. Yuan, X. Derivation of Voltage Source Multilevel Converter Topologies. IEEE Trans. Ind. Electron. 2017, 64,
966–976. [CrossRef]
3. Rodriguez, J.; Franquelo, L.G.; Kouro, S.; Leon, J.I.; Portillo, R.C.; Prats, M.A.M.; Perez, M.A. Multilevel
Converters: An Enabling Technology for High-Power Applications. Proc. IEEE 2009, 97, 1786–1817.
[CrossRef]
4. Gupta, K.K.; Ranjan, A.; Bhatnagar, P.; Kumar Sahu, L.; Jain, S. Multilevel Inverter Topologies with Reduced
Device Count: A Review. IEEE Trans. Power Electron. 2016, 31, 135–151. [CrossRef]
5. Leon, J.I.; Vazquez, S.; Franquelo, L.G. Multilevel Converters: Control and Modulation Techniques for Their
Operation and Industrial Applications. Proc. IEEE 2017, 105, 2066–2081. [CrossRef]
Energies 2019, 12, 207 15 of 15

6. Akagi, H. Multilevel Converters: Fundamental Circuits and Systems. Proc. IEEE 2017, 105, 2048–2065.
[CrossRef]
7. Wu, B.; Narimani, M. Diode-Clamped Multilevel Inverters. In High-Power Converters and AC Drives;
Wiley-IEEE Press: New York, NY, USA, 2017.
8. Khounjahan, H.; Abapour, M.; Zare, K. Switched-Capacitor Based Single Source Cascaded H-bridge
Multilevel Inverter Featuring Boosting Ability. IEEE Trans. Power Electron. 2018, 34, 1113–1124. [CrossRef]
9. Lee, S. Single-Stage Switched-Capacitor Module (S3CM) Topology for Cascaded Multilevel Inverter.
IEEE Trans. Power Electron. 2018, 33, 8204–8207. [CrossRef]
10. Choi, J.S.; Kang, F.S. Seven-Level PWM Inverter Employing Series-Connected Capacitors Paralleled to
a Single DC Voltage Source. IEEE Trans. Ind. Electron. 2015, 62, 3448–3459.
11. Hinago, Y.; Koizumi, H. A Switched-Capacitor Inverter Using Series/Parallel Conversion. IEEE Int. Symp.
Circuits Syst. 2010, 62, 3188–3191.
12. Wang, K.; Zheng, Z.; Wei, D.; Fan, B.; Li, Y. Topology and Capacitor Voltage Balancing Control of
a Symmetrical Hybrid Nine-Level Inverter for High-Speed Motor Drives. IEEE Trans. Ind. Appl. 2017,
53, 5563–5572. [CrossRef]
13. Taghvaie, A.; Adabi, J.; Rezanejad, M. A Self-Balanced Step-Up Multilevel Inverter Based on
Switched-Capacitor Structure. IEEE Trans. Power Electron. 2018, 33, 199–209. [CrossRef]
14. Lee, S.S.; Sidorov, M.; Lim, C.S.; Idris, N.R.N.; Heng, Y.E. Hybrid Cascaded Multilevel Inverter (HCMLI)
With Improved Symmetrical 4-level Submodule. IEEE Trans. Power Electron. 2018, 33, 932–935. [CrossRef]
15. Lee, S.S. A Single-Phase Single-Source 7-Level Inverter with Triple Voltage Boosting Gain. IEEE Access 2018,
6, 30005–30011. [CrossRef]
16. McGrath, B.P.; Holmes, D.G. Multicarrier PWM Strategies for Multilevel Inverters. IEEE Trans. Ind. Electron.
2002, 49, 858–867. [CrossRef]
17. Mei, J.; Xiao, B.; Shen, K.; Tolbert, L.M.; Zheng, J.Y. Modular Multilevel Inverter with new Modulation
Method and its Application to Photovoltaic Grid-Connected Generator. IEEE Trans. Power Electron. 2013, 28,
5063–5073. [CrossRef]
18. Tsunoda, A.; Hinago, Y.; Koizumi, H. Level-and Phase-Shifted PWM for Seven-Level Switched-Capacitor
Inverter Using Series/Parallel Conversion. IEEE Trans. Ind. Electron. 2014, 61, 4011–4021. [CrossRef]
19. Barzegarkhoo, R.; Moradzadeh, M.; Zamiri, E.; Kojabadi, H.M.; Blaabjerg, F. A new Boost Switched-Capacitor
Multilevel Converter with Reduced Circuit Devices. IEEE Trans. Power Electron. 2018, 33, 6738–6754.
[CrossRef]
20. Albarbar, A.; Batunlu, C. Thermal Analysis of Power Electronic Devices Used in Renewable Energy Systems;
Springer-Cham: Cham, Switzerland, 2018.
21. Ma, K.; Muñoz-Aguilar, R.S.; Rodriguez, P.; Blaabjerg, F. Thermal and Efficiency Analysis of Five-Level
Multilevel-Clamped Multilevel Converter Considering Grid Codes. IEEE Trans. Ind. Appl. 2014, 50, 415–423.
22. Lixiang, W.; McGuire, J.; Lukaszewski, R.A. Analysis of PWM Frequency Control to Improve the Lifetime of
PWM Inverter. IEEE Trans. Ind. Electron. 2011, 47, 922–929. [CrossRef]
23. Ma, K.; Bahman, A.S.; Beczkowski, S.; Blaabjerg, F. Complete Loss and Thermal Model of Power
Semiconductors Including Device Rating Information. IEEE Trans. Power Electron. 2015, 30, 2556–2569.
[CrossRef]
24. Rajapakse, A.; Gole, A.; Jayasinghe, R. An Improved Representation of FACTS Controller Semiconductor
Losses in EMTP-Type Programs Using Accurate Loss-Power Injection Into Network Solution. IEEE Trans.
Power Del. 2009, 24, 381–389. [CrossRef]
25. Tu, Q.; Xu, Z. Power Losses Evaluation for Modular Multilevel Converter with Junction Temperature
Feedback. In Proceedings of the IEEE Power and Energy Society General Meeting, Detroit, MI, USA,
24–29 July 2011; pp. 1–7.

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access
article distributed under the terms and conditions of the Creative Commons Attribution
(CC BY) license (http://creativecommons.org/licenses/by/4.0/).