Académique Documents
Professionnel Documents
Culture Documents
272430 – 1
Figure 1. Block Diagram
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1994 Order Number: 272430-002
COPYRIGHT © INTEL CORPORATION, 1995 1
80186/80188 High-Integration 16-Bit Microprocessors
CONTENTS PAGE CONTENTS PAGE
2
80186/80188
Contacts Facing Up
272430 – 2
272430 – 3
3
80186/80188
272430 – 4
4
80186/80188
NOTE:
Pin names in parentheses apply to the 80188.
5
80186/80188
6
80186/80188
NOTE:
Pin names in parentheses apply to the 80188.
7
80186/80188
PCS0 25 O Peripheral Chip Select signals 0 – 4 are active LOW when a reference is made
PCS1 27 O to the defined peripheral area (64 Kbyte I/O space). These lines are not
PCS2 28 O floated during bus HOLD. The address ranges activating PCS0 – 4 are
PCS3 29 O software programmable.
PCS4 30 O
PCS5/A1 31 O Peripheral Chip Select 5 or Latched A1 may be programmed to provide a
sixth peripheral chip select, or to provide an internally latched A1 signal. The
address range activating PCS5 is software-programmable. PCS5/A1 does
not float during bus HOLD. When programmed to provide latched A1, this pin
will retain the previously latched value during HOLD.
PCS6/A2 32 O Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select, or to provide an internally latched A2 signal.
The address range activating PCS6 is software programmable. PCS6/A2
does not float during bus HOLD. When programmed to provide latched A2,
this pin will retain the previously latched value during HOLD.
DT/R 40 O Data Transmit/Receive controls the direction of data flow through an
external data bus transceiver. When LOW, data is transferred to the
processsor. When HIGH, the processor places write data on the data bus.
DEN 39 O Data Enable is provided as a data bus transceiver output enable. DEN is
active LOW during each memory and I/O access. DEN is HIGH whenever
DT/R changes state. During RESET, DEN is driven HIGH for one clock, then
floated. DEN also floats during HOLD.
NOTE:
Pin names in parentheses apply to the 80188.
8
80186/80188
FUNCTIONAL DESCRIPTION Intel recommends the following values for crystal se-
lection parameters:
Temperature Range: 0 to 70§ C
Introduction ESR (Equivalent Series Resistance): 30X max
C0 (Shunt Capacitance of Crystal): 7.0 pf max
The following Functional Description describes the C1 (Load Capacitance): 20 pf g 2 pf
base architecture of the 80186. The 80186 is a very Drive Level: 1 mW max
high integration 16-bit microprocessor. It combines
15–20 of the most common microprocessor system
components onto one chip while providing twice the
performance of the standard 8086. The 80186 is ob-
Clock Generator
ject code compatible with the 8086/8088 microproc- The clock generator provides the 50% duty cycle
essors and adds 10 new instruction types to the processor clock for the processor. It does this by
8086/8088 instruction set. dividing the oscillator output by 2 forming the sym-
metrical clock. If an external oscillator is used, the
For more detailed information on the architecture, state of the clock generator will change on the fall-
please refer to the 80C186XL/80C188XL User’s ing edge of the oscillator signal. The CLKOUT pin
Manual. The 80186 and the 80186XL devices are provides the processor clock signal for use outside
functionally and register compatible. the device. This may be used to drive other system
components. All timings are referenced to the output
clock.
CLOCK GENERATOR
The processor provides an on-chip clock generator
for both internal and external clock generation. The
READY Synchronization
clock generator features a crystal oscillator, a divide- The processor provides both synchronous and asyn-
by-two counter, synchronous and asynchronous chronous ready inputs. In addition, the processor, as
ready inputs, and reset circuitry. part of the integrated chip-select logic, has the capa-
bility to program WAIT states for memory and
peripheral blocks.
Oscillator
The oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal. This is
RESET Logic
used as the time base for the processor. The crystal The processor provides both a RES input pin and a
frequency selected will be double the CPU clock fre- synchronized RESET output pin for use with other
quency. Use of an LC or RC circuit is not recom- system components. The RES input pin is provided
mended with this oscillator. If an external oscillator is with hysteresis in order to facilitate power-on Reset
used, it can be connected directly to the input pin X1 generation via an RC network. RESET output is
in lieu of a crystal. The output of the oscillator is not guaranteed to remain active for at least five clocks
directly available outside the processor. The recom- given a RES input of at least six clocks.
mended crystal configuration is shown in Figure 5.
Figure 5. Recommended
Crystal Configuration
9
80186/80188
Memory/Peripheral Control either memory or I/O space. Internal logic will recog-
nize control block addresses and respond to bus cy-
The processor provides ALE, RD, and WR bus con- cles. During bus cycles to internal registers, the bus
trol signals. The RD and WR signals are used to controller will signal the operation externally (i.e., the
strobe data from memory or I/O to the processor or RD, WR, status, address, data, etc., lines will be driv-
to strobe data from the processor to memory or I/O. en as in a normal bus cycle), but D15–0 (D7–0),
The ALE line provides a strobe to latch the address SRDY, and ARDY will be ignored. The base address
when it is valid. The local bus controller does not of the control block must be on an even 256-byte
provide a memory/I/O signal. If this is required, use boundary (i.e., the lower 8 bits of the base address
the S2 signal (which will require external latching), are all zeros).
make the memory and I/O spaces nonoverlapping,
or use only the integrated chip-select circuitry. The control block base address is programmed by a
16-bit relocation register contained within the control
block at offset FEH from the base address of the
Local Bus Arbitration control block. It provides the upper 12 bits of the
base address of the control block.
The processor uses a HOLD/HLDA system of local
bus exchange. This provides an asynchronous bus In addition to providing relocation information for the
exchange mechanism. This means multiple masters control block, the relocation register contains bits
utilizing the same bus can operate at separate clock which place the interrupt controller into Slave Mode,
frequencies. The processor provides a single and cause the CPU to interrupt upon encountering
HOLD/HLDA pair through which all other bus mas- ESC instructions.
ters may gain control of the local bus. External cir-
cuitry must arbitrate which external device will gain
control of the bus when there is more than one alter- Chip-Select/Ready Generation Logic
nate local bus master. When the processor relin-
quishes control of the local bus, it floats DEN, RD, The processor contains logic which provides
WR, S0–S2, LOCK, AD0–AD15 (AD0–AD7), programmable chip-select generation for both mem-
A16–A19 (A8–A19), BHE (S7), and DT/R to allow ories and peripherals. In addition, it can be pro-
another master to drive these lines directly. grammed to provide READY (or WAIT state) genera-
tion. It can also provide latched address bits A1 and
A2. The chip-select lines are active for all memory
Local Bus Controller and Reset and I/O cycles in their programmed areas, whether
they be generated by the CPU or by the integrated
During RESET the local bus controller will perform DMA unit.
the following action:
# Drive DEN, RD, and WR HIGH for one clock cy- MEMORY CHIP SELECTS
cle, then float.
The processor provides 6 memory chip select out-
NOTE: puts for 3 address areas; upper memory, lower
RD is also provided with an internal pull-up de- memory, and midrange memory. One each is provid-
vice to prevent the processor from inadvertently ed for upper memory and lower memory, while four
entering Queue Status Mode during RESET. are provided for midrange memory.
# Drive S0–S2 to the inactive state (all HIGH) and
then float. UPPER MEMORY CS
# Drive LOCK HIGH and then float.
The processor provides a chip select, called UCS,
# Float AD0–15 (AD0–AD7), A16–19 (A8–A19),
BHE (S7), DT/R. for the top of memory. The top of memory is usually
used as the system memory because after reset the
# Drive ALE LOW (ALE is never floated). processor begins executing at memory location
# Drive HLDA LOW. FFFF0H.
LOWER MEMORY CS
PERIPHERAL ARCHITECTURE
The processor provides a chip select for low memo-
All of the integrated peripherals are controlled by ry called LCS. The bottom of memory contains the
16-bit registers contained within an internal 256-byte
interrupt vector table, starting at location 00000H.
control block. The control block may be mapped into
10
10
80186/80188
The lower limit of memory defined by this chip select # Upon leaving RESET, the UCS line will be pro-
is always 0H, while the upper limit is programmable. grammed to provide chip selects to a 1K block
By programming the upper limit, the size of the with the accompanying READY control bits set at
memory block is defined. 011 to insert 3 wait states in conjunction with ex-
ternal READY (i.e., UMCS resets to FFFBH).
MID-RANGE MEMORY CS # No other chip select or READY control registers
have any predefined values after RESET. They
The processor provides four MCS lines which are will not become active until the CPU accesses
active within a user-locatable memory block. This their control registers. Both the PACS and MPCS
block can be located within the 1-Mbyte memory ad- registers must be accessed before the PCS lines
dress space exclusive of the areas defined by UCS will become active.
and LCS. Both the base address and size of this
memory block are programmable.
DMA Channels
PERIPHERAL CHIP SELECTS The DMA controller provides two independent DMA
channels. Data transfers can occur between memo-
The processor can generate chip selects for up to ry and I/O spaces (e.g., Memory to I/O) or within the
seven peripheral devices. These chip selects are ac- same space (e.g., Memory to Memory or I/O to I/O).
tive for seven contiguous blocks of 128 bytes above Data can be transferred either in bytes or in words
a programmable base address. The base address (80186 only) to or from even or odd addresses.
may be located in either memory or I/O space. Sev- Each DMA channel maintains both a 20-bit source
en CS lines called PCS0 –6 are generated by the and destination pointer which can be optionally in-
processor. PCS5 and PCS6 can also be pro- cremented or decremented after each data transfer
grammed to provide latched address bits A1 and A2. (by one or two depending on byte or word transfers).
If so programmed, they cannot be used as peripher- Each data transfer consumes 2 bus cycles (a mini-
al selects. These outputs can be connected directly mum of 8 clocks), one cycle to fetch data and the
to the A0 and A1 pins used for selecting internal other to store data. This provides a maximum data
registers of 8-bit peripheral chips. transfer rate of 1.25 Mword/sec or 2.5 Mbytes/sec
at 10 MHz (half of this rate for the 80188).
READY GENERATION LOGIC
DMA CHANNELS AND RESET
The processor can generate a READY signal inter-
nally for each of the memory or peripheral CS lines. Upon RESET, the DMA channels will perform the
The number of WAIT states to be inserted for each following actions:
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for # The Start/Stop bit for each channel will be reset
which the chip select is active. In addition, the proc- to STOP.
essor may be programmed to either ignore external # Any transfer in progress is aborted.
READY for each chip-select range individually or to
factor external READY with the integrated ready
generator. Timers
The processor provides three internal 16-bit pro-
CHIP SELECT/READY LOGIC AND RESET grammable timers. Two of these are highly flexible
and are connected to four external pins (2 per timer).
Upon RESET, the Chip-Select/Ready Logic will per-
They can be used to count external events, time ex-
form the following actions:
ternal events, generate nonrepetitive waveforms,
# All chip-select outputs will be driven HIGH. etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time de-
lay applications. In addition, the third timer can be
used as a prescaler to the other two, or as a DMA
request source.
11
11
80186/80188
12
12
80186/80188
272430 – 6
NOTE:
Pin names in parenthesis apply to 80188.
(1) BHE does not exist on the 80188, this is only required for a 16-bit data bus.
13
13
80186/80188
272430 – 7
NOTE:
Pin names in parentheses apply to 80188.
(1) BHE does not exist on the 80188, this is only required for a 16-bit data bus.
14
14
80186/80188
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature under Bias ÀÀÀÀÀÀ0§ C to 70§ C
*WARNING: Stressing the device beyond the ‘‘Absolute
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Maximum Ratings’’ may cause permanent damage.
Voltage on any Pin with These are stress ratings only. Operation beyond the
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 1.0V to a 7V ‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3W may affect device reliability.
15
15
80186/80188
16
16
80186/80188
17
17
80186/80188
18
18
80186/80188
WAVEFORMS
272430 – 8
NOTE:
Pin names in parentheses apply to the 80188.
19
19
80186/80188
WAVEFORMS (Continued)
NOTES: 272430 – 9
1. INTA occurs one clock later in slave mode.
2. Status inactive just prior to T4.
3. If latched A1 and A2 are selected instead of PCS5 and PCS6, only TCLCSV is applicable.
4. Pin names in parentheses apply to the 80188.
20
20
80186/80188
WAVEFORMS (Continued)
272430 – 10
272430 – 11
272430 – 12
21
21
80186/80188
WAVEFORMS (Continued)
272430 – 13
272430 – 14
22
22
80186/80188
WAVEFORMS (Continued)
READY TIMING
272430 – 15
23
23
80186/80188
272430 – 16
NOTE:
Pin names in parentheses apply to the 80188.
24
24
80186/80188
WAVEFORMS (Continued)
272430 – 17
25
25
80186/80188
26
26
80186/80188
Immediate to register/memory 1100011w mod 000 r/m data data if w e 1 12/13 12/13 8/16-bit
PUSH e Push:
Memory 11111111 mod 1 1 0 r/m 16 20
Register 0 1 0 1 0 reg 10 14
Register 0 1 0 1 1 reg 10 14
XCHG e Exchange:
Register/memory with register 1000011w mod reg r/m 4/17 4/17*
IN e Input from:
Fixed port 1110010w port 10 10*
27
27
80186/80188
SS 00110110 2 2
DS 00111110 2 2
ES 00100110 2 2
ARITHMETIC
ADD e Add:
Reg/memory with register to either 000000dw mod reg r/m 3/10 3/10*
INC e Increment:
Register/memory 1111111w mod 0 0 0 r/m 3/15 3/15*
Register 0 1 0 0 0 reg 3 3
SUB e Subtract:
Reg/memory and register to either 001010dw mod reg r/m 3/10 3/10*
Immediate from register/memory 100000sw mod 1 0 1 r/m data data if s w e 01 4/16 4/16*
Immediate from register/memory 100000sw mod 0 1 1 r/m data data if s w e 01 4/16 4/16*
Register 0 1 0 0 1 reg 3 3
CMP e Compare:
Register/memory with register 0011101w mod reg r/m 3/10 3/10*
Immediate with register/memory 100000sw mod 1 1 1 r/m data data if s w e 01 3/10 3/10*
28
28
80186/80188
IMUL e Integer Immediate multiply 011010s1 mod reg r/m data data if s e 0 22–25/ 22–25/
(signed) 29–32 29–32
LOGIC
Shift/Rotate Instructions:
Register/Memory by 1 1101000w mod TTT r/m 2/15 2/15
TTT Instruction
000 ROL
001 ROR
010 RCL
011 RCR
1 0 0 SHL/SAL
101 SHR
111 SAR
AND e And:
Reg/memory and register to either 001000dw mod reg r/m 3/10 3/10*
Immediate data and register/memory 1111011w mod 0 0 0 r/m data data if w e 1 4/10 4/10*
Immediate data and accumulator 1010100w data data if w e 1 3/4 3/4 8/16-bit
OR e Or:
Reg/memory and register to either 000010dw mod reg r/m 3/10 3/10*
29
29
80186/80188
CONTROL TRANSFER
CALL e Call:
Direct within segment 11101000 disp-low disp-high 15 19
segment selector
segment selector
30
30
80186/80188
Intersegment 11001011 22 30
INT e Interrupt:
BOUND e Detect value out of range 01100010 mod reg r/m 33–35 33–35
31
31
80186/80188
32
32
80186/80188
REVISION HISTORY
This data sheet replaces the following data sheets:
210706-011 80188
210451-011 80186
33
33