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EC6404 LINEAR INTEGRATED CIRCUITS


SYLLABUS COPY
UNIT I BASICS OF OPERATIONAL AMPLIFIERS
Current mirror and current sources, Current sources as active loads, Voltage
sources, Voltage References, BJT Differential amplifier with active loads, Basic
information about op-amps – Ideal Operational Amplifier - General operational
amplifier stages -and internal circuit diagrams of IC 741, DC and AC performance
characteristics, slew rate, Open and closed loop configurations.
UNIT II APPLICATIONS OF OPERATIONAL AMPLIFIERS
Sign Changer, Scale Changer, Phase Shift Circuits, Voltage Follower, V-to-I

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and I-to-V converters, adder, subtractor, Instrumentation amplifier, Integrator,
Differentiator, Logarithmic amplifier, Antilogarithmic amplifier, Comparators, Schmitt

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trigger, Precision rectifier, peak detector, clipper and clamper, Low-pass, high-pass

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and band-pass Butterworth filters.

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UNIT III ANALOG MULTIPLIER AND PLL
Analog Multiplier using Emitter Coupled Transistor Pair - Gilbert Multiplier cell –

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Variable transconductance technique, analog multiplier ICs and their applications,
Operation of the basic PLL, Closed loop analysis, Voltage controlled oscillator,

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Monolithic PLL IC 565, application of PLL for AM detection, FM detection, FSK
modulation and demodulation and Frequency synthesizing.

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UNIT IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS

.
Analog and Digital Data Conversions, D/A converter – specifications - weighted
resistor type, R-2R Ladder type, Voltage Mode and Current-Mode R 2R Ladder
types - switches for D/A converters, high speed sample-and-hold circuits, A/D
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Converters – specifications - Flash type - Successive Approximation type - Single
Slope type – Dual Slope type - A/D Converter using Voltage-to-Time Conversion -
Over-sampling A/D Converters.
UNIT V WAVEFORM GENERATORS AND SPECIAL FUNCTION ICS
Sine-wave generators, Multivibrators and Triangular wave generator, Saw-tooth
wave generator, ICL8038 function generator, Timer IC 555, IC Voltage regulators –
Three terminal fixed and adjustable voltage regulators - IC 723 general purpose
regulator - Monolithic switching regulator, Switched capacitor filter IC MF10,
Frequency to Voltage and Voltage to Frequency converters, Audio Power amplifier,
Video Amplifier, Isolation Amplifier, Opto-couplers and fibre optic IC.
2

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TABLE OF CONTENTS
S.No TITLE PAGE NO
a Aim and Objective of the subject 5
b Detailed Lesson Plan 6
UNIT 1- BASICS OF OPERATIONAL AMPLIFIERS
PART A 9
PART B
1 Current Sources 13
2 DC Characteristics 26
3 AC Characteristics 32

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4.i Slew rate 49

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4.ii Open loop and closed loop configurations 52
5
6.i
6.ii asy
Voltage References

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General Amplifier Stages
BJT Differential Amplifier

PART C

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61
64
67
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UNIT 2 - APPLICATIONS OF OPERATIONAL AMPLIFIERS
PART A
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PART B
1 Instrumentation Amplifier 78
2
3
Schmitt Trigger
Log and Antilog Amplifier
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83
4 Differentiator and Integrator 87
5 Operational Amplifier using Diodes 98
6.i V to I and I to V Convertors 107
6.ii Adder-Subtractor 109
7 Explain the construction and working of active filters. 118
127
PART C
UNIT 3 - ANALOG MULTIPLIER AND PLL
PART A 135
PART B

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1 VCO Voltage Control Oscillator 140


2 Monolithic PLL IC 565 143
3 PLL Applications 149
4 Analog Multiplier and its Applications 157
5 (i)Emitter coupled Transistor-Gilbert Multiplier cell- 164
(ii)Variable Transconductance Technique
PART C 168
UNIT 4 - ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS
PART A 171
PART B

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1
2
DAC
Flash type and Successive Approximation A/D
174
184

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3
4.i
4.ii
Converters

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Single Slope and Dual Slope A/D Converters
Sample and Hold circuits

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Over sampling A/D Converters

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195
197
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5.i Specifications 198
5.ii
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A/D Converter using Voltage to Time Conversion
PART C
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202

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UNIT 5 - WAVEFORM GENERATORS AND SPECIAL FUNCTION ICS


PART A 205

1 Multivibrator using Op-Amp


PART B
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2 Multivibrator using IC555 Timer 212
3 IC723 General Purpose Regulator 220
4 Opto-Coupler and Fiber optic IC 234
5 Triangular and Saw-tooth or Sinewave Generators 238
6 Frequency to Voltage and Voltage to Frequency 245
Converters
7 Audio Amplifier LM380 248
PART C 254
Previous years‟ University Question Papers 260

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AIM AND OBJECTIVE OF THE SUBJECT


Aim:
To discuss the construction and operation of the operational amplifiers and to learn
the theory and applications of DAC, ADC and analog multipliers.
Objectives:
 To introduce the basic building blocks of linear integrated circuits.
 To learn the linear and non-linear applications of operational amplifiers.
 To introduce the theory and applications of analog multipliers and PLL.
 To learn the theory of ADC and DAC.
 To introduce the concepts of waveform generation and introduce some

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3. Industry Connectivity and Latest Developments

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Industry Connectivity:

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 The following companies (Industries) are connectivity to Linear Integrated

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Circuits: Vi micro systems, Arasan Chips, HCL Hardware

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.Latest Developments:

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 Fibre optics were introduced almost in all telephone connections.
 Increased operating speeds in computer.

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 Reduction in power consumption in electronic devices.


4. Industrial Visit (Planned if any)
Date: 25.02.2017
Industry: Arasan Chip Systems – Thoothukudi.
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DETAILED LESSON PLAN

Name of the Subject & Code: LINEAR INTEGRATED CIRCUITS & EC6404
Name of the Faculty: Mr. C. Susil Kumar, ASP/ECE, SCADCET
Mrs. J. Nirmal Jothi AP/ECE, SCADCET
Mr. K. John Samuel Raj AP/ECE, SCADCET
Sem / Yr / Branch : IV / II / ECE

TEXT BOOKS:
1. D.Roy Choudhry, Shail Jain, ―Linear Integrated Circuits‖, New Age International

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Pvt. Ltd., 2000. (Copies Available in Library: Yes)
2. Sergio Franco, ―Design with Operational Amplifiers and Analog Integrated

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Circuits‖, 3rd Edition, Tata Mc Graw-Hill, 2007. (Copies Available in Library: Yes)

REFERENCES:
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1. Ramakant A. Gayakwad, ―OP-AMP and Linear ICs‖, 4th Edition, Prentice Hall /

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Pearson Education, 2001. (Copies Available in Library: Yes)
2. Robert F.Coughlin, Frederick F.Driscoll, ―Operational Amplifiers and Linear

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Integrated Circuits‖, Sixth Edition, PHI, 2001. (Copies Available in Library: Yes)
3. B.S.Sonde, ―System design using Integrated Circuits‖ , 2nd Edition, New Age Pub,

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2001 (Copies Available in Library: Yes)

International, 2005. (Copies Available in Library: Yes) .


4. Gray and Meyer, ―Analysis and Design of Analog Integrated Circuits‖, Wiley

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5. Michael Jacob, ―Applications and Design with Analog Integrated Circuits‖, Prentice
Hall of India, 1996. (Copies Available in Library: Yes)
6. William D.Stanley, ―Operational Amplifiers with Linear Integrated Circuits‖,
Pearson Education, 2004. (Copies Available in Library: Yes)
7. S.Salivahanan & V.S. Kanchana Bhaskaran, ―Linear Integrated Circuits‖, TMH,
2008. (Copies Available in Library: Yes)

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Hours Cumulative Page


S.NO UNIT TOPICS Planned Hours Text
No
UNIT 1 - BASICS OF OPERATIONAL AMPLIFIERS
T1,
1 Current mirror ,Current sources 2 2 55-76
R7
T1,
2 Current sources as active loads 1 3 77-79
R7
Voltage References, BJT Differential
3 1 4 R7,T1 50-65
amplifier with active loads
T1,
4 Basic information about op-amps 1 5 37-50
I R2
5 Internal circuit diagrams of IC 741 2 7 T1 82-89
T1,
6 DC performance 1 8 104-111
R1

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7 AC performance characteristics, slew rate 1 9
T1,
R1
111-127

8
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Open and closed loop configurations 2 11 T1,R1 42-50

10
Circuits
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UNIT 2 - APPLICATIONS OF OPERATIONAL AMPLIFIERS
Sign Changer, Scale Changer, Phase Shift

Voltage follower , V-to-I and I-to-V


converters
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1

1
12

13
T1,R1 42-49

T1, R1
49-50,
146-147
A
11 Adder, subtractor, Instrumentation amplifier 1 14 T1, R1 135-144

12

13
Integrator, Differentiator
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Logarithmic amplifier, Antilogarithmic
amplifier eer
1

1
15

16
T1,R1 164-175

T1 155-159

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II
14 Comparators, Schmitt trigger 2 18 T1,R1 207-216

15

16
Precision rectifier

peak detector, clipper and clamper


1

1
19

20
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T1,R2 148-150

T1, R2 151-153

17 Low-pass Butterworth filters 1 21 T1,R1 262-271

18 high-pass and band-pass Butterworth filters 1 22 T1,R1 271-277


UNIT 3 - ANALOG MULTIPLIER AND PLL
Analog Multiplier using Emitter Coupled T2,
19 1 23 615-616
Transistor Pair R7
T2,
20 Gilbert Multiplier cell 2 25 617-621
R7
III T2,
21 Variable trans conductance technique 1 26 616-617
R7
22 Analog multiplier ICs and their applications 1 27 T2 622-624
Operation of the basic PLL, Closed loop T1,
23 1 28 327-333
analysis R1

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T1,
24 Voltage controlled oscillator 1 29 334-337
R1
T1,
25 Monolithic PLL IC 565 1 30 337-342
R1
Application of PLL for AM detection, FM
T1,
26 detection, FSK modulation and 1 342-345
31 R1
demodulation, Frequency synthesizing.
UNIT 4 - ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS
Analog and Digital Data Conversions, D/A 348-349,
27 1 32 T1,R2
converter – specifications 366-368
28 Weighted resistor type, R-2R Ladder type 1 33 T1,R2 349-354
Voltage Mode and Current-Mode R - 2R
29 2 35 T2,R2 570-572
Ladder types

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30

31
IV
Switches for D/A converters

High speed sample-and-hold circuits


1

1
36

37
T2

T2
572-574

574-576

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A/D Converters – specifications - Flash
32

33

34
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type - Successive Approximation type

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Single Slope type – Dual Slope type
A/D Converter using Voltage –to - Time

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Conversion - Over-sampling A/D

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1
1

T2 595-599
38

39
T1,R2 357-363

T1 363-366
A
40
Converters
UNIT 5 - WAVEFORM GENERATORS AND SPECIAL FUNCTION ICS
35 Sine-wave generators, Multivibrators
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Triangular wave generator, Saw-tooth wave
1 41
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T1,R2
222-228,
216-220

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36 1 42 T1,T2 220-222
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generator
37 ICL8038 function generator 1 43 T1 229-232

38 Timer IC 555
IC Voltage regulators – Three terminal fixed
1 .
44
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T1,R2 311-324

39 1 45 T1,R2 241-248
and adjustable voltage regulators
IC 723 general purpose regulator,
40 V 1 46 T1 248-255
Monolithic switching regulator
288-293,
41 Switched capacitor filter IC MF10 1 47 T1,R1
298-300
Frequency to Voltage and Voltage to
42 1 48 T1,R1 180-184
Frequency converters
43 Audio Power amplifier, Isolation Amplifier 1 49 T1,R1 188-194

44 Video Amplifier 1 50 T1 194-196

45 Opto-couplers and fiber optic IC 1 51 T1 198-204

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UNIT-1

BASICS OF OPERATIONAL AMPLIFIERS


2-MARKS
1. What is an integrated circuit? [APR 10]
The Integrated Circuit or IC is a miniature, low cost electronic circuit
consisting of active and passive components that are irreparably joined together
on a single crystal chip of silicon.

2. State the limitations of discrete circuits. [APR 13]


i. Large size.

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iii. High cost

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iv. High power consumption.

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3. State the advantages of integrated circuits over discrete components.

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[DEC 13, APR 14, DEC 14]
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i. Practically size of an IC is thousands of times smaller than the discrete

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circuits.
ii. ICs operate at low voltages
iii. Low cost eer
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iv. Low power consumption.

4. What is current mirror? [APR 10]


OR
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Define current mirror with magnification. [DEC 11]
The circuit in which the output current is forced to equal to the input current is
called current mirror circuit. In a current mirror circuit, the output current is the
mirror image of input current.

5. Define slew rate. [MAY16,May15 ]


The slew rate is defined as the maximum rate of change of output voltage
caused by a step input voltage. An ideal slew rate is infinite which means that op-

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amp‘s output voltage should change instantaneously in response to input step


voltage.

6. Why are active loads preferred than passive loads in the input stage of an
operational amplifier? [DEC 10, Dec 16]
The active loads are realized using current source in place of the passive load
in the collector arm of differential amplifier to make it possible to achieve high
voltage gain without requiring large power supply voltage.

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7. Compare the performance of inverting and non-inverting operational

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amplifier configurations. [DEC 10]

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Compared to the inverting amplifier, the input resistance of the non-inverting

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amplifier is extremely large (=∞) as the op-amp draws negligible current from the
signal source.

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8. Why is frequency compensation required in operational amplifier? [DEC 10]

1. Large bandwidth
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Frequency compensation is required, when we need

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2. Low closed loop gain

9. Define CMRR of an OP-AMP. [APR 11, DEC 10, APR 13, May15]
.
The ratio of differential gain and the common mode gain is termed as
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Common Mode Rejection Ratio.

Ad = differential gain
Ac = common mode gain

10. What are the two requirements to be met for a good current source? [APR 12]
i. Output current Io should not be dependent upon β
ii. Output resistance should be very high

10

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11. List the various methods of realizing high i/p resistance in a differential
amplifier. [APR 12]
i. Darlington pair
ii. Fabricate a FET differential pair as input stage

12. Define offset voltage of an operational amplifier. [DEC 13]


A small voltage applied to the input terminals to make the output voltage as
zero when the two input terminals are grounded is called input offset voltage.

13. What is meant by Monolithic IC? [DEC 14]

ww A monolithic circuit means a circuit fabricated from a single stone or a single


crystal. Monolithic is from a Greek word ‗Monos‘ meaning ‗Single‘&‗lithos‘

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meaning ‗stone‘. Monolithic ICs are made in a single piece of single crystal
silicon.

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14. List the characteristics of ideal op-amp and draw its equivalent circuit?

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[MAY 15, Nov 16, MAY 2016]
Ideal op-amp:

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Characteristics of ideal op-amp:


Open loop voltage gain AOL = ∞
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Input impedance Ri = ∞
Output impedance Ro = 0
Bandwidth BW = ∞
Zero offset Vo = 0 When V1 = V2 = 0
Equivalent circuit:

11

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15. Define the following parameters as applied to an op-amp: (Dec15)


i) Input bias current
Input bias current IB is the average of the currents that flow into the inverting and
non-inverting input erminals of the op-amp.
i.e. IB = (IB1+IB2)/2
ii) Input offset current
The algebraic difference between the current into the inverting and non-inverting
terminals is referred to as input offset current Iio. Mathematically it is represented as
Iio = |IB - IB |
Where

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I B+is the current into the non-inverting input terminals. IB- is the current into the
inverting input terminals.

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iii) Input offset voltage

zero volts.
iv) P.S.R.R

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This is the voltage required to be amplified at the input for making output voltage to

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Power Supply Rejection Ratio (PSRR) is the ability of an amplifier to maintain its
output voltage as its

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DC power-supply voltage is varied. PSRR = (change in Vcc)/(change in Vout)

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Part B
1. Explain Current source (Current mirror) in detail.

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2. Explain the DC characteristics of Operational Amplifier.


DC Characteristics of op-amp:
An ideal op-amp draws no current from the source and its response is also
independent of temperature. Current is taken from the source into the op-amp
inputs. Also the two inputs respond differently to current and voltage due to
mismatch in transistor. A real op-amp also shifts its operation with
temperature.These non-ideal dc characteristics that add error components to the
dc output voltage are
Input bias current
Input offset current

ww Input offset voltage


Thermal drift

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Input bias current:

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The op-amp‗s input is differential amplifier, which may be made of BJT or

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FET. In an ideal op-amp, we assumed that no current is drawn from the input
terminals.
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Practically, input terminals do conduct a small value of dc current to bias

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the input transistors. The base currents entering into the inverting and non-

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inverting terminals are IB-& IB+ respectively shown in fig.

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Fig:Input Bias Current
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Even though both the transistors are identical, IB- and IB+ are not exactly
equal due to internal imbalance between the two inputs. Manufacturers specify
the input bias current IB as the average value of the base currents entering into
the terminals of an op-amp. So

For 741, a bipolar op-amp, the bias current is 500nA or less. The FET
input of op-amp will have bias currents as low as 50pA at room temperature.
Consider the basic inverting amplifier as

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Fig:Inverting Amplifier with bias currents


If input voltage Vi = 0V. The output Voltage Vo should also be 0 but for IB =
500nA
We find that the output voltage is offset by Op-amp with a 1M feedback resistor

ww Vo = 500nA x 1M = 500mV
The output is driven to 500mV with zero input, because of the bias

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currents. In application where the signal levels are measured in mV, this is totally

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unacceptable. This can be compensated by a compensation resistor R comp has

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been added between the non-inverting input terminal and ground as shown in the
figure below.
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Fig: Bias compensated circuit
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Current IB+ flowing through the compensating resistor R comp, then by KVL we get,
-V1+0+V2-Vo = 0 (or)
Vo = V2 – V1 ----- ---- (1)
By selecting proper value of Rcomp, V2 can be cancelled with V1 and the Vo = 0.
The value of
Rcomp is derived as
V1 = IB+Rcomp (or)
IB+ = V1/Rcomp ------------------------ (2)

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The node ‗a‘ is at voltage (-V1). Because the voltage at the non-inverting input
terminal is (-V1). So with Vi = 0 we get,
I1 = V1/R1 ------------------------ (3)
I2 = V2/Rf ------------------------ (4)
For compensation, Vo should equal to zero (Vo = 0, Vi = 0). i.e. from equation (3)
V2 = V1. So that,
I2 = V1/Rf ——> (5)
KCL at node ‗a‘ gives,
IB- = I2 + I1 = (V1/Rf ) +(V1/R1) = V1(R1+Rf)/R1Rf -------------------
----- (5)

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Assume IB- = IB+ and using equation (2) & (5) we get
V1 (R1+Rf)/R1Rf = V1/Rcomp

w.E Rcomp = R1 || Rf ------------------------ (6)

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i.e. to compensate for bias current, the compensating resistor, Rcomp should be

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equal to the parallel combination of resistor R1 and Rf.
Input offset current:

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Bias current compensation will work if both bias currents I B+ and IB- are
equal.
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Since the input transistor cannot be made identical. There will always be
some small
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difference between IB+ and IB-. This difference is called the offset current
|Ios | = IB+-IB------------------------- (7)
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Offset current Ios for BJT op-amp is 200nA and for FET op-amp is 10pA. Even
with bias
current compensation, offset current will produce an output voltage when V i = 0.
e
V1 = IB+ Rcomp ------------------------ (11)
I1 = V1/R1------------------------ (12)
KCL at node a gives,
= Rcomp/ R1)

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To find output offset voltage V0 when input voltage Vi=0.If Rf=1Mohm,


V0=1M x 200nA=200mV
The offset current can be minimized by keeping feedback resistance small.

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Fig: Inverting amplifier with T-feedback network

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Unfortunately to obtain high input impedance, R1 must be kept large.
R1 large, the feedback resistor Rf must also be high. So as to obtain
reasonable gain.
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The T-feedback network is a good solution. This will allow large feedback

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resistance, while keeping the resistance to ground low (in dotted line).
The T-network provides a feedback signal as if the network were a single

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feedback resistor.
By T to Π conversion,
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To design T- network first pick Rt<<Rf/2 and calculate
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Input offset voltage:
Inspite of the use of the above compensating techniques, it is found that
the output voltage may still not be zero with zero input voltage [V o ≠ 0 with Vi= 0].
This is due to unavoidable imbalances inside the op-amp and one may have to
apply a small voltage at the input terminal to make output (V o) = 0.This voltage is
called input offset voltage Vos. This is the voltage required to be applied at the
input for making output voltage to zero (Vo = 0).

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D
Let us determine the Vos on the output of inverting and non-inverting amplifier. If

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Vi = 0 (Fig (b) and (c)) become the same as in figure (d).
The voltage at (-) input terminal is V2=(R1/R1+Rf)V0

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V0=(1+(Rf/R1)V2

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Since Vios=
Vi = 0,Vios =V2
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Therefore V0=(1+(Rf/R1) Vios

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Total output offset voltage:

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The total output offset voltage VOT could be either more or less than the
offset voltage produced at the output due to input bias current (I B) or input offset
voltage alone(Vos). This is because IB and Vos could be either positive or negative
with respect to ground. Therefore the maximum offset voltage at the output of an
e
inverting and non-inverting amplifier (figure b, c) without any compensation
technique used is given by many op amps provide offset compensation pins to
nullify the offset voltage. A 10K potentiometer is placed across offset null pins
1&5. The wipes connected to the negative supply at pin 4. The position of the
wipes is adjusted to nullify the offset voltage.When the given (below) op-amps
does not have these offset null pins, external balancing techniques are used.

With Rcomp, the total output offset voltage

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Fig: Compensation circuit for Offset Voltage

ww
w.E
asy D En
Fig: Balancing circuit for inverting amplifier
A
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Thermal drift:
Fig:Balancing circuit for non-inverting amplifier e
Bias current, offset current, and offset voltage change with temperature. A
circuit carefully nulled at 25ºC may not remain. So when the temperature rises to
35ºC. This is called drift. Offset current drift is expressed in nA/ºC. These indicate
the change in offset for each degree Celsius change in temperature.
Techniques to avoid drift: Careful printed circuit board layout must be used to
keep op-amps away from source of heat. Forced air cooling may be used to
stabilize the ambient temperature.

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3. Explain the AC characteristics of Operational Amplifier.


AC Characteristics:

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4. i) Explain Slew Rate in detail.

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4. ii) Explain the Open loop configuration and Closed Loop Configuration of
operational amplifier in detail. (16)
Open – loop op-amp Configuration:
The term open-loop indicates that no feedback in any form is fed to the input from
the output. When connected in open – loop the op-amp functions as a very high
gain amplifier. There are three open – loop configurations of op-amp namely,
1. Differential amplifier
2. Inverting amplifier
3. Non-inverting amplifier
The above classification is made based on the number of inputs used and the

ww
terminal to which the input is applied. The op-amp amplifies both ac and dc input
signals. Thus, the input signals can be either ac or dc voltage.

w.E
Loop Differential Amplifier:

asy D
In this configuration, the inputs are applied to both the inverting and the
non inverting

En
A
input terminals of the op-amp and it amplifies the difference between the two

gi
input voltages. Figure shows the open-loop differential amplifier configuration.

nee
The input voltages are represented by Vi1 and Vi2. The source resistance

rin
Ri1 and Ri2 are negligibly small in comparison with the very high input resistance
SC

offered by the op-amp, and thus the voltage drop across these source

g.n
resistances is assumed to be zero. The output voltage V 0 is given by V0 = A (Vi1 –
Vi2)
where A is the large signal voltage gain. Thus the output voltage is equal
to the voltage gain A times the difference between the two input voltages. This is
e
the reason why this configuration is called a differential amplifier. In open – loop
configurations, the large signal voltage gain A is also called open-loop gain A.

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Fig: Open loop differential amplifier


Inverting amplifier:

ww
In this configuration the input signal is applied to the inverting input terminal of the
op- amp and the non-inverting input terminal is connected to the ground. Figure

w.E
shows the circuit of an open– loop inverting amplifier. The output voltage is 180 0

D
out of phase with respect to the input and hence, the output voltage V 0 is given

asy
by, V0 = -AVi. Thus, in an inverting amplifier, the input signal is amplified by the

En
open-loop gain A and in phase shifted by 1800
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Non-inverting Amplifier:
Figure shows the open – loop non- inverting amplifier. The input signal is applied
to the non-inverting input terminal of the op-amp and the inverting input terminal
is connected to the ground. The input signal is amplified by the open – loop gain
A and the output is in-phase with input signal. V0 = AVi

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Fig: Open loop non-inverting amplifier


In all the above open-loop configurations, only very small values of input

ww
voltages can be applied. Even for voltages levels slightly greater than zero, the
output is driven into saturation, which is observed from the ideal transfer

w.E
characteristics of op-amp shown in figure. Thus, when operated in the open-loop

D
configuration, the output of the op-amp is either in negative or positive saturation,

asy
or switches between positive and negative saturation levels. This prevents the
use of open – loop configuration of op-amps in linear applications.

En
A
gi
Limitations of Open – loop Op – amp configuration:

nee
Firstly, in the open – loop configurations, clipping of the output waveform
can occur when the output voltage exceeds the saturation level of op-amp. This

rin
SC

is due to the very high open – loop gain of the op-amp. This feature actually

g.n
makes it possible to amplify very low frequency signal of the order of microvolt or
even less, and the amplification can be achieved accurately without any
distortion. However, signals of such magnitudes are susceptible to noise and the
amplification for that application is almost impossible to obtain in the laboratory.
e
Secondly, the open – loop gain of the op – amp is not a constant and it
varies with changing temperature and variations in power supply. Also, the
bandwidth of most of the open- loop op amps is negligibly small. This makes the
open – loop configuration of op-amp unsuitable for ac applications. The open –
loop bandwidth of the widely used 741 IC is approximately 5Hz. But in almost all
ac applications, the bandwidth requirement is much larger than this.
For the reason stated, the open – loop op-amp is generally not used in
linear applications. However, the open – loop op amp configurations find use in

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certain non – linear applications such as comparators, square wave generators


and astable multivibrators.

Closed – loop op-amp configuration:


The op-amp can be effectively utilized in linear applications by providing a
feedback from the output to the input, either directly or through another network.
If the signal feedback is out- of phase by 1800 with respect to the input, then the
feedback is referred to as negative feedback or degenerative feedback.
Conversely, if the feedback signal is in phase with that at the input, then the
feedback is referred to as positive feedback or regenerative feedback.

ww An op – amp that uses feedback is called a closed – loop amplifier. The


most commonly used closed – loop amplifier configurations are 1. Inverting

w.E
amplifier (Voltage shunt amplifier) 2. Non- Inverting amplifier (Voltage – series
Amplifier)

Inverting Amplifier:
asy D En
A
The inverting amplifier is shown in figure and its alternate circuit

gi
arrangement is shown in figure, with the circuit redrawn in a different way to

nee
illustrate how the voltage shunt feedback is achieved. The input signal drives the
inverting input of the op – amp through resistor R1.
rin
SC

The op – amp has an open – loop gain of A, so that the output signal is

g.n
much larger than the error voltage. Because of the phase inversion, the output
signal is 1800 out – of – phase with the input signal. This means that the
feedback signal opposes the input signal and the feedback is negative or
degenerative.
e
Practical Inverting amplifier:
The practical inverting amplifier has finite value of input resistance and
input current, its open voltage gain A0 is less than infinity and its output
resistance R0 is not zero, as against
the ideal inverting amplifier with finite input resistance, infinite open – loop voltage
gain and zero output resistance respectively.
Figure shows the low frequency equivalent circuit model of a practical
inverting amplifier. This circuit can be simplified using the Thevenin‗s equivalent
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circuit shown in figure. The signal source Vi and the resistors R1 and Ri are
replaced by their Thevenin‗s equivalent values. The closed –loop gain AV and the
input impedance Rif are calculated as follows.
The input impedance of the op- amp is normally much larger than the input
resistance R1.

Non –Inverting Amplifier:


The non – inverting Amplifier with negative feedback is shown in figure.
The input signal drives the non – inverting input of op-amp. The op-amp provides
an internal gain A. The external resistors R 1 and Rf form the feedback voltage

ww
divider circuit with an attenuation factor of β.
Since the feedback voltage is at the inverting input, it opposes the input

w.E
voltage at the non – inverting input terminals, and hence the feedback is negative

D
or degenerative.The differential voltage Vid at the input of the op-amp is zero,

asy
because node A is at the same voltage as that of the non- inverting input

En
terminal. As shown in figure, Rf and R1 form a potential divider. Therefore,
A
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Fig: Non – inverting Amplifier
Closed Loop Non – Inverting Amplifier
The input resistance of the op – amp is extremely large (approximately
infinity,) since the op –amp draws negligible current from the input signal.

Practical Non –inverting amplifier:


The equivalent circuit of a non- inverting amplifier using the low frequency
model is shown below in figure. Using Kirchhoff‘s current law at node a,

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Fig: Equivalent circuit of a non-inverting amplifier

ww
w.E The difference volt is equal to the input volt minus the f/b volt. (or) The

D
feedback volt always opposes the input volt (or out of phase by 180 0 with respect

asy
to the input voltage) hence the feedback is said to be negative.It will be
performed by computing
En
A
1. Closed loop volt gain
2. Input and output resistance
3. Bandwidth
gi nee
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5. Explain the stages of General Operational Amplifier and internal circuit


diagrams of IC 741.
g.n
(16)
(May/June2014)
An operational amplifier generally consists of three stages, namely
1. A differential amplifier
e
2. Additional amplifier stages to provide the required voltage gain and dc
level shifting.
3. An emitter-follower or source follower output stage to provide current
gain and low output resistance.
A low-frequency or dc gain of approximately 104 is desired for a general
purpose op-amp and hence, the use of active load is preferred in the internal
circuitry of op-amp.The output voltage is required to be at ground, when the
differential input voltages are zero, and this necessitates the use of dual polarity

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supply voltage. Since the output resistance of op-amp is required to be low, a


complementary push-pull emitter – follower or source follower output stage is
employed. Moreover, as the input bias currents are to be very small of the order
of pico amperes, an FET input stage is normally preferred.

Input stage:
The input differential amplifier stage uses p-channel JFETs M1 and M2. It
employs a three transistor active load formed by Q3, Q4, and Q5. The bias
current for the stage is provided by a two-transistor current source using PNP
transistors Q6 and Q7. Resistor R1 increases the output resistance seen

ww
looking into the collector of Q4 as indicated by R 04. This is necessary to provide
bias current stability against the transistor parameter variations. Resistor R 2

w.E
establishes a definite bias current through Q5. A single ended output is taken out
at the collector of Q4.

D
asy
MOSFET‗s are used in place of JFETs with additional devices in the circuit

En
to prevent any damage for the gate oxide due to electrostatic discharges.
A
Gain stage:
gi nee
The second stage or the gain stage uses Darlington transistor pair formed

rin
by Q8 and Q9 as shown in figure. The transistor Q8 is connected as an emitter
SC

follower, providing large input resistance. Therefore, it minimizes the loading

g.n
effect on the input differential amplifier stage. The transistor Q9 provides an
additional gain and Q10 acts as an active load for this stage. The current mirror
formed by Q7 and Q10 establishes the bias current for Q9. The VBE drop across
Q9 and drop across R5 constitute the voltage drop across R4, and this voltage
e
sets the current through Q8. It can be set to a small value, such that the base
current of Q8 also is very less.

Output stage:
The final stage of the op-amp is a class AB complementary push-pull
output stage. Q11 is an emitter follower, providing a large input resistance for
minimizing the loading effects on the gain stage. Bias current for Q11 is provided
by the current mirror formed by Q7 and Q12, through Q13 and Q14 for

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minimizing the cross over distortion. Transistors can also be used in place of the
two diodes.
The overall voltage gain AV of the op-amp is the product of voltage gain of
each stage as given byAV=|Ad| |A2||A3|
Where Ad is the gain of the differential amplifier stage, A 2 is the gain of the
second gain stage and A3 is the gain of the output stage.

ww
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Fig: Internal Stages of Op-amp


IC 741 Bipolar operational amplifier:
g.n
The IC 741 produced since 1966 by several manufactures is a widely used
general purpose
operational amplifier. Figure shows that equivalent circuit of the 741 op-amp,
e
divided into various individual stages. The op-amp circuit consists of three
stages.
1. The input differential amplifier
2. The gain stage
3. the output stage.
A bias circuit is used to establish the bias current for whole of the circuit in the IC.
The op-amp is supplied with positive and negative supply voltages of value ± 15V
and the supply voltages as low as ±5V can also be used.

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Bias Circuit:
The reference bias current IREF for the 741 circuit is established by the bias
circuit consisting of two diodes-connected transistors Q11 and Q12 and resistor
R5. The Widlar current source formed by Q11, Q10 and R4 provide bias current
for the differential amplifier stage at the collector of Q10. Transistors Q8 and Q9
form another current mirror providing bias current for the differential amplifier.
The reference bias current IREF also provides mirrored and proportional current at
the collector of the double –collector lateral PNP transistor Q13. The
transistor Q13 and Q12 thus form a two-output current mirror with Q13A
providing bias current for output stage and Q13B providing bias current for Q17.

ww
The transistor Q18 and Q19 provide dc bias for the output stage. Formed by Q14
and Q20 and they establish two VBE drops of potential difference between the

w.E
bases of Q14 and Q18.

Input stage:
asy D En
The input differential amplifier stage consists of transistors Q1 through Q7
A
with biasing provided by Q8 through Q12. The transistor Q1 and Q2 form emitter

gi
– followers contributing to high differential input resistance, and whose output

nee
currents are inputs to the common base amplifier using Q3 and Q4 which offers a

rin
large voltage gain. The transistors Q5, Q6 and Q7 along with resistors R1, R2
SC

and R3 from the active load for input stage. The single-ended output is available

g.n
at the collector of Q6. The two null terminals in the input stage facilitate the null
adjustment. The lateral PNP transistors Q3 and Q4 provide additional protection
against voltage breakdown conditions. The emitter-base junction Q3 and Q4
have higher emitter-base breakdown voltages of about 50V. Therefore, placing
e
PNP transistors in series with NPN transistors provide protection against
accidental shorting of supply to the input terminals.

Gain Stage:
The Second or the gain stage consists of transistors Q16 and Q17, with
Q16 acting as an emitter –follower for achieving high input resistance. The
transistor Q17 operates in common emitterconfiguration with its collector voltage
applied as input to the output stage. Level shifting is donefor this signal at this
stage.Internal compensation through Miller compensation technique is achieved
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using the feedback capacitor C1 connected between the output and input
terminals of the gain stage.

Output stage:
The output stage is a class AB circuit consisting of complementary emitter
follower transistor pair Q14 and Q20. Hence, they provide an effective loss output
resistance and current gain. The output of the gain stage is connected at the
base of Q22, which is connected as an emitter follower providing a very high
input resistance, and it offers no appreciable loading effect on the gain stage. It is
biased by transistor Q13A which also drives Q18 and Q19, that are used for

ww
establishing a quiescent bias current in the output transistors Q14 and Q20.

w.E
6. i) Design an active load for an emitter-coupled pair (differential amplifier)

output resistance.
asy D
and perform a detailed analysis to find its differential mode gain and the

En
A
The function of a differential amplifier is to amplify the difference between

gi
two signals. The need for differential amplifier arises in many physical

nee
measurements where response from DC to many MHz of frequency is required.

rin
SC

V1
High Gain
Differential g.n
V2 amplifier
Vo
e
V0 = Adm (V1 – V2 )
If V1 = V2, then the output voltage is zero.
The difference mode input voltage is defined as V m = V1 – V2 and the
common mode input voltage is defined as
VCM=

The open circuit voltage gain can be increased by using large values of
collector resistance. For such a circuit, the voltage gain is given by

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Adm= gm RC

BJT Differential Amplifier using active loads:


The open circuit voltage gain can be increased by cascading gain stages.
Increasing gain by using large collector resistance values

ww
w.E
,
asy D En
A
gi
Fig: BJT differential amplifier with current mirror active load

nee
The active load comprises of transistors Q3 and Q4 with the transistor Q3
connected as a Diode with its base and collector shorted.

rin
SC

Under the quiescent conditions, V1=V2=0. From the symmetry of Q1 and

g.n
Q2, Ic1=Ic2=IQ/2 where base currents are assumed to be neglected. Since
Q3 and Q4 from a current mirror, I=Ic1=Ic2.
The load current IL entering the next stage is
IL= IC4 - IC3=0
e
IC4 = IC3 = IC1 = gmVid/2
where IC4 = IC3 due to current mirror action
IC2 = - gmVid/2
The current IC4 always remains equal to IC2 due to current mirror. The
load current is given by
IL = IC4 – IC2
= gmVid/2 –( -gmVid/2 )
= gmVid
The collector currents of all the transistors are equal.
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IC1 = IC2 = IC3 =IC4 = IEE/2 .


The Collector -emitter voltages of Q1 and Q2 are given by
VCE1-VCE2 =VC-VE=V CC - VEB-(-VEB)= VCC

Eqn. shows that, the offset is higher than that of a resistive loaded
differential amplifier A. This can be reduced by the use of emitter resistors
for Q 3 and Q 4 , and a transistor Q5 in the current mirror load.

Differential mode analysis:

ww The ac analysis of the differential amplifier can be made using the circuit
model as shown below. The total current i o flowing through the load

w.E resistor RL is given by

asy D
Then the output voltage is

En
gain Ad of the differential amplifier is
and the differential mode
A
gi nee
The equivalent resistance is expressed by Req = ro2 || r04 || ri5 = ri5.

rin
The gain of the differential stage then becomes Adm = gm 2 Req = gm2
SC

ri5=βIC2/IC5

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e

Fig: Differential amplifier with differential mode input and common mode
input

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6. ii) Explain supply independent biasing using zener-referenced bias


circuit. Also, design a temperature compensated zener-reference source.

The most important characteristic of a voltage reference is the temperature


coefficient of the output reference voltage TCR , and it is expressed as

The desirable properties of a voltage reference are:

ww 1. Reference voltage must be independent of any temperature change.


2. Reference voltage must have good power supply rejection which is as

w.E independent of the supply voltage as possible and

asy D En
A
gi nee
rin
SC

g.n
Fig: Voltage Reference circuit using temperature compensation scheme
e
Output voltage must be as independent of the loading of output current as
possible, or in other words, the circuit should have low output impedance.
The voltage reference circuit is used to bias the voltage source
circuit, and the combination can be called as the voltage regulator. The
basic design strategy is producing a zero TCR at a given temperature, and
thereby achieving good thermal ability. Temperature stability of the order
of 100ppm/0 C is typically expected.

Voltage Reference circuit using temperature compensation scheme:

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This technique compensates the known thermal drifts by introducing an


opposing and compensating drift source of equal magnitude.
A constant current I is supplied to the avalanche diode D B and it provides a
bias voltage of VB to the base of Q1.
Hence, with the use of resistors R1 and R2 with tapping across them at
point N compensates for the temperature drifts in the base emitter loop of
Q1.

Voltage Reference circuit using Avalanche Diode Reference:


A voltage reference can be implemented using the breakdown

ww phenomenon condition of a heavily doped PN junction. The Zener


breakdown is the main mechanism for junctions which breakdown at a

w.E voltage of 5V or less. The avalanche breakdown voltage V B of a transistor

D
incurs a positive temperature coefficient.

asy
The base bias for transistor Q1 is provided through register R1 and it also

En
provides the dc current needed to bias D B, D1 and D2 .The voltage at the
A
base of Q1 is equal to the Zener voltage VB added with two diode drops

gi
due to D1 and D2. The voltage across R2 is equal to the voltage at the base

nee
of Q1 less the sum of the base – emitter voltages of Q1 and Q2.

rin
Hence, the voltage across R2 is approximately equal to that across D B =
SC

VB. Since Q2 and Q3 act as a current mirror circuit, current I 0 equals the
current through R2. g.n
The base voltage of Q1 is the voltage VB across Zener DB.
e
Then, VB = (VBE * n) +VBE across Q1 + VBE across Q2 + drop across R2.
Here, n is the number of diodes. It can be expressed as VB = ( n+ 2) VBE +
I0 * R2.
Differentiating for VB, I0, R2 and VBE partially, with respect to temperature
T, we get

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Fig: Voltage reference using avalanche diodes and temperature

ww compensated

w.E
asy D
Dividing throughout by Io R2, we get

En
Therefore, zero temperature coefficient of I o can be obtained, if the above
A
condition is satisfied.
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PART – C

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Unit 2- APPLICATIONS OF OPERATIONAL AMPLIFIERS


Part A
1. Give the schematic of op-amp based current to voltage converter.
[APR 10]

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2. Draw the circuit diagram of differentiator and give its output

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equation. [APR 10, DEC 12]

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3. Draw and write equation of an integrator using an op-amp. [DEC 10,
e

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4. Mention two important features of an instrumentation amplifier. [APR


11,
The important features of an instrumentation amplifier are
1. High gain accuracy
2. High CMRR
3. High gain stability with low temperature coefficient
4. Low DC offset
5. Low output impedance.

5. How does precision rectifier differ from the conventional rectifier?

ww [APR 11,DEC 12] (OR)


State the difference between conventional and precision rectifier?

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[DEC14, May15}

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The conventional rectifier cannot rectify voltages below 0.6 V whereas the
precision rectifier can rectify voltages above 60 µV.

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A
6. Why are integrators preferred over differentiators? [DEC 11,

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i. Gain of an integrator decreases as frequency increases hence easy to

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stabilize with respect to oscillations. Gain of differentiator decreases
with frequency.
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ii. The differentiator is more sensitive to noise whereas integrator is less


sensitive to noise.
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7. What is comparator? [DEC 11, APR 12, May16] e

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A comparator is a circuit which compares a signal voltage applied at one


input of the op-amp with a known reference voltage at the other input. It is of
two types
1. Non-inverting comparator
2. Inverting comparator.
Applications:
Zero Crossing Detector:

8. Why active guard drive is necessary for an instrumentation


amplifier? [APR 12]

ww 1. It reduces effective common mode input capacitance


2. It reduces input leakage currents

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1. Adder

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9. Give an application of an Inverting Amplifier. [APR 13,]

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2. Phase shifter

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10. Give an application for each of the following circuits:

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Voltage follower, peak detector, Schmitt trigger and clamper [DEC 13,
Nov16]
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1. Application of Voltage Follower:


a. Buffer for impedance matching
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2. Application of peak detector:
a. Test & Measurement Instrumentation
b. Amplitude Modulation
e
3. Application of Schmitt Trigger:
a. Squaring circuit
b. Sine-Square comparator
4. Application of Clamper:
a. TV receivers

11. What is a voltage follower? [APR 14,


Voltage follower is a circuit in which output voltage follows input voltage.
i.e. Vo = Vi
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It is a Unity Gain Circuit.


It provides High Input Impedance & Zero Output Impedance.

12. Draw the circuit diagram of peak detector with waveforms. [APR 14,

ww Nov16]

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Fig: Peak detector circuit and input and output waveforms

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13. State reasons why integrator is called „Lossy‟. [APR 15]
The parallel combination of RF and CF behaves like a practical capacitor,
which dissipates power unlike an ideal capacitor. So this circuit is called a
e
Lossy Integrator

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14. What is hysteresis and mention the purpose of hysteresis in a


comparator? (May15,
The comparator with positive feedback is said to exhibit hysteresis, a dead band
condition.(i.e) when the input of the comparator exceeds Vut its output switches
from +Vsat to –Vsat and reverts to its original state, +Vsat when the input goes
below VLT. The hysteresis voltage is equal to the difference between Vut and Vlt.
Therefore VH= Vut – Vlt.

15. How do you convert a basic multiplier to a squaring and square root
circuit? [May15]

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VoltageSquarer:

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Square Rooter:

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The divider voltage can be used to find the square root of a signal by connecting

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both inputs of the multiplier to the output of the op-amp.
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PART B
1. Discuss the need for an instrumentation amplifier? Give a detailed
analysis for the same.
1. An instrumentation amplifier is a differential op-amp circuit providing high
input impedances with ease of gain adjustment through the variation of a
single resistor.
2. The important features of an instrumentation amplifier are
1. High gain accuracy
2. High CMRR
3. High gain stability with low temperature coefficient

ww 4. Low output impedance

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Fig: Basic Differential Amplifier

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For R1/R2=R3/R4, we obtain e
In the circuit of figure, source V1 sees an input impedance = R3+R4
(=101K) and the impedance seen by source V2 is only R1 (1K).

The voltage at the (+) input terminal of op-amp A3 is

Using superposition theorem, we have

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Fig: Instrumentation Amplifier


Since no current flows into op-amps, the current I flowing (upwards) in R is

I= and passes through the resistor R‘

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Putting the values of V1‘ and V2‘ in the previous equation

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The difference gain of this instrumentation amplifier R, however should

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never be made zero, as this will make the gain infinity.

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Fig: Instrumentation bridge using transducer Bridge
Figure shows a differential instrumentation amplifier using Transducer
Bridge.
The bridge is initially balanced by a dc supply voltage V dcso that V1=V2. The
differential voltage amplified by the three op-amp differential instrumentation
amplifier.

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2. Explain Schmitt trigger in detail.

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3. Detail the working of log and antilog amplifier.


When a logarithmic PN junctions obtained from a transistor is used the
circuit results in a log or antilog response.
Basic log circuit:
The logarithmic amplifier, called a log-amp or a logger is basically a
current to voltage converter with the transfer characteristics of

A grounded base transistor is placed in the feedback path. The transistor‗s


voltage-current relationship becomes that of a diode and is given by

ww Since Ic=IE for a grounded base transistor

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IS= Emitter saturation current = 10-13 A
e
K= Boltzmann‘s Constant.
T = Absolute temperature (in oK)
Therefore

Or

Taking natural log on both sides, we get

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So,

The output voltage is thus proportional to the logarithm of input voltage.


Although the circuit gives natural log (ln), one can find log10, by proper
scaling
Log10X=0.4343 ln X

ww Since emitter saturation current Is varies from transistor to transistor and

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with temperature a stable reference voltage V ref cannot be obtained. This

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is eliminated by the circuit given below

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Fig: Log amp with saturation current and temperature compensation
Assume IS1=IS2=IS
e

The output voltage is

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Where RTC is a temperature-sensitive resistance with a positive coefficient


of temperature.
Antilog Amplifier:
The input Vi for the antilog-amp is fed into the temperature compensation
voltage divider R2 and RTC and then to the base of Q2. The output Vo of the
antilog-amp is fed back to the inverting input of A1 through the resistor R1.
The base to emitter voltage of transistors Q1 and Q2 can be written as

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Fig: Antilog amplifier e

Since the base of Q1 is tied to ground, we get

The base voltage VB of Q2 is

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The voltage at the emitter of Q2 is

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decade. gi
Hence an increase of input by one volt causes the output to decrease by a

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4. Explain Differentiator and Integrator in detail.

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5. Explain the Operational amplifier using diodes in detail.


(16).
Precision Rectifier:
The ordinary diodes cannot rectify voltages below the cut-in-voltage of
the diode. A circuit which can act as an ideal diode or precision signal
processing rectifier circuit for rectifying voltages which are below the level of
cut-in voltage of the diode can be designed by placing the diode in the
feedback loop of an op-amp.

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Fig. Precision diode and its waveform
Precision diodes:
Figure shows the arrangement of a precision diode. It is a single diode
arrangement and functions as a non-inverting precision half– wave rectifier
circuit.
If V1 in the circuit of figure is positive, the op-amp output VOA also

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becomes positive. Then the closed loop condition is achieved for the op-amp
and the output voltage V0 = Vi . When Vi < 0, the voltage V0A becomes
negative and the diode is reverse biased. The loop is then broken and the
output V0 = 0.

Consider the open loop gain AOL of the op-amp is approximately 104
and the cut-in voltage Vγ for silicon diode is ≈ 0.7V. When the input voltage Vi
> Vγ / AOL, the output of the op-amp VOA exceeds Vγ and the diode D
conducts.
Then the circuit acts like a voltage follower for input voltage level V i >

Vγ / AOL ,(i.e. when Vi > 0.7/104 = 70μV), and the output voltage V0 follows the
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input voltage during the positive half cycle for input voltages higher than

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70μV as shown in figure.

D
When Vi is negative or less than Vγ / AOL, the output of op-amp VOA

asy
becomes negative, and the diode becomes reverse biased. The loop is then
broken, and the op-amp swings down to negative saturation. However, the

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output terminal is now isolated from both the input signal and the output of
the op-amp terminal thus V0 =0.
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No current is then delivered to the load RL except for the small bias

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current of the op-amp and the reverse saturation current of the diode.
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This circuit is an example of a non-linear circuit, in which linear


operation is achieved
g.n
over the remaining region (Vi < 0). Since the output
swings to negative saturation level when Vi < 0, the circuit is basically of
saturating form. Thus the frequency response is also limited.
Applications: The precision diodes are used in
e
 half wave rectifier,
 Full-wave rectifier,
 peak value detector,
 Clipper and clamper
Disadvantage:
It can be observed that the precision diode as shown in figure operated in the
first quadrant with Vi> 0 and V0 > 0. The operation in third quadrant can be
achieved by connecting the diode in reverse direction.

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Half – wave Rectifier:


A non-saturating half wave precision rectifier circuit is shown in figure.
When Vi > 0V, the voltage at the inverting input becomes positive, forcing the
output VOA to go negative. This results in forward biasing the diode D 1 and the
op-amp output drops only by ≈ 0.7V below the inverting input voltage. Diode
D2 becomes reverse biased.
The output voltage V0 is zero when the input is positive. When Vi <0,
the op-amp output VOA becomes positive, forward biasing the diode D 2 and
reverse biasing the diode D1. The circuit then acts like an inverting amplifier
circuit with a non- linear diode in the forward path. The gain of the circuit is

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unity when Rf = Ri.

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Fig. Half wave rectifier and its operation


The circuit operation can mathematically be expressed as
g.n
V0 =

en Vi>0 and V0=


wh
0

e
Rf/RiV1
for
Vi<0
The voltage VoA at the op amp output is VOA= - 0.7V for V i>0
VOA= Rf/RiV1 + 0.7V for V i<0
Advantages:
 it is a precision half wave rectifier and
 it is a non saturating one.

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The inverting characteristics of the output V0 can be circumvented by the use


of an additional inversion for achieving a positive output.
Full wave Rectifier:
The first part of the Full wave circuit is a half wave rectifier circuit. The
second part of the circuit is an inverting amplifier.

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Fig. Full wave rectifier and its operation
For positive input voltage Vi > 0V and assuming that Rf =Ri = R, the
e
output voltage VOA= Vi. The voltage V0 appears as (-) input to the summing
op-amp circuit formed by A2, The gain for the input V‗0 is R/(R/2), as shown
in figure.
The input Vi also appears as an input to the summing amplifier. Then,
the net output is V0 =-Vi -2V0= -Vi -2(-Vi) = Vi. Since Vi > 0V, V0 will be
positive, with its input output characteristics in first quadrant. For negative
input Vi < 0V, the output V‗0 of the first part of rectifier circuit is zero. Thus, one
input of the summing circuit has a value of zero. However, V i is also applied as

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an input to the summer circuit formed by the op-amp A2.


The gain for this input id (-R/R) = -1, and hence the output is V0 = -Vi.
Since Vi is negative, V0 will be inverted and will thus be positive. This
corresponds to the second quadrant of the circuit. To summarize the operation
of the circuit, V0 = Vi when Vi < 0V and
V0 = Vi for Vi > 0V, and hence V0 = |Vi |
Peak Detector
Square, Triangular, Saw tooth and pulse waves are typical examples of
non-sinusoidal waveforms. A conventional AC voltmeter cannot be used to
measure these sinusoidal waveforms because it is designed to measure the

ww
RMS value of the pure sine wave. One possible solution to this problem is to
measure the peak values of the non-sinusoidal waveforms. Peak detector

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measures the +ve peak value of the square wave input.

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Fig. Peak detector circuit and input and output waveforms


i) During the positive half cycle of Vin:
The o/p of the op-amp drives D1 on. (Forward biased)

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Charging capacitor C to the positive peak value Vp of the input volt Vin.
ii) During the negative half cycle of Vin:
D1 is reverse biased and voltage across C is retained.
The only discharge path for C is through RL since the input bias IB is
negligible.
For proper operation of the circuit, the charging time constant (CR d ) and
discharging time constant (CRL) must satisfy the following condition.
CRd <= T/10
Where Rd = Resistance of the forward-biased diode.
T = time period of the input

ww CRL>=10T(2)
waveform.

w.E
resistor.
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Where RL = load resistor.
If RL is very small so that eqn. (2) cannot

En
be satisfied.
Use a (buffer) voltage follower circuit between capacitor C and RL load
A
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R is used to protect the op-amp against the excessive discharge currents.

nee
Rcomp = minimizes the offset problems caused by input current
D2 conducts during the –ve half cycle of Vin and prevents the op-amp

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from going into negative saturation.


Positive Clipper:
g.n
A circuit that removes positive parts of the input signal can be formed by
using an op-amp with a rectifier diode. The clipping level is determined by
the reference voltage Vref, which should less than the i/p range of the op-amp
e
(Vref < Vin). The Output voltage has the portions of the positive half cycles
above Vref clipped off.The circuit works as follows:
During the positive half cycle of the input, the diode D 1 conducts only
until Vin = Vref. This happens because when Vin <Vref, the output volts V0 of
the op-amp becomes negative to device D1 into conduction when D1 conducts
it closes feedback loop and op-amp operates as a voltage follower. (i.e.)
Output V0 follows input until Vin = Vref.When Vin > Vref => the V0 becomes
+ve to derive D1 into off. It opens the feedback loop and op- amp operates

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open loop.
When Vin drops below Vref (Vin<Vref) the o/p of the op-amp V0 again
becomes –ve to device D1 into conduction. It closes the feedback path. (o/p
follows the i/p). Thus diode D1 is on for Vin<Vref (o/p follows the i/p) and D1 is
off for Vin>Vref.

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Fig Positive clipper input output waveforms
e
Negative Clipper:

Fig. Negative clipper

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The positive clipper is converted into a –ve clipper by simply reversing


diode D1 and changing the polarity of Vref voltage. The negative clipper clips
off the –ve parts of the input signal below the reference voltage. Diode D 1
conducts -> when Vin > -Vref and therefore during this period o/p volt V0
follows the i/p volt Vin. The –Ve portion of the output volt below –Vref is
clipped off because (D1 is off) Vin<-Vref. If –Vref is changed to –Vref by
connecting the potentiometer Rp to the +Vcc, the V0 below +Vref will be
clipped off. The diode D1 must be on for Vin > Vref and off for Vin.

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Fig. Input output waveforms


Positive and Negative Clampers:
g.n
In clamper circuits a predetermined dc level is added to the output voltage.
(or) The output is clamped to a desired dc level.
1. If the clamped dc level is +ve, the clamper is positive clamper
e
2. If the clamped dc level is –ve, the clamper is negative clamper.
Other equivalent terms used for clamper are dc inserter or restorer. Inverting
and Non Inverting that uses this technique.
Capacitor:
The Value of the capacitors in these circuits depends on different input rates
and pulse widths.
1. In both circuits the dc level added to the o/p voltage is approximately equal to
Vcc/2.
2. This +ve fixed dc level is needed to obtain a maximum undistorted
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symmetrical sine wave.

Fig. Positive –Negative campers

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Fig. Input and output waveform with +Vref

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Peak clamper circuit:

g.n
In this circuit, the input waveform peak is clamped at Vref. For this reason, the
circuit is called the peak clamper.First consider the input voltage Vref at the (+)
input: since this volt is +ve, V‗0 is also +ve which forward biases D1. This closed
the feedback loop.Voltage Vin at the (-) input: During its –ve half cycle, diode D1
e
conducts, charging c; to the –ve peak value of Vp. During the +ve half cycle,
diode D1 in reverse biased. Since this voltage Vp is in series with the +ve peak
volt Vp the o/p volt V0 = 2 Vp. Thus the nett o/p is Vref plus 2 Vp. So the – ve
peak of 2 Vp is at Vref. For precision clamping, C iRd << T/2. Where Rd =
resistance of diode D1 when it is forward biased.T = time period of the input
waveform.Resistor R is used to protect the op-amp against excessive discharge
currents from capacitor Ci especially when the dc supply voltages are switched
off. A +ve peak clamping is accomplished by reversing D1 and using –ve
reference voltage (-Vref).

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Fig: Peak clamper circuit

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Fig: Input and Output Waveforms with -Vref

g.n
6. i) Explain the working of (i)V to I converter (ii) I to V Converter.
V to I converter :
To convert a voltage signal to a proportional output current two types of
e
circuits possible.
V-I Converter with floating load
V-I Converter with grounded load
Voltage to Current Converter with floating loads (V/I):
Voltage to current converter in which load resistor R L is floating (not
connected to ground).
Voltage at node ‗a‘ is Vf.

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The input voltage Vi is converted into an output current of .

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w.E Fig: Voltage to current converter with floating load

D
Voltage to Current converter with grounded load:

asy
When one of end of the load is grounded it is no longer possible to place
the load within feedback loop of op-amp

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Fig: Voltage to Current converter with grounded load
e

The gain of the circuit is 1+R/R = 2. The output voltage is

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6. ii) Explain Adder & Subtractor in detail.

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7. Explain the construction and working of active filters.


An electric filter is often a frequency selective circuit that passes a specified band
of frequencies and blocks or alternates signal and frequencies outside this band.
Filters may be classified as
1. Analog or digital.
2. Active or passive
3. Audio (AF) or Radio Frequency (RF)
1. Analog or digital filters:
Analog filters are designed to process analog signals, while digital filters process
analog signals using digital technique.

ww
2. Active or Passive:
Depending on the type of elements used in their construction, filter may be

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classified as passive or Active elements used in passive filters are Resistors,

D
capacitors, inductors. Elements used in active filters are transistor, or op-amp.

asy
Active filters offer the following advantages over passive filters:

En
1. Gain and Frequency adjustment flexibility:
A
Since the op-amp is capable of providing gain, the i/p signal is not attenuated as

2. No loading problem:
gi
it is in a passive filter. [Active filter is easier to tune or adjust].

nee
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Because of the high input resistance and low o/p resistance of the op-amp, the
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active filter does not cause loading of the source or load.


3. Cost:
g.n
Active filters are more economical than passive filter. This is because of the
variety of cheaper op-amps and the absence of inductors. e
1. Low pass Filters
2. High pass Filters
3. Band pass filters
4. Band –reject filters
5. All pass filters.

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Frequency response of the active filters:

Fig Frequency response of Low Pass filter and High pass Filter

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A
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Fig Frequency response of Band Pass filter and Band reject Filter

nee
Low pass filters:
rin
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1. It has a constant gain from 0 Hz to a high cutoff frequency f1.


2. At fH the gain in down by 3db. g.n
3. The frequency between 0 Hz and fH are known as the pass band frequencies
where as the range of frequencies those beyond fH, that are attenuated includes e
the stop band frequencies.
4. Butterworth, Chebyshev and Cauer filter are some of the most commonly used
practical filters.
5. The key characteristics of the butter worth filter are that it has a flat pass band
as well as stop band. For this reason, it is sometimes called flat- flat filters.
6. Chebyshev filter -> has a ripple pass band & flat stop band.
7. Causer Filter -> has a ripple pass band & ripple stop band. It gives best stop
band response among the three.

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High pass filter:


High pass filter with a stop band 0 <f< f L and a pass band f> f L
fL -> low cut off frequency
f -> operating frequency.

Band pass filter:


It has a pass band between 2 cut off frequencies fH and fL where fH > fL and
two, stop bands: 0<f<
fL and f > fH between the band pass filter (equal to fH - fL.
Band –reject filter: (Band stop or Band elimination)

ww
It performs exactly opposite to the band pass.
It has a band stop between 2 cut-off frequency fL and fH and 2 pass bands: 0<f<

w.E
fL and f> fH
fC -> center frequency.
Note:
asy D En
The actual response curves of the filters in the stop band either Ror S or both
A
with Rin

the order of the filter.


gi
The rate at which the gain of the filter changes in the stop band is determined by

nee
rin
Ex: 1st order low pass filter the gain rolls off at the rate of 20dB/decade in the
SC

stop band.
(i.e) for f > fH.
g.n
2nd order LPF -> the gain roll off rate is 40dB/decade.
1st order HPF -> the gain rolls off at the rate of 20dB (i.e.) until f:fL
2nd order HPF -> the gain rolls off at the rate of 40dB/decade
e
First order LPF Butterworth filter:
First order LPF that uses an RC for filtering op-amp is used in the non inverting
configuration.
Resistor R1 & Rf determine the gain of the filter. According to the voltage –divider
rule, the voltage at the non-inverting terminal (across capacitor) C is,

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Fig. First order LPF Butterworth filter


Gain A= (1+Rf/R1)

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Voltage across capacitor V1= Vi / (1+j2πfRC)
Output voltage V0 for non inverting amplifier =AV1

w.E
= (1+Rf/R1) Vi/(1+j2πfRC)

D
Overall gain V0/Vi = (1+Rf/R1) Vi/(1+j2πfRC

asy
Transfer function H(s) =A/(jf/fh+1) if fh =1/2πRC
H (jω) = A/( j RC+1) = A/( j RC+1).

En
A
The gain magnitude and phase angle of the equation of the LPF can be obtained

1. At very low frequency, f < fH


gi
by converting eqn. (1) b into its equivalent polar form as follows.

nee
|H (jω)| =A

rin
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2. At f =fH
|H (jω)| =A/√2=0.707A
g.n
3. At f> fH
|H (jω)| <<A ≅ 0
When the frequency increases by tenfold (one decade), the volt gain is divided by
e
10. The gain falls by 20 dB (=20log10) each time the frequency is reduces by 10.
Hence the rate at which the gain rolls off fH = 20 dB or 6dB/octave (twofold Rin
frequency). The frequency f = fH is called the cut off frequency because the gain
of the filter at this frequency is down by 3 dB (=20 log 0.707).
Filter design:
A LPF can be designed by implementing the following steps.
1. Choose a value of high cut off frequency fH.
2. Select a value of C less than or equal to 1μf.
3. Choose the value of R using fh=1/2πRC

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4. Finally select values of R1 and RF dependent on the desired pass band gain
AF
Using A= (1+Rf/R1)
Second order LP Butterworth filter:
A second order LPF having a gain 40dB/decade in stop band. A First order LPF
can be converted into a II order type simply by using an additional RC network.
The gain of the II order filter is set by R1 and RF, while the high cut off frequency
fH is determined by R2, C2, R3 and C3.

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Fig. second order LP Butterworth filter

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Fig. Second order Low pass Butterworth and filter with unity gain and its
transfer function

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Filter Design:
1. Choose a value for a high cut off freq. (fH ).
2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C then
choose a value of C<=1μf.
3. Calculate the value of R R =1/2πfhC
4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3 )
values, the pass band volt gain AF = 1 + RF / R1 of the second order had to be =
to 1.586. RF = 0.586 R1. Hence choose a value of R1 <=100kΩ.
5. Calculate the value of RF.
First order HP Butterworth filter:

ww
High pass filters are often formed simply by interchanging frequency-determining
resistors and capacitors in low-pass filters. (i.e) I order HPF is formed from a I

w.E
order LPF by interchanging components R & C. Similarly II order HPF is formed

asy D
from a II order LPF by interchanging R & C.

En
A
gi nee
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g.n
Fig. I order HPF and its frequency response
Here I order HPF with a low cut off frequency of fL. This is the frequency at which
the magnitude of the gain is 0.707 times its passband value. Here all the
e
frequencies higher than fL are passband frequencies.
The output voltage V0 of the first order active high pass filter is

The gain of the filter:

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Frequency response of the filter is

-20 db /decade. The frequency below


cutoff frequency is stop band.
Second – order High Pass Butterworth Filter:

ww
I order Filter, II order HPF can be formed from a II order LPF by interchanging the
frequency

w.E
asy D En
A
gi nee
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Fig. II order HPF and its frequency response
SC

Band pass filters

g.n
frequencies and attenuates others. Its high cutoff
frequency and low cutoff frequency are related as fH >fL and maximum gain at
resonant frequency e
- fL) = fr/B where B= bandwidth.
pass and wide band pass filters
Wide band pass filter:
It is connection of a low pass filter and a high pass filter in cascade.
The fH of low pass filter and fL of high pass filter are related as fH > fL

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Fig. (a) Wide band pass filter and (b) its frequency response

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PART – C

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UNIT-3
ANALOG MULTIPLIER AND PLL
2-MARKS
1. What are the advantages of emitter coupled transistor pair? [APR 11]
Cascading doesn‘t need Coupling Capacitors.
It is very sensitive to difference between two input voltages.

2. What are the advantages of variable transconductance technique? [DEC


11, APR 12]
Good accuracy

ww Economical
Simple to integrate into monolithic chip

w.E Higher bandwidth

asy D
3. Define the term lock-in-range of PLL. [DEC 12, DEC 13, DEC 10]

En
The range of frequencies over which the PLL can maintain lock with the
A
incoming signal is called lock-in range or tracking range. It is also expressed
as a percentage of fo.
gi nee
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Capture range = 2fL

4. Define: Capture range of a PLL. [DEC 11, DEC 10


The range of frequencies over which the PLL can acquire lock with an
input signal is called the capture range. It is also expressed as a percentage
of fo.

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Capture range = 2fC

5. State the operation of basic PLL. [APR 14]

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w.E
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Phase detector compares the frequency and phase of input and output signal,

En
to give error voltage Ve. The phase detector is actually a multiplier, it produces
A
(fs+fo). gi
sum (fs+fo) and difference (fs-fo). The LPF removes high frequency component

nee
(fs-fo) is amplified. It provides control voltage Vc.Vc shifts the VCO output

rin
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voltage to make output frequency equal to input frequency. The circuit said to
be locked.
Now phase difference alters the Vc to maintain lock. g.n
6. Draw the relation between the capture ranges and lock range in a PLL.
e
[APR 10, Nov15]

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7. Mention any two applications of PLL. [APR 13,Nov16, May15]


Frequency multiplier
FM Demodulator
AM Detection
Frequency Translation

8. A PLL frequency multiplier has an input frequency of “f” and a decade


counter is included in the loop. What will be the frequency of the PLL
output? [APR 13]

ww Solution:
f = fo * 10n

w.E fo = f * 10-n

asy
9. What is a VCO? [APR 10,
D En
The VCO is a Free-running multivibrator and operates at a set of
A
frequency fo called free running frequency. The frequency is determined by an

gi
external timing capacitor and an external resistor. It can also be shifted to

nee
either side by applying a DC control voltage v c to an appropriate terminal of

rin
the IC. The frequency deviation is directly proportional to the DC control
SC

voltage and hence it is called as Voltage Controlled Oscillator or VCO.

g.n
10. VCO is also called as V-f converter. Why? [APR 12] (OR) With reference
to a VCO, define voltage to frequency conversion factor Kv. [APR 11]
The VCO provides the linear relationship between the applied voltage and
e
the oscillation frequency. Applied voltage is called control voltage. The control of
frequency with the help of control voltage is also called voltage to frequency
conversion. Hence VCO is also called voltage to frequency converter.

Voltage to frequency converter

∆vc = modulation voltage


∆fo = frequency shift

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11. What is meant by frequency synthesizing? [DEC 13] (OR) What is the
need of frequency synthesizer? [APR 14]
A frequency synthesizer is an electronic system for generating any of a
range of frequencies from a single fixed time base or oscillator. They are
found in many modern devices, including radio receivers, mobile telephones,
radiotelephones, walkie-talkies, CB radios, satellite receivers, GPS systems,
etc. A frequency synthesizer can combine frequency multiplication, frequency
division, and frequency mixing (the frequency mixing process generates sum
and difference frequencies) operations to produce the desired output signal.

ww
12. What is a two quadrant multiplier? What is a four quadrant multiplier?[
DEC 12,May16]

w.E
In two quadrant multiplier, one input is held positive and the other is allowed

D
to swing both positive and negative.

asy
In a multiplier circuit, if both the inputs are allowed to swing in both positive

En
and negative directions the multiplier is called as a four quadrant multiplier.
A
[Nov16]
gi
13. Draw the block diagram of IC 566 VCO (Voltage Controlled Oscillator).

nee
rin
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14. Draw the circuit diagram of a PLL circuit using as a FM detector. [May16]

ww
15. Mention two applications of analog multiplier. [Nov15]

w.E
The multiplier ICs are used for the following purposes:
1. Voltage Squarer
2. Frequency doublers
3. Voltage divider
4. Square rooter
asy D En
A
5. Phase angle detector
6. Rectifier gi nee
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PART B
1. With a neat functional diagram, explain the operation of VCO. Also derive
an expression for f0.
A VCO is oscillator circuit in which the frequency of oscillations can be controlled
by an externally applied voltage it generates an output frequency directly
proportional to input voltage.
Constant Current source:
It controls the timing capacitor CT.
Amount of current can be controlled by
1. Modulating input

ww 2. Timing resistor RT.


Voltage at pin 6 & pin 5 must be same.

w.E
If voltage at pin 5 increases, voltage at pin 6 also increases

asy D
Voltage across RT is low thus decreasing the charging current.
Oscillations can be removed by connecting capacitor 0.001μf between pin5 & pin 6.

En
A
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Fig. Pin diagram and block diagram of VCO

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A timing capacitor CT is linearly charged or discharged by a constant current


source.
The amount of current can be controlled by changing the voltage is applied at the
modulating input (pin 5) or by changing the timing register RT external to IC chip.
If the modulating voltage at pin 5 is increased the voltage at pin 6 also increases,
resulting is less voltage across RT, and decreasing the charging current.
The voltage across the capacitor CT is applied to the inverting input terminal of
the Schmitt trigger A2 via buffer amplifier A1.
When the voltage on the capacitor CT exceeds 0.5 VCC during charging the
output of the Schmitt trigger goes low.

ww
The capacitor discharges and when it is at 0.25 VCC , the input of Schmitt trigger
goes HIGH (VCC). This gives a triangular voltage waveform across CT. which is

w.E
available at pin 4. The square wave output of the Schmitt trigger is inverted by

asy D
inverter A3 and is available at pin 3.

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2. Explain in detail the Monolithic PLL with reqired sketches.

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3. Explain the Applications of PLL in Detail.


The output from a PLL system can be obtained either as the voltage signal vc(t)
corresponding to the error voltage in the feedback loop, or as a frequency signal
at VCO output terminal. The voltage output is used in frequency discriminator
applications whereas the frequency output is used in signal conditioning,
frequency synthesis or clock recovery applications.
When PLL is locked to an input frequency, the error voltage vc(t) is proportional
to (fs-fo). If the input frequency is varied as in the case of FM signal vc will also
vary in order to maintain the lock. Thus the voltage output serves as a frequency
discriminator which converts the input frequency changes to voltage changes.

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The circuit diagram of LM565 PLL

In the case of frequency output, if the input signal is comprised of many


frequency components corrupted with noise and other disturbances, the PLL can
be made to lock, selectively on one particular frequency component at the input.
The output of VCO would then regenerate that particular frequency (because of
LPF which gives output for beat frequency) and attenuate heavily other
frequencies. VCO output thus can be used for regenerating or reconditioning a
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desired frequency signal (which is weak and buried in noise) out of many
undesirable frequency signals.
Some of the typical applications of PLL are discussed below.
Frequency Multiplier:
Frequency divider is inserted between the VCO & phase comparator. Since the
output of the divider is locked to the fIN, VCO is actually running at a multiple of
the input frequency.
The desired amount of multiplication can be obtained by selecting a proper
divide-by-N network, where N is an integer.

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Fig. Frequency multiplier using PLL
e
Frequency Shift Keying (FSK) demodulator:
In computer peripheral & radio (wireless) communication the binary data or code
is transmitted by means of a carrier frequency that is shifted between two preset
frequencies. Since a carrier frequency is shifted between two preset frequencies,
the data transmission is said to use a FSK. The frequency corresponding to logic
1 & logic 0 states are commonly called the mark & space frequency.
For example, when transmitting teletype writer information using a modulator-
demodulator (Modem) a 1070-1270 (mark-space) pair represents the originate
signal, while a 2025-2225 Hz (mark-space) pair represents the answer signal.

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FSK Generator:

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frequency is controlled by the state of transistor Q1.

En
A
state of the digital data input.

transmitted.
gi nee
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the transistor Q1 is off. Under the condition, 555 timer
SC

works in its normal mode as an astable multivibrator i.e., capacitor C charges


through RA & RB to 2/3Vcc & discharges through RB to 1/3 Vcc. Thus capacitor
g.n
C charges & discharges between 2/3Vcc & 1/3 Vcc as long as the input is logic 1.

fo=1.45/(RA +2RB)C = 1070 Hz (mark frequency)


e
resistance Rc across RA. This action reduces the charging time of capacitor C1
increases the output frequency, which is given by,
fo= 1.45/(RA || RC+2 RB)C = 1270 Hz (space frequency)

space frequency of 1270 Hz. The difference between the FSK signals of 1070 Hz
& 1270 Hz is 200 Hz, this is called ―frequency shift‖.
omparator between
the output of the ladder filter and pin 6 of PLL.

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with R1 so that at fIN = 1070 Hz.


FSK Demodulator:

tracks it between the


2 frequencies.

filter is used to remove the carrier component from the output.


Applications:
In digital data communication and computer peripheral, binary data is transmitted

ww
by means of a carrier frequency which is shifted between two preset frequencies.
This type of data transmission is called frequency shift keying (FSK) technique.

w.E
The binary data can be retrieved using FSK demodulator. The figure below

D
shows FSK demodulator using PLL for tele-typewriter signals of 1070 Hz and

asy
1270 Hz. As the signal appears at the input, the loop locks to the input frequency

En
and tracks it between the two frequencies with a corresponding dc shift at the
A
output. A three stage filter removes the carrier component and the output signal

gi
is made logic compatible by a voltage comparator.

nee
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Fig. 3.21 FSK demodulator circuit
AM Demodulation:
A PLL may be used to demodulate AM signals as shown in the figure below. The
PLL is locked to the carrier frequency of the incoming AM signal. The output of
VCO which has the same frequency as the carrier, but unmodulated is fed to the
multiplier. Since VCO output is always 900 before being fed to the multiplier. This
makes both the signals applied to the multiplier and the difference signals, the
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demodulated output is obtained after filtering high frequency components by the


LPF. Since the PLL responds only to the carrier frequencies which are very close
to the VCO output, a PLL AM detector exhibits high degree of selectivity and
noise immunity which is not possible with conventional peak detector type AM
modulators.

ww
w.E
FM Demodulation: asy D Fig. AM demodulator

En
If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of
A
gi
the input signal. The filtered error voltage which controls the VCO and maintains

nee
lock with the input signal is the demodulated FM output.
The VCO transfer characteristics determine the linearity of the demodulated

rin
SC

output.

g.n
Since, VCO used in IC PLL is highly linear, it is possible to realize highly linear
FM demodulators.
Frequency multiplication/division:
The block diagram shown below shows a frequency multiplier/divider using PLL.
e
A divide by N network is inserter between the VCO output and the phase
comparator input. In the locked state, the VCO output frequency fo is given by fo
= Nfs. The multiplication factor can be obtained by selecting a proper scaling
factor N of the counter.
Frequency multiplication can also be obtained by using PLL in its harmonic
locking mode.
If the input signal is rich in harmonics e.g. square wave, pulse train etc., then the
VCO can be directly locked to the n-th harmonic of the input signal without
connecting any frequency divider in between. However, as the amplitude of the

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higher order harmonics becomes less, effective locking may not take place for
high values of n. Typically n is kept less than 10.

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w.E Fig. Frequency Divider

D
The circuit of the figure above can also be used for frequency division. Since the

asy
VCO output (a square wave) is rich in harmonics, it is possible to lock the m-th

En
harmonic of the VCO output with the input signal fs. The output fo of VCO is now
A
given by fo=fs/m

gi nee
In digital wireless communication systems (GSM, CDMA etc), PLL's are used to
provide the

rin
SC

Local Oscillator (LO) for up-conversion during transmission, and down-

g.n
conversion during reception. In most cellular handsets this function has been
largely integrated into a single integrated circuit to reduce the cost and size of the
handset.
However due to the high performance required of base station terminals, the
e
transmission and reception circuits are built with discrete components to achieve
the levels of performance required. GSM LO modules are typically built with a
Frequency Synthesizer integrated circuit,
and discrete resonator VCO's.
Principle of PLL synthesizers
A phase locked loop does for frequency what the Automatic Gain Control does
for voltage. It compares the frequencies of two signals and produces an error
signal which is proportional to the difference between the input frequencies.

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The error signal is then low pass filtered and used to drive a voltage-controlled
oscillator (VCO) which creates an output frequency. The output frequency is fed
through a frequency divider back to the input of the system, producing a negative
feedback loop.
If the output frequency drifts, the error signal will increase, driving the frequency
in the opposite direction so as to reduce the error. Thus the output is locked to
the frequency at the other input. This input is called the reference and is derived
from a crystal oscillator, which is very stable in frequency.
The block diagram below shows the basic elements and arrangement of a PLL
based frequency synthesizer.

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Fig. PLL based frequency synthesizer
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The key to the ability of a frequency synthesizer to generate multiple frequencies

g.n
is the divider placed between the output and the feedback input. This is usually in
the form of a digital counter, with the output signal acting as a clock signal.
The counter is preset to some initial count value, and counts down at each cycle
of the clock signal. When it reaches zero, the counter output changes state and
e
the count value is reloaded.
This circuit is straightforward to implement using flip-flops, and because it is
digital in nature, is very easy to interface to other digital components or a
microprocessor. This allows the frequency output by the synthesizer to be easily
controlled by a digital system.
Example:
Suppose the reference signal is 100 kHz, and the divider can be preset to any
value between 1 and 100. The error signal produced by the comparator will only

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be zero when the output of the divider is also 100 kHz. For this to be the case,
the VCO must run at a frequency which is 100 kHz x the divider count value.
Thus it will produce an output of 100 kHz for a count of 1, 200 kHz for a count of
2, 1 MHz for a count of 10 and so on. Note that only whole multiples of the
reference frequency can be obtained with the simplest integer N dividers.
Fractional N dividers are readily available
Practical considerations:
In practice this type of frequency synthesizer cannot operate over a very wide
range of frequencies, because the comparator will have a limited bandwidth and
may suffer from aliasing problems. This would lead to false locking situations, or

ww
an inability to lock at all. In addition, it is hard to make a high frequency VCO that
operates over a very wide range. This is due to several factors, but the primary

w.E
restriction is the limited capacitance range of varactor diodes. However, in most

D
systems where a synthesizer is used, we are not after a huge range, but rather a

asy
finite number over some defined range, such as a number of radio channels in a

En
specific band. Many radio applications require frequencies that are higher than
A
can be directly input to the digital counter. To overcome this, the entire counter

gi
could be constructed using high-speed logic such as ECL, or more commonly,

nee
using a fast initial division stage called a prescaler which reduces the frequency

rin
to a manageable level. Since the prescaler is part of the overall division ratio, a
SC

fixed prescaler can cause problems designing a system with narrow channel

g.n
spacing‘s - typically encountered in radio applications. This can be overcome
using a dual-modulus prescaler. Further practical aspects concern the amount of
time the system can switch from channel to channel, time to lock when first
switched on, and how much noise there is in the output. All of these are a
e
function of the loop filter of the system, which is a low-pass filter placed between
the output of the frequency comparator and the input of the VCO. Usually the
output of a frequency comparator is in the form of short error pulses, but the input
of the VCO must be a smooth noise- free DC voltage. (Any noise on this signal
naturally causes frequency modulation of the VCO.). Heavy filtering will make the
VCO slow to respond to changes, causing drift and slow response time, but light
filtering will produce noise and other problems with harmonics. Thus the design of
the filter is critical to the performance of the system and in fact the main area that
a designer will concentrate on when building a synthesizer system.
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4. Explain Analog Multiplier and its applications in detail.

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5)(i) Explain the analog multiplier using emitter coupled logic.Analyze the
Gilbert‟s four quadrant multiplier cell with a neat circuit diagram. Explain
how a frequency doubler can be realized using this cell.
(ii) Explain the purpose and functioning of Variable trans-conductance
multiplier
Analog multiplier using emitter coupled logic

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Fig: Multiplier circuit using an emitter coupled pair

rin
where V i s thermal voltage and the base currents have been neglected.
SC

Combining above difference between the two output currents as


g.n
The dc transfer characteristics of the emitter – coupled pair is shown in figure. It
shows that the emitter coupled pair can be used as a simple multiplier using this
e
configuration. When the differential input voltage V1 << VT, we can appropriate
as given by

The current IEE is the bias current for the emitter – coupled pair. If the current
IEE is made proportional to a second input signal V2, then

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ww Fig: DC Transfer characteristics of emitter coupled pair


This arrangement is shown in figure. It is a simple modulator circuit

w.E
constructed using a differential amplifier. It can be used as a multiplier,

D
provided V1 is small and much less than 50mV and V2 is greater than VBE

asy
(on). But, the multiplier circuit shown in figure has several limitations. The first

En
limitation is that V2 is offset by VBE (on).
A
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Fig: A simple modulator using a differential amplifier


The second is that V2 must always be positive which results in only a two-
quadrant multiplier operation. The third limitation is that, the tanh (X) is
approximately as X, where X = V1 /2VT.The first two limitations are overcome in
the Gilbert cell.

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Gilbert‟s four quadrant multiplier cell :


If both the inputs are allowed to swing in both positive and negative directions,
the operation.
The bias current IEE is emitter bias current for Q1 and Q2. The current ΔIC is
related to the two input voltages Vid1 and Vid2.
Two inputs determine the division of the total current I E among the various
branches of the circuit.
The devices are cross-coupled and the current IE is constant.

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Fig: Gilbert‟s four quadrant multiplier cell :

g.n
Assume all the transistors are well matched.The hfe for the transistors is very high.
I1+I2 = I5
I3+I4 = I6
I5+I6 = IE
e
Assuming V1<< VT,the current unbalance in the differential pairs can be expressed as
I1-I2 = (gm)12 V1
I3-i4 = (gm)34 V1
Under the absence of emitter degeneration resistancee,the transconductances
are directly proportional to the bias currents.

Differential Output:

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Vo=RL[(I1-I2)-(I3-I4)]
Vo=RL[(gm)12V1-(gm)34V1]

Vo=K.V1.V2
Thus the output is proportional to the product of two input voltages.
(ii)Variable trans-conductance multiplier

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Fig: Variable trans-conductance multiplier

rin
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It uses the principle of the dependence of the transistor transconductance


on the emitter current bias.
g.n
Differential amplifier is formed by transistors Q1 and Q2 for very small
values of differential input voltage V1, V1<<VT
Vo = gmRLV1
e
The transconductance gm depends on the emitter current IE which can be
controlled by applying second voltage V2 to the transistor Q3.
The overall voltage transfer can be expressed as

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PART - C

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Unit - 4 Analog To Digital and Digital To Analog Converters


PART - A
1. Compare and contrast binary ladder and R-2R ladder DAC? [DEC 10,
S.No Binary Ladder DAC R-2R Ladder DAC
1 Wide range of resistor values are Only 2 values of resistor are
needed needed
2 It operates in voltage mode It operates in voltage mode

2. Mention any two specifications of a D/A converter. [APR 13],


OR
Define resolution and conversion time of DAC. [DEC 10],

ww OR
Define resolution of a data converter. [APR 10],

w.E OR

Resolution

D
What is meant by resolution of a DAC? [DEC 11, DEC 14]

asy
The resolution of a converter is the smallest change in voltage which may

En
be produced at the output or input of the converter.
A
gi
Resolution (in volts) =

nee
VFS – Full scale voltage
n – no of bits

rin
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Conversion time:

g.n
It is defined as the total time required to convert an analog signal

e
into its digital output. It depends on the conversion technique used & the
propagation delay of circuit components.
The conversion time of a successive approximation type ADC is
given by
Tc = T(n+1)
Where T --- clock period
Tc --- conversion time
N --- no. of bits

3. Define accuracy of a D/A converter. [APR 11,


Absolute Accuracy is the maximum deviation between the actual
converter output and the ideal converter output.

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Relative Accuracy is the maximum deviation after gain and offset


errors have been removed.
The accuracy is also specified in terms of LSB increments or full scale
voltage.
4. Define settling time of D/A converter. [APR 12,
Settling time of DAC is defined as the time until the output voltage reaches
and don‘t leaves again a defined voltage tolerance band. It is said the DAC
has settled to X bit or X ppm or X% within X time.

5. What is a sample/hold circuit? [APR 14]

ww (OR)
Draw a sample and hold circuit. [DEC 13]

w.E A sample and hold circuit samples an input signal and holds on to its last

Application:

D
sampled value until the input is sampled again.

asy
Digital interfacing
En
A
ADC
PCM systems
gi nee
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g.n
6. What is the main drawback of dual slope ADC? [DEC 12, APR 12
The main drawback of dual slope ADC is the Long Conversion Time.
e
7. Give any two advantages of SA type ADC. [APR 14,
1. Very fast
2. Versatile
8. For an n-bit flash type A/D converter, how many comparators are
required? State the disadvantage of that type of converter. [APR 13,
Nov15, May16,

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The number of comparators required are2n-1, where n is the desired


number of bits
Disadvantage:
Number of comparators doubles for each added bits.
If n increases, priority encoder will be complex.

9. Which is the fastest ADC? State the reason. [DEC 11, APR 11
Flash type ADC is the fastest because the conversion takes place
simultaneously rather than sequentially. Conversion time is 100 ns or less.
Conversion time is limited by the comparator and encoder only.

ww
10. Give the advantages of integrating type ADC. [APR 10,

w.E 1. It does not require a S/H circuit.

asy D
2. It is possible to transmit frequency even in noisy environment.

En
11. What are the advantages of inverted R – 2R (current type) ladder D/A
A
converter over R – 2R (voltage type) D/A converter? [Nov16, Nov15, ]

gi
1. The major advantage of current mode D/A converter is that the voltage change

nee
across each switch is minimal. So the charge injection is virtually eliminated and
the switch driver design is made simpler.
rin
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2. In Current mode or inverted ladder type DACs, the stray capacitance do not

g.n
affect the Speed of response of the circuit due to constant ladder node voltages.
So improved speed performance.

12. What is the need for electronic switches in D/A converter? [Nov16]
e
Electronic switches are used to ensure the high speed switching operations for
different types of DACs.

13. What is oversampling?[May 15]


The technique of increasing the apparent sampling frequency of a digital signal
by repeating each digit a number of times, in order to facilitate the subsequent
filtering of unwanted noise.

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PART B
1. Explain Various DAC technique in detail.

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2. i) With a neat sketch explain flash type of Analog to digital Converter.


[May/June 2014]
This is the simplest possible A/D converter. It is at the same time, the fastest and
most expensive technique. The circuit cosist of a resistive divider network, 8 Op-
ampcomparator and 8 line to 3 line ecoder (3-bit priority encoder). The
comparator and truth table is shown in the fig. A small amount of hysteresis is
built into the comparator to resolve

ww
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g.n
Any problem that might occur if both inputs were of equal voltage as shown in
truth table. In the fig, at each node of the resistive divider, a comparison voltage
e
is available. Since all the resistors are of equal value, the voltage levels
available at the nodes are equally divided between the reference voltage V Rand
the ground. The purpose of the circuit is to compare the analog input voltage
Vawith each of the node voltage. The truth table for the flash type AD converter
is shown in fig. the circuit has the advantage of high speed as the conversion
take place simultaneously rather than sequentially. Typical conversion time is
100 ns or less. Conversion time is limited only by the speed of the comparator
and of the priority encoder. By using an Advanced Micro Device AMD 686A

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comparator and a T1147 priority encoder, conversion delays of the order of


20ns can be obtained.

Comparator and its truth table

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A
Truth table for a flash type A/D converter

gi
This type of ADC has the disadvantage that the number of comparator required

nee
almost doubles for each added bit. A 2-bit ADC requires 3 comparators, 3-bit
ADC needs 7, whereas 4-bit requires 15 comparators. In general, the number of

rin
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comparators required are 2n-1 where n is the desired number of bits. Hence the
number of comparators approximately doubles for each added bit. Also the
g.n
larger the value of n, the more complex is the priority encoder.
Advantages
Simplest in terms of operational theory
e
Most efficient in terms of speed, very fast
Limited only in terms of comparator and gate propagation delays
Disadvantages
Lower resolution
Expensive
For each additional output bit, the number of comparators is doubled
i.e. for 8 bits, 256 comparators needed

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2. ii. Explain Successive approximation type of Analog to digital Converter


in detail. [May/June 2010, Dec 2009], [Nov/Dec 2012]

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3. Explain Single slope ADC & Dual slope ADC in detail [May/June 2014]

ww Fig: Single slope ADC

w.E
At the start, the reset signal is provided to the ramp generator and the counters.

D
Thus counters are rested to 0‘s. The analog input voltage V in is applied to the

asy
positive terminal of the comparator. As this is more positive than the negative

En
input, the comparator output goes high. The output of ramp generator is applied
A
to the negative terminal of the comparator. The high output of the comparator

high output starts the ramp


gi
enable the AND gate which allows clock to reach to the counters and also this

nee
rin
The ramp voltage goes positive until it exceeds the input voltage. When it
SC

exceeds Vin, comparator output goes low. This disables AND gate which in turn

g.n
stop the clock to the counter. The control circuitry provides the latch signal which
is used to latch the counter data. The reset signal reset the counter to 0‘s and
also reset the ramp generator. The latched data is then displayed using decoder
and a display device.
e
Let us consider the practical example to understand the working. Assume that the
clock frequency is 1 MHZ. There are four BCD counters and the input V in is 2.000
V.
Now let ramp has a slope of 1V/ms. As the input is 2.000 V, the ramp will
take 2ms to reach to 2V and to stop the clock to the counter
Now many pulse will reach to the counter during 2ms? It can be calculated
from the frequency of the clock. The number of pulses reaching to the counter in
2 ms is

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The high comparator output latches the counter Output and makes it available for
the display. Inserting a decimal point at the proper point in the seven segment
display gives a reading of 2.000. But we want binary output. In such case instead
of BCD counter, binary counter must be used, where output will be straight binary
coded.
The main limitations of this circuit are,
i. Its resolution is less. Hence for applications which require resolution of
9 part in 20,000 or more, this ADC is not suitable.

ww ii. Variation in ramp generator due to time, temperature or input voltage


sensitivity also causes a lot of problems.

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4. i) Explain high speed sample and hold circuits in detail [Nov/Dec 2012]

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4. ii) Explain the concept of over sampling using A/D converter.

It consists of 2 main parts - modulator and digital filter.


The modulator includes an integrator and a comparator with a feedback
loop that contains a 1-bit DAC.
The modulator oversamples the input signal, converting it to a serial bit
stream with a frequency much higher than the required sampling rate.
This is then transformed by the output filter to a sequence of parallel digital
words at the sampling rate.
The characteristics of sigma-delta converters are high resolution, high

ww accuracy, Low noise and low cost.


Typical applications are for speech and audio.

w.E A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the

D
desired signal by a large factor and filters the desired signal band.

asy
Generally a smaller number of bits than required are converted using a

En
Flash ADC after the Filter. The resulting signal, along with the error
A
from the input to the filter. gi
generated by the discrete levels of the Flash, is fed back and subtracted

nee
This negative feedback has the effect of noise shaping the error due to the

rin
Flash so that it does not appear in the desired signal frequencies.
SC

g.n
A digital filter (decimation filter) follows the ADC which reduces the
sampling rate, filters off unwanted noise signal and increases the
resolution of the output.
e

Fig: Sigma-delta ADCs/ Over sampling converters

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5. i) Explain brifly Specifications for ADC and DAC

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5. ii) Explain the basic voltage to time conversion type of A to D converter.


[May/June 2013]
A/D USING VOLTAGE TO TIME CONVERSION:
The Block diagram shows the basic voltage to time conversion type of A to
D converter. Here the cycles of variable frequency source are counted for a fixed
period. It is possible to make an A/D converter by counting the cycles of a fixed-
frequency source for a variable period. For this, the analog voltage required to be
converted to a proportional time period.

ww
w.E
asy D En
Fig: A/D using voltage to time conversion
A
gi
As shown in the diagram, A negative reference voltage -VR is applied to

nee
an integrator, whose output is connected to the inverting input of the comparator.
The output of the comparator is at 1 as long as the output of the integrator Vo is

rin
SC

less than Va. At t = T, Vc goes low and switch S remains open. When VEN goes

g.n
high, the switch S is closed, thereby discharging the capacitor. Also the NAND
gate is disabled. The waveforms are shown here.

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PART - C

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UNIT V
SPECIAL FUNCTION ICs
PART A
1. State the need for current limiting in voltage regulators. (April/May
2014)
It is used to prevent the load current from increasing above a preset value

2. How does switched capacitor emulate resistor? (April/May 2014)


The value of this resistor decreases with increasing switching frequency or
increasing capacitance, as either will increase the amount of charge transferred

ww
from v2 to v1 in a given time.

w.E
3. Define line and load regulation of a regulator. (Nov/Dec 2014)

D
Line regulation is defined as the percentage change in the output voltage

asy
for a change in the input voltage. It is expressed in milli volts or as a
percentage of the output voltage.

En
A
Load regulation is defined as the change in output voltage for a change

voltage.
gi
in load current. It is expressed in millivolts or as a percentage of the output

nee
rin
SC

4. What are the different protection circuits inside the monolithic IC


regulator? (Nov/Dec 2014)
g.n
Short Circuit protection circuit, Voltage transient protection circuit,
Current foldback protection circuit e
5. List the types of multivibrators. Define it. (May/June 2014)
1. Monostable multivibrator is one which generates a single pulse of
specified duration in response to each external trigger signal. It has only one
stable state. Application of a trigger causes a change to the quasi-stable state.
An external trigger signal generated due to charging and discharging of the
capacitor produces the transition to the original stable state.
2.Astable multivibrator is a free running oscillator having two quasi-
stable states. Thus, there is oscillations between these two states and no
external signal are required to produce the change in state.
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6. What is opto coupler? Advantages? (May/June2014)


An opto-isolator, also called an optocoupler, photocoupler, or optical
isolator, is "an electronic device designed to transfer electrical signals by
utilizing light waves to provide coupling with electrical isolation between its
input and output". The main purpose of an opto-isolator is "to prevent high
voltages or rapidly changing voltages on one side of the circuit from damaging
components or distorting transmissions on the other side.
Advantages of opto-couplers:
Better isolation between the two stages.
Impedance problem between the stages is eliminated.

ww Wide frequency response.


Easily interfaced with digital circuit.

w.E Compact and light weight.

asy
eliminated.
D
Problems such as noise, transients, contact bounce, are

En
A
7. Mention some applications of 555 timer. (Nov/Dec 2013)
Oscillator
Pulse genearator
gi nee
Ramp and square wave generator
rin
SC

Mono-shot multivibrator
Burglar alarm g.n
Traffic light control
e
8. Give the formula for period of oscillations in an op-amp astable
circuit. (May/June2013)

9. Define duty cycle of a periodic pulse waveform. (May/June2013)


It is the ratio of the time during which the output is high to the total
period T
%Duty cycle=tHIGH/T×100

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10. What are the limitations of IC 723 general purpose


regulator?(Nov/Dec 2012)
No in-built thermal protection
It has no short circuit current limits

11. What is power amplifier?


The power amplifier is used to amplify an audio signal.It is required to
deliver a large amount of power and as such it has to handle large
current,inorder to achieve high power amplification.

ww
12. List the applications of 555 timer in monostable mode and Astable
mode

w.E
Monostable

D
Missing Pulse detector

asy
Linear ramp generator
Frequency divider
En
A
Pulse width modulation.
Astable mode of operation:
FSK generator
gi nee
Pulse-position modulator
rin
SC

13. What is a switching regulator? Advantages? g.n


Switching regulators are those which operate the power transistor as a high
frequency on/off switch, so that the power transistor does not conduct current
e
continuously. This gives improved efficiency over series regulators.
Advantages:
Greater efficiency is achieved as the power transistor is made to
operate as low impedance switch. Power transmitted across the
transistor is in discrete pulses rather than as a steady current flow.
By using suitable switching loss reduction technique, the switching
frequency can be increased so as to reduce the size and weight of
the inductors and capacitors.

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14. What are the advantages of switched capacitor filters?


(Nov/Dec2011)
Very high value of resistors can be easily simulated using small value
capacitors, of the order of 10pF.
The switched capacitor filters require no external reactive components
like inductors and capacitors.
Completely active filters can be easily obtained on a monolithic IC chip.
Good temperature stability, high accuracy and low cost.

15. Define video amplifier.

ww A video amplifier has to amplify signals over a wideband of frequencies, say


upto 20MHz. It is a RC coupled amplifier with bandwidth from d.c. to high

w.E
frequency upto few megahertz.

asy D
16. What is an isolation amplifier? Applications. [May16]

En
An isolation amplifier is an amplifier that offers electrical isolation between
A
its input and output terminals
Applications of Isolation amplifier.
gi nee
Floating pulse amplifier output voltage and current interface

rin
Instrumentation in high-noise environments
SC

g.n
Analogue from end processing
Medical instrumentation

17. What is the purpose of connecting a capacitor at the input and the
e
output side of an IC voltage regulator?[Nov15]
1. To stabilize the circuit operation
2. To reduce ripple on the output

18. Mention two applications frequency to voltage converter.[Nov15]


a. F-V convertors applications: Tachometer in motor speed control
b. Rotational speed measurement.

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19. Draw the block schematic of IC 555 timer. [Nov 16]

ww
w.E
asyD En
A
gi nee
rin
20. What is the function of a voltage regulator? Name few IC voltage
SC

regulators.[Nov16]

g.n
The voltage regulator is a specially designed circuit to keep the output voltage
constant. It does not remain exactly constant. It changes slightly due to changes
in certain parameters.
Adjustable Positive Voltage Regulator (LM317),
e
Practical Regulator using LM317,
IC 723 – General Purpose Regulator are few examples

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PART B
1. With necessary equations and diagram explain Multivibrators in detail
[Nov /Dec 2014]
Astable Multivibrator
The two states of circuit are only stable for a limited time and the circuit switches
between them with the output alternating between positive and negative
saturation values.

ww
w.E
asy D En
A
Astable multivibrator circuit
gi nee
Analysis of this circuit starts with the assumption that at time t=0 the output has

rin
just switched to state 1, and the transition would have occurred. An op-amp
SC

Astable multivibrator is also called as free running oscillator. The basic principle

g.n
of generation of square wave is to force an op-amp to operate in the saturation
region (±Vsat).
A fraction β =R2/(R1+R2) of the output is feedback to the positive input terminal
of op-amp. The charge in the capacitor increases & decreases upto a threshold
e
value called ±βVsat. The charge in the capacitor triggers the op-amp to stay
either at +Vsat or –Vsat. Asymmetrical square wave can also be generated with
the help of Zener diodes. Astable multi vibrator do not require a external trigger
pulse for its operation & output toggles from one state to another and does not
contain a stable state. Astable multi vibrator is mainly used in timing applications
& waveforms generators.

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Design
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor
as T=2RCln (R1+2R2)/R1
2. To simplify the above expression, the value of R1 & R2 should be taken as R2
= 1.16R Such that fo simplifies to fo =1/2RC.
3. Assume the value of R1 and find R2.
4. Assume the value of C & Determine R from fo =1/2R C
5. Calculate the threshold point from βVSATl = R1lVTl/ R1-R2 l/βVSATl w h e r e
β is the feedback ratio.

ww
Monostable Multivibrator using Op-amp

w.E
asy D En
A
gi nee
rin
SC

g.n
Mono stable Multi vibrator using Op-amp
e

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Input Output Waveform:


A multivibrator which has only one stable and the other is quasi stable state is
called as Monostable multivibrator or one-short multivibrator. This circuit is useful
for generating signal output pulse of adjustable time duration in response to a
triggering signal. The width of the output pulse depends only on the external
components connected to the opamp.
Usually a negative trigger pulse is given to make the output switch to other
state. But, it then return to its stable state after a time interval determining by
circuit components. The pulse width T can be given as T = 0.69RC. For
Monostable operation the triggering pulse width Tp should be less then T, the

ww
pulse width of Monostable multivibrator. This circuit is also called as time delay
circuit or gating circuit.

w.E
asy D En
A
gi nee
rin
SC

g.n
e
2. Explain the Pin description and explain the monostable and Astable
operation of operation of The 555 Timer IC: [April/ May 2015]
The 555 is a monolithic timing circuit that can produce accurate & highly stable
time delays or oscillation. The timer basically operates in one of two modes:
either
(i) Monostable (one - shot) multivibrator or

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(ii) Astable (free running) multivibrator


The important features of the 555 timer are these:
(i) It operates on +5v to +18 v supply voltages
(ii) It has an adjustable duty cycle
(iii) Timing is from microseconds to hours
(iv) It has a current o/p

ww
w.E
asy D En
Pin configuration of 555 timer
A
Pin description:
gi nee
Pin 1: Ground:All voltages are measured with respect to this terminal.
Pin 2: Trigger:The o/p of the timer depends on the amplitude of the external

rin
SC

trigger pulse applied to this pin.

g.n
Pin 3: Output:There are 2 ways a load can be connected to the o/p terminal either
between pin3& ground or between pin 3 & supply voltage(Between Pin 3 &
Ground ON load) (Between Pin 3 & + Vcc OFF load)
(i) When the input is low:The load current flows through the load connected
e
between Pin 3 & +Vcc in to the output terminal & is called the sink current.
(ii) When the output is high: The current through the load connected between Pin
3 & +Vcc (i.e. ON load) is zero. However the output terminal supplies currentto
the normally OFF load. This current is called the source current.
Pin 4: Reset: The 555 timer can be reset (disabled) by applying a negative pulse
to this pin. When the reset function is not in use, the reset terminal should be
connected to +Vcc to avoid any false triggering.
Pin 5: Control voltage: An external voltage applied to this terminal changes the
threshold as well as trigger voltage. In other words by connecting a potentiometer

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between this pin& GND, the pulse width of the output waveform can be varied.
When not used,the control pin should be bypassed to ground with 0.01 capacitor
to prevent anynoise problems.
Pin 6: Threshold: This is the non inverting input terminal of upper comparator
which monitors the voltage across the external capacitor.
Pin 7: Discharge: This pin is connected internally to the collector of transistor Q1.
When the output is high Q1 is OFF.
When the output is low Q is (saturated) ON.
Pin 8: +Vcc: The supply voltage of +5V to +18V is applied to this pin with respect
to ground.

ww
From the figure, three 5k internal resistors act as voltage divider providing bias
voltage of 2/3 Vcc to the upper comparator & 1/3 Vcc to the lower comparator. It

w.E
is possible to vary time electronically by applying a modulation voltage to the

(i) In the Stable state:

D
control voltage input terminal (5).

asy
En
The output of the control FF is high. This means that the output is low because of
A
power amplifier which is basically an inverter. Q = 1; Output = 0

gi
(ii) At the Negative going trigger pulse: The trigger passes through (Vcc/3) the

nee
output of the lower comparator goes high & sets the FF. Q = 1; Q = 0

rin
(iii) At the Positive going trigger pulse: It passes through 2/3Vcc, the output of the
SC

upper comparator goes high and resets the FF. Q = 0; Q = 1The reset input (pin

g.n
4) provides a mechanism to reset the FF in a manner which over rides the effect
of any instruction coming to FF from lower comparator.
e

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ww
w.E
asy D
Block Diagram of 555 Timer IC

En
A
Monostable Operation:[April/ May 2015]

gi nee
rin
SC

g.n
e

Connected as a Monostable Multivibrator

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Waveforms of monostable multivibrators


Initially when the output is low, i.e. the circuit is in a stable state, transistor Q1 is

ww
ON &capacitor C is shorted to ground. The output remains low. During negative
going trigger pulse, transistor Q1 is OFF, which releases the short circuit across

w.E
D
the external capacitor C &drives the output high. Now the capacitor C starts

asy
charging toward Vcc through RA. When the voltage across the capacitor equals
2/3 Vcc, upper comparator switches from low to high. i.e.Q = 0, the transistor Q1
= OFF ; the output is high.
En
A
gi
Since C is unclamped, voltage across it rises exponentially through R

nee
towards Vcc with a time constant RC (fig b) as shown in below. After the time
period, the upper comparator resets the FF,i.e. Q = 1, Q1 = ON; the output is

rin
low.[i.e discharging the capacitor C to ground potential (figc)]. The voltage across
SC

the capacitor as in fig (b) is given by


Vc = Vcc (1-e-t/RC)……. (1) g.n
Therefore At t = T, Vc = 2/3 Vcc
2/3 Vcc = Vcc(1-e-T/RC)
e
Or
T = RC ln (1/3)
Or
T = 1.1RC seconds ……………. (2)
If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately
discharged. The output now will be as in figure (d & e). If the reset is released
output will still remain low until a negative going trigger pulse is again applied at
pin 2.

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Applications of Monostable Mode of Operation:


(a) Frequency Divider:
The 555 timer as a monostable mode. It can be used as a frequency divider by
adjustingthe length of the timing cycle tp with respect to the time period T of the
trigger input. Touse the monostable multivibrator as a divide by 2 circuit, the
timing interval tp must be alarger than the time period of the trigger input. [Divide
by 2, tp> T of the trigger]By the same concept, to use the monostable
multivibrator as a divide by 3 circuit, tp must be slightly larger than twice the
period of the input trigger signal & so on, [ divide by 3tp> 2T of trigger]

ww
(b) Pulse width modulation:

w.E
asy D En
A
gi nee
rin
SC

g.n
Pulse Width Modulation e

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Pulse width of a carrier wave changes in accordance with the value of a incoming
(modulating signal) is known as PWM. It is basically monostable multivibrator. A
modulating signal is fed in to the control voltage (pin 5). Internally, the control
voltage is adjusted to 2/3 Vcc externally applied modulating signal changes the
control voltage level of upper comparator. As a result, the required to change the
capacitor up to threshold voltage level changes, giving PWM output.

(c) Pulse Stretcher:


This application makes use of the fact that the output pulse width (timing interval)
of the monostable multivibrator is of longer duration than the negative pulse width

ww
of the input trigger. As such, the output pulse width of the monostable
multivibrator can be viewed as stretched version of the narrow input pulse, hence

w.E
the name ―Pulse stretcher‖.

D
Often, narrow –pulse width signals are not suitable for driving an LED display,

asy
mainly because of their very narrow pulse widths. In other words, the LED may

En
be flashing but not be visible to the eye because its on time is infinitesimally small
A
compared to its off time. The 55 pulse stretcher can be used to remedy this

varied by changing the value of RA& C.


gi
problem. The LED will be ON during the timing interval tp = 1.1RAC which can be

nee
rin
SC

g.n
e
Pulse Stretcher
The 555 timer as an Astable Multivibrator:
An Astable multivibrator, often called a free running multivibrator, is
arectangular wave generating circuit. Unlike the monostable multivibrator, this
circuit does not require an external trigger to change the state of the output,
hence the name free running.

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However, the time during which the output is either high or low is determined by 2
resistors
and capacitors, which are externally connected to the 55 timer.

ww
w.E
Astable Multivibrator asy D En
A
gi nee
rin
SC

g.n
e

Waveforms of Astable multivibrator


The above figures show the 555 timer connected as an astable multivibrator and
its model graph
Initially, when the output is high:
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Capacitor C starts charging toward Vcc through RA & RB. However, as soon as
voltage across the capacitor equals 2/3 Vcc. Upper comparator triggers the FF &
output switches low.
When the output becomes Low:
Capacitor C starts discharging through RB and transistor Q1, when the voltage
across C equals 1/3 Vcc, lower comparator output triggers the FF & the output
goes high. Then cycle repeats. The capacitor is periodically charged &
discharged between 2/3 Vcc& 1/3Vcc respectively. The time during which the
capacitor charges from 1/3 Vcc to 2/3 Vcc equal to the time the output is high & is
given by

ww
tc = (RA+RB)C ln 2……………(1) Where [ln 2 = 0.69]= 0.69 (RA+RB) C

w.E
Where RA & RB are in ohms. And C is in farads.

asy D
Similarly, the time during which the capacitors discharges from 2/3 Vcc to 1/3 Vcc
is equal to the time, the output is low and is given by,

En
A
tc = RB C ln 2

gi
td = 0.69 RB C …………………..(2) where RB is in ohms and C is infarads.
Thus the total period of the output waveform is
nee
T = tc + td = 0.69 (RA+2RB) C …………….(3)
rin
SC

This, in turn, gives the frequency of oscillation as,f 0 = 1/T = 1.45/(RA+2RB)C


………(4)
g.n
Equation 4 indicates that the frequency f 0 is independent of the supply voltage
Vcc. Often the term duty cycle is used in conjunction with the astable
multivibrator. The duty cycle is the ratio of the time tc during which the output is
e
high to the total time period T. It is generally expressed as a percentage.
% duty cycle = (tc / T )* 100
% DC = [(RA+RB)/ /(RA+2RB)] * 100

3. Explain the IC 723 General Purpose Regulators in detail [May/June 2014]


IC 723 – General Purpose Regulator

1. Do not have the shot circuit


2. Output voltage is not adjustable
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These limitations can be overcomes in IC723.

1. Unregulated dc supply voltage at the input between 9.5V & 40V


2. Adjustable regulated output voltage between 2 to 3V.
3. Maximum load current of 150 mA (ILmax = 150mA).
4. With the additional transistor used, IL maxupto 10A is obtainable.
5. Positive or Negative supply operation
6. Internal Power dissipation of 800mW.
7. Built in short circuit protection.
8. Very low temperature drift.

ww
9. High ripple rejection.
The simplified functional block diagram can be divided in to 4 blocks.

w.E
1. Reference Generating block:

D
The temperature compensated Zener diode, constant current source & voltage

asy
reference amplifier together from the reference generating block. The Zener

En
diode is used to generate a fixed reference voltage internally. Constant current
A
source will make the Zener diode to operate at affixed point & it is applied to the

gi
Non – inverting terminal of error amplifier. The Unregulated input voltage ±Vcc is

nee
applied to the voltage reference amplifier as well as error amplifier.

rin
SC

2. Error Amplifier:

g.n
Error amplifier is a high gain differential amplifier with 2 input (inverting &Non
inverting).
The Non-inverting terminal is connected to the internally generated reference
voltage. The Inverting terminal is connected to the full regulated output voltage.
e

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Functional block diagram of IC723

ww
w.E
asy D En
A
gi nee
rin
SC

Pin diagram of IC723


g.n
3. Series Pass Transistor:
e
Q1 is the internal series pass transistor which is driven by the error amplifier. This
transistor actually acts as a variable resistor & regulates the output voltage. The
collector of transistor Q1 is connected to the Un-regulated power supply. The
maximum collector voltage of Q1 is limited to 36Volts. The maximum current
which can be supplied by Q1 is 150mA.

4. Circuitry to limit the current:


The internal transistor Q2 is used for current sensing & limiting. Q2 is normally
OFF transistor. It turns ON when the IL exceeds a predetermined limit. Low

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voltage, Low current is capable of supplying load voltage which is equal to or


between 2 to 7Volts.
Vload = 2 to 7V and Iload= 50mA

IC723 as a LOW voltage LOW current:

ww
w.E
asy D En
A
Typical circuit connection diagram

gi
R1 & R2 from a potential divider between Vref& Gnd.
nee
Voltage across R2 is connected to the Non – inverting terminal of the

rin
SC

regulator IC Vnon-inv = R2/(R1+R2) Vref


-inv = Vin
g.n
must also be equal to Vnon-inv Vo = Vnon-inv =R2/(R1+R2) Vref
R1 & R2 can be in the range of 1 KΩ to 10KΩ & value of R3 is given by R3 = R1ll
e
R2 =R1R2/(R1+R2) Rsc (current sensing resistor) is connected between Cs &
CL. The voltage
drop across Rsc is proportional to the IL.

load current
can be higher than 150mA.

circuit.
2) Vref

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IC723 as a HIGH voltage LOW Current:

ranges of 7 to 37 volts with a maximum load current of 150 mA.


– inverting terminal is now connected to Vref through resistance R3.

inverting terminal at the desired output. Vin = Vref =R2 /(R1+R2) V0


Vo = [1+R1/R2] Vin

Circuit current limiting Rsc =0.6/Ilimit

ww
w.E
IC723 as a HIGH voltage HIGH Current:

regulator
improve
to
its
asy D En current
A
sourcing
capacity.
gi nee
rin
SC

g.n
e
Typical circuit connection diagram

than 150mA.

V0= Vo = [1+R1/R2] Vin

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Rsc =0.6/Ilimit

Switching Regulators
Introduction
The switching regulator offers the advantages

begenerated from a single input voltage).

ww
The primary filter capacitor is placed on the input to the regulator to help filter out
the60 cycle ripple. If the output voltage is 12 volts and the input voltage is 24

w.E
volts then we must drop 12 volts across the regulator. At output currents of 10

asy D
amps this translates into120 watts (12 volts times 10 amps) of heat energy that
the regulator must dissipate in to heat.

En
A
gi nee
rin
SC

g.n
Switching regulator principle
e
The switching regulator is much more efficient than the linear regulator achieving
efficiencies as high as 80% to 95% in some circuits. The obvious result is smaller
heat sinks, less heat and smaller overall size of the power supply. The switching
regulator is really nothing more than just a simple switch. This switch goes on
and off at a fixed rate usually between 50 Khz to 100Khz as set by the circuit.

Operation:
Diode D1 has to be a Schottky or other very fast switching diode. Inductor
L1must be a type of core that does not saturate under high currents. Capacitor

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C1 is normally a low ESR(Equivalent Series Resistance) type. To understand the


action of D1 and L1, let‘s look at what happens when S1 is closed as indicated
below:

ww Switching operation of regulator

w.E L1, which tends to oppose the rising current, begins to generate an

D
electromagnetic field in its core. Diode D1 is reversed biased and is essentially

asy
an open circuit at this point. When S1 opens, the electromagnetic field that was
built up in L1 is now discharging and generating a current in the reverse polarity.

En
As a result, D1 is now conducting and will continue until the field in L1 is
A
gi
diminished. This action is similar to the charging and discharging of capacitor C1.

nee
The use of this inductor/diode combination gives us even more efficiency and
augments the filtering of C1.

rin
SC

Because the switching system operates in the 50 to 100 kHz region and

g.n
has an almost square waveform, it is rich in harmonics way up into the HF and
even the VHF/UHF region Four most commonly used switching converter types:
Buck: used the reduce a DC voltage to a lower DC voltage.
Boost: provides an output voltage that is higher than the input.
e
Buck-Boost (invert): an output voltage is generated opposite in polarity to the
input.
Fly back: an output voltage that is less than or greater than the input can be
generated, as well as multiple outputs.
Converters:
Push-Pull: A two-transistor converter that is especially efficient at low input
voltages.
Half-Bridge: A two-transistor converter used in many off-line applications.

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Full-Bridge: A four-transistor converter (usually used in off-line designs) that can


generate the highest output power of all the types listed.

Switching Regulator: [Nov/ Dec 2012]


An example of general purpose regulator is Motorola‘s MC1723. It can be used in
many different ways, for example, as a fixed positive or negative output voltage
regulator, variable regulator or switching regulator because of its flexibility. To
minimize the power dissipation during switching, the external transistor used
must be a switching power transistor.
To improve the efficiency of a regulator, the series pass transistor is used

ww
as a switch
rather than as a variable resistor as in the linear mode.

w.E ching

D
regulator. In such regulators the series pass transistor is switched between cut off

asy
& saturation at a high frequency which produces a pulse width modulated (PWM)
square wave output.

En
A
n average dc
output voltage.
gi nee
rin
SC

output
Differential & can approach 95%
g.n
e

Basic Switching regulator


A basic switching regulator consists of 4 major components,
1. Voltage source Vin
2. Switch S1
3. Pulse generator Vpulse

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4. Filter F1
1. Voltage Source Vin:
It may be any dc supply – a battery or an unregulated or a regulated voltage. The
voltage source must satisfy the following requirements.

switching regulator.

regulations.
o meet the minimum requirement of the regulator
system to be designed.

ww
failures.

w.E
2. Switch S1:

asy D
It is typically a transistor or thyristor connected as a power switch & is operated in

En
the saturated mode. The pulse generator output alternately turns the switch ON &
A
OFF

3. Pulse generator Vpulse:


gi nee
rin
It provides an asymmetrical square wave varying in either frequency or pulse
SC

width called frequency modulation or pulse width modulation respectively. The

g.n
most effective frequency range for the pulse generator for optimum efficiency 20
KHz. This frequency is inaudible to the human ear & also well within the switching
speeds of most inexpensive transistors &diodes.
the pulse wave form determines the relationship between the
e
input & output voltages. The duty cycle is the ratio of the on time ton, to the
period T of the pulse waveform.
Duty cycle = ton/(ton+toff) = ton/T =ton.f
Where ton = On-time of the pulse waveform toff=off-time of the pulse waveform
T = time period = ton + toff= 1/frequency or T = 1/f

require large filter components (inductors & capacitors).

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4. Filter F1:
It converts the pulse waveform from the output of the switch into a dc voltage.
Since this switching mechanism allows a conversion similar to transformers, the
switching regulator is often referred to as a dc transformer.
The output voltage Vo of the switching regulator is a function of duty cycle & the
input voltage Vin.
Vo is expressed as follows, Vo= ton Vin/T

proportional to the ON-time, ton for a given value of Vin. This method of changing
the output voltage by varying ton is referred to as a pulse width modulation.

ww
to the period T or directly proportional to the frequency of the pulse waveform.

w.E
This method of varying the output voltage is referred to as frequency modulation
(FM).

i) Step – Down
asy D En
A
ii) Step – Up
iii) Polarity inverting
gi nee
Monolithic Switching Regulator [μa78s40]:
rin
SC

The μA78S40 consists of a temperature compensated voltage reference, duty


cycle controllable oscillator with an active current limit circuit, a high gain
g.n
comparator, a high- current, high voltage output switch, a power switching diode
& an uncommitted op-amp. e
Important features of the μA78S40 switching regulators are:

Peak current to 1.5A without external resistors

The internal switching frequency is set by the timing capacitor CT, connected
between pin12 &ground pin 11. The initial duty cycle is 6:1. The switching
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frequency & duty cycle can be modified by the current limit circuitry, IPK sense,
pin14, 7 the comparator, pin9 & 10.

Comparator:
The comparator modifies the OFF time of the output switch transistor Q1 & Q2. In
the step– up & step down modes, the non-inverting input(pin9) of the comparator
is connected to thevoltage reference of 1.3V (pin8) & the inverting input (pin10) is
connected to the output terminalvia the voltage divider network.

ww
w.E
asy D En
A
gi nee
Functional block diagram of μA78S40

rin
SC

g.n
e

Pin diagram of Monolithic Switching Regulator [μa78s40]:


In the Inverting mode the non – inverting input is connected to both the voltage
eference & the output terminal through 2 resistors & the inverting terminal is
connected to ground.

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utput is in high state & has


no effect on the circuit operation.

higher than that at the non-inverting terminal, then the comparator output goes
low.
parator inhibits the turn on of the output switching
transistors. This means that, as long as the comparator output is low, the system
is in off time.

decreases.

ww uently, as the output current nears its maximum IoMAX, the off time
approaches its

w.E
minimum value. In all 3 modes (Step down, step up, Inverting), the current limit

&Vcc.

D
circuit is completed by connecting a sense resistor Rsc, between IPK sense

asy
En
nt limit circuit is activated when a 330mV potential appears across
A
Rsc.

current IPK, flows through it.


gi nee
rin The
SC

forward voltage drop, VD, across the internal power diode is used to determine

g.n
the value of inductor L off time & efficiency of the switching regulator. Another
important quantity used in the design of a switching regulator is the saturation
voltage Vs:
In the step down mode an ―output saturation volt‖ is 1.1V typical, 1.3VMAX.
e
In the step up mode an ―Output saturation volt‖ is 0.45V typical, 0.7 maximum.
The desired peak current value is reached; the current limiting circuit turns ON
&immediately terminates the ON time & starts OFF time.

the ON timeof the output is increased automatically.


If the IL decreased then Vout increased, to compensate for this, the OFF time of
the output is increased automatically.

(i) Step – Down Switching Regulator:


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-inverting terminal of the internal op-amp (pin9) is connected to the


1.3Vreference (pin8).

Their value should be such that the potential at the inverting input of the op-amp
should be equal to 1.3V ref when Vo is at its desired level. The output
capacitance Co is used for reducing the ripple contents in the output voltage. It
acts as a filter along with the inductor L.

ww
ripple percentage.

w.E
voltage coupled to the reference (pin8).

asy D En
A
gi nee
rin
SC

g.n
e
Step down convertor
(ii) Step – Up Switching Regulator:

ut is shorted & the collector current of Q1 flows


through L.

induced emf that appears across the inductor with polarities.

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Vo = Vin + VL

ww
w.E
asy D En
A
gi
Step up convertor

nee
rin
SC

g.n
e
With Q1 ON with Q1 oFF

Inverting Switching Regulator:


Inverting switching regulator converts a positive input voltage into a
negativeoutput voltage which is higher in magnitude.

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ww
w.E
4. Explain the following
D
Circuit diagram of inverting switching regulator

asy
En
Opto couplers/Opto Isolators [Nov/Dec 2013]
A
Fibre optic IC [May/June 2013]

in the same
gi nee
rin
SC

package.

complete electric isolation between them. This kind of isolation is providedg.n


between a low power control circuit& high power output circuit, to protect the
control circuit.
e
(i) Current Transfer Ratio:
It is defined as the ratio of output collector current (Ic) to the input forward
current(If)CTR = Ic/If * 100%. Its value depends on the devices used as source
&detector.
(ii) Isolation voltage between input & output: It is the maximum voltage which can
exist differentially between the input & output without affecting the electrical
isolation voltage is specified in K Vrms with a relative humidity of 40 to 60%.
(iii) Response Time:

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Response time indicates how fast an opto coupler can change its output state.
Response time largely depends on the detector transistor, input current & load
resistance.
(iv) Common mode Rejection:
Even though the opto couplers are electrically isolated for dc & low frequency
signals, an impulsive input signal (the signal which changes suddenly)can give
rise to a displacement current Ic= Cf*dv/dt. This current can flow between input &
output due to the capacitance Cf existing between input &output. This allows the
noise to appear in the output. Depending on the type of light source & detector
used we can get a variety of opto couplers.

ww
They are as follows,
(i) LED – Photodiode opto coupler:

w.E
asy D En
A
gi nee
rin
SC

photodiode is used as a detector.


g.n
high linearity. When the pulse at
the input goes high, the LED turns ON. It emits light. This light is focused on the
photodiode.
e
photodiode. As soon as the input pulse reduces to zero, the LED turns OFF & the
photocurrent through the photodiode reduces to zero. Thus the pulse at the input
is coupled to the output side.

(ii) LED – Phototransistor Opto coupler:

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ww
w.E
asy D En
A
gi
SCHEMATIC SYMBOL AND WAVEFORMS nee
rin
SC

in figure. An infrared LED acts as


a light source and the phototransistor acts as a photo detector.
g.n
additional amplification.
ns ON. The light emitted by
e
the LED is
focused on the CB junction of the phototransistor.

current for the


phototransistor.
flowing. As soon as the input
pulse reduces to zero, the LED turns OFF & the collector current of
phototransistor reduces to zero. Thus the pulse at the input is optically coupled to
the output side.

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the output is taken at


the collector of the phototransistor
Advantages of Opto coupler:

utput side does not get


coupled to the input side.

ww
Disadvantages:

w.E
Applications:

asy D
Opto couplers are used basically to isolate low power circuits from high power
circuits.

En
A
high power circuits.
gi nee
(i) AC to DC converters used for DC motor speed control
rin
SC

(ii) High power choppers


(iii) High power inverters
g.n
driving signals to a power transistor connected in a DC-DC chopper. e
Opto coupler IC:
The opto-couplers are available in the IC form MCT2E is the standard opto-
coupler IC which is used popularly in many electronic application.

connected between these pins.


radiation from the LED gets focused on the internal
phototransistor.

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value pull down resistance is connected from the Base to ground to improve the
sensitivity.
ram shows the opto-electronic-integrated circuit (OEIC) and the
major components of a fiber-optic communication facility.
-electronic-integrated circuit (OEIC) and the
major components of a fiber-optic communication facility.

ww
w.E
asy D En
A
gi nee
rin
SC

g.n
The block diagram of opto-electronic-integrated circuit (OEIC) e
5. i) With a neat diagram explain the Triangular Wave Generator Circuit:
[Nov/Dec 2012], [April May 2015].

This signal generator gives two waveforms: a triangle-wave and a square- wave.
The central component of this circuit is the integrator capacitor CI. Basically we
are interested in performing two functions on CI: charge it, discharge it - repeat
indefinitely. The output waveforms are shown here and it is apparent that a
square wave generator followed by an integrator acts as a triangular wave
generator.

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ww Circuit diagram of Triangular waveform generator

w.E
asy D En
A
gi nee
rin
SC

g.n
e
Output waveforms from generator

Basic triangular waveform generator


The triangle peaks and period may not accurately meet +/-10V swing at 100 us.
The main reason is that current source and thresholds are derived from Zener
diodes - not exactly the most accurate reference.
Saw-Tooth Wave Generator

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ww
w.E
asy D En
Saw-Tooth Wave Generator Circuit Diagram and output waveform
A
gi
The saw tooth wave oscillator which used the operational amplifier. The

nee
composition of this circuit is the same as the triangular wave oscillator basically
and is using two operational amplifiers.

rin
SC

At the circuit diagram above, IC(1/2) is the Schmitt circuit and IC(2/2) is the
Integration circuit. The difference with the triangular wave oscillator is to be
changing the time of the charging and the discharging of the capacitor. When theg.n
output of IC (1/2) is positive voltage, it charges rapidly by the small resistance
(R1) value.
e
(When the integration output voltage falls) When the output of IC(1/2) is
negative voltage, it is made to charge gradually at the big resistance(R2) value.
The output waveform of the integration circuit becomes a form like the tooth of
the saw. Such voltage is used for the control of the electron beam (the scanning
line) of the television.
When picturing a picture at the cathode-ray tube, an electron beam is
moved comparative slow. (When the electron beam moves from the left to the
right on the screen). When turning back, it is rapidly moved.(When moving from
the right to the left).

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Like the triangular wave oscillator, the line voltage needs both of the
positive power supply and the negative power supply. Also, to work in the
oscillation, the condition of R3>R4 is necessary. However, when making the
value of R4 small compared with R3, the output voltage becomes small. The near
value is good for R3 and R4.
The oscillation frequency can be calculated by the following formula.

With the circuit diagram,the oscillation frequency is as follows.


f = (1/2C (R1+R2))*(R3/R4)

ww
= (1/(2x0.1x10-6x(5.6x103+100x103))x(120x103/100x103)
= (1/(21.12x10-3))x1.2= 56.8 Hz

w.E
asy D
5. ii) Explain Sine Wave Generators (Oscillators) in detail.
Sine wave oscillator circuits use phase shifting techniques that usually employ

En
A
RC Phase Shift Oscillator
gi nee
rin
SC

g.n
e
RC Phase shift oscillator
RC phase shift oscillator using op-amp in inverting amplifier introduces the phase
shift of 180 between input and output. The feedback network consists of 3 RC
sections each producing 60 phase shift. Such a RC phase shift oscillator using
op-amp is shown in the figure. The output of amplifier is given to feedback
network. The output of feedback network drives the amplifier. The total phase
shift around a loop is 1800 of amplifier and 180 due to 3 RC sections, thus 360.

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This satisfies the required condition for positive feedback and circuit works as an
oscillator.

Oscillation criterion:

ww
w.E
D
The loop phase shift is –180° when the phase shift of each section is –60°, and

asy
this occurs when ω = 2πf = 1.732/RC because the tangent 60° = 1.73. The

En
magnitude of β at this point is (1/2)3, so the gain, A, must be equal to 8 for the
A
system gain to be equal to 1.
Wien Bridge Oscillator: gi nee
Figure give the Wien-bridge circuit configuration. The loop is broken at the
positive input,
rin
SC

g.n
and the return signal is calculated in Equation 2 below.

Wien Bridge Oscillator

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When ω = 2πf = 1/RC, the feedback is in phase (this is positive feedback), and
the gain is 1/3, so oscillation requires an amplifier with a gain of 3. When RF =
2RG, the amplifier gain is 3 and oscillation occurs at f = 1/2πRC. The circuit
oscillated at 1.65 kHz rather than 1.59 kHz with the component values shown in
Figure 3, but the distortion is noticeable.

ww
w.E
asy D En
A
gi nee
rin
SC

Wien Bridge Circuit Schematic with non-linear feedback


Figure 4 shows a Wien-bridge circuit with non-linear feedback. The lamp
g.n
resistance, RL, is nominally selected as half the feedback resistance, RF, at the
lamp current established by RF and RL. The non-linear relationship between the
lamp current and resistance keeps output voltage changes small. If a voltage
e
source is applied directly to the input of an ideal amplifier with feedback, the input
current will be:

Where vinis the input voltage, voutis the output voltage, and Zfis the feedback
impedance. If
the voltage gain of the amplifier is defined as:

And the input admittance is defined as:


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Input admittance can be rewritten as:

For the Wien Bridge, Zfis given by:

If Av is greater than 1, the input admittance is a negative resistance in parallel

ww
with an inductance.
The inductance is:

w.E
asy D
If a capacitor with the same value of C is placed in parallel with the input, the
circuit has a

En
A
natural resonance at:

gi
Substituting and solving for inductance yields: nee
rin
SC

If Av is chosen to be 3: Lin = R2C g.n


Substituting this value yields:
e
Or

Similarly, the input resistance at the frequency above is:


For Av = 3: Rin= − R

If a resistor is placed in parallel with the amplifier input, it will cancel some of the
negative resistance. If the net resistance is negative, amplitude will grow until
clipping occurs. Similarly, if the net resistance is positive, oscillation amplitude will
decay. If a resistance is added in parallel with exactly the value of R, the net
resistance will be infinite and the circuit can sustain stable oscillation at any

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amplitude allowed by the amplifier. Increasing the gain makes the net resistance
more negative, which increases amplitude. If gain is reduced to exactly 3 when
suitable amplitude is reached, stable, low distortion oscillations will result.
Amplitude stabilization circuits typically increase gain until suitable output
amplitude is reached. As long as R, C, and the amplifier are linear, distortion will
be minimal.

6. With a neat graph and circuit diagram explain Frequency to Voltage (F-V)
and voltage to frequency convertors (V-F) [May/June 2014], [Nov/Dec 2012]
-V convertors applications: Tachometer in motor speed control Rotational

ww
speed measurement.
Phase locked loop

w.E
asy D En
A
gi nee
rin
SC

Ideal characteristics of V-F convertor and F-V convertor

g.n
-V convertor produces an output voltage whose amplitude is a function of
input signal frequency.
-V convertor e

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ww
w.E
asy D En
Frequency to Voltage Convertor using VFC32 (V-F)
A
gi nee
rin
SC

g.n
e

F-V Convertor using VF32 and input and output characteristics


Input frequency is applied to comparator A.
Resistor R acts as feedback element.
Capacitor Ci enables charge-balancing,
High pass network conditions input signal
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For negative spike of V01, comparator COMP triggers one shot multivibrator with
threshold 7.5V The output of multivibrator closes the switch SW, for a time TH,
this causes voltage Vo to build up and inject thru R and this continues until
current out of summing input of op-amp is equal to that injected by Vo through R
continuously.
Vo=10-3 *TH *R*fi as TH =7.5 C /1X10-3
Ripple Voltage, Vr(max) =7.5 C /Ci
II. VOLTAGE TO FREQUENCY CONVERTOR
Principle: Charge balancing technique-the process of charging and discharging
results in frequency proportional to input signal F0= k Vi

ww
Operation: Op-amp A converts input Vi to current Ii = Vi/R into summing junction.

w.E
When switch SW is open the current flows into capacitor Ci and charges it, and

D
node voltage Vo1 produce ramp down.

asy
When V01 =0 CMP triggers and sends a triggering signal to one shot multivibrator

En
that closes the switch SW and turns transistor Q ON for time T H.
A
The threshold of mono shot = 7.5 V and T H= 7.5 C/10-3

gi
During TH , V01 ramps upward by amount Δ 01=(1mA-Ii) TH /Ci

nee
Time duration TL for vo1 to return to 0 is TL = CΔ 01/Ii
TL+TH = 1mA TH /Ii = T
rin
SC

F0=Vi/7.5 RC

g.n
e

Voltage-Frequency convertor using VF32 and its input output


characteristics

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7. Audio Amplifier LM380:


Power Audio Amplifier IC LM 380:
Introduction:
Small signal amplifiers are essentially voltage amplifier that supplies their loads
with larger amplifier signal voltage. On the other hand, large signal or power
amplifier supply a large signal current to current operated loads such as speakers
& motors. In audio applications, however, the amplifier called upon to deliver
much higher current than that supplied by general purpose op-amps. This means
that loads such as speakers & motors requiring substantial currents cannot be
driven directly by the output of general purpose op-amps. To handle it following is

ww
done
the output of the op-amp

w.E
asy D
1. Internally fixed gain of 50 (34dB)

En
2. Output is automatically self centering to one half of the supply voltage.
A
3. Output is short circuit proof with internal thermal limiting.

5. Supply voltage range (5 to 22V).


gi
4. Input stage allows the input to be ground referenced or ac

nee
6. High peak current capability.
rin
SC

7. High impedance.

g.n
e

Fig.5.48 Functional block diagram of Audio Power Amplifier

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ww
w.E
asy D
Fig.5.49 Pin diagram Of Power amplifier LM380

En
A
gi nee
rin
SC

g.n
e
Fig. Block diagram of LM380
LM380 circuit description:
It is connected of 4 stages,
(i) PNP emitter follower
(ii) Different amplifier
(iii) Common emitter

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(iv) Emitter follower


(i) PNP Emitter follower:

drives the PNP Q3-Q4 differential pair.


transistors Q1 & Q2 allows the input to be referenced
to ground i.e., the input can be direct coupled to either the inverting & non-
inverting terminals of the amplifier.
(ii) Differential Amplifier:
-Q4 is established by Q7, R3 & +V.

ww
establishes the collector current of Q9.

w.E amplifier is taken at the junction of Q4 & Q6

asy D
transistors & is applied as an input to the common emitter voltage gain.
(iii) Common Emitter amplifier stage:

En
A
a current source load.

gi nee
compensation & helps to establish the upper cutoff frequency of 100 KHz.

rin
SC

approximately the same as the current through R3.

g.n
that D1 & D2 have the same characteristics as the base-emitter junctions of Q11.
Therefore the current through Q10 & (Q11-Q12) is approximately equal to the
current through diodes D1 & D2.
e
(iv) (Output stage) - Emitter follower:

transistor Q11 & NPN transistor Q12 has the power capability of NPN transistors
but the characteristics of a PNP transistor.

so that the dc output voltage is stabilized at +V/2;

order of micro farad should be connected between the bypass terminal (pin 1) &
ground (pin 7).
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increased by using positive feedback.


Applications:
(i) Audio Power Amplifier:

ww Fig. 5.51 Connections of audio power amplifier

w.E
biasing, compensation & fixed gain.

asy D
inverting terminal may be either shorted to ground, connected to ground through
resistors & capacitors.

En
A
resistor or capacitor.
gi
inverting terminal may be either shorted to ground or returned to ground through

nee
nnected between the inverting terminal & ground if the

rin
SC

input has a high internal impedance.

g.n
terminal (pin 8)
to eliminate 5-to-10 MHz oscillation.
couples the output of the amplifier to the 8 ohms
e
loud speaker which acts as a load. The amplifier will amplify the Vin applied at
the non-inverting terminal.
(ii) LM 380 as a High gain amplifier:

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Fig.5.52 Circuit connections


internally fixed at 50. But it can be increased by using the
external components.

to obtain a gain 200.


(iii) LM 380 as a variable Gain:
50, it is possible to obtain a variable gain up to
50 by connecting a potentiometer between the input terminals.

ww
w.E
Fig. Circuit connections

asy D
(iv) LM 380 as a Bridge Audio Power Amplifier:

En
A
gi nee
rin
SC

Fig. Circuit connections


g.n
power than what is provided by a single
LM380 amplifier, then 2 LM380 chips can be used in the bridge configuration.
e
single LM380 amplifier.
output will increase by four times that of a
single LM380 amplifier. The pot R4 is used to balance the output offset voltages
of the two chips.
(v) Intercom system using LM 380:

microphone.

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of transformer T.

ww
Fig. Talk mode

w.E
asy D En
A
gi nee
rin
SC

Fig. Listen mode g.n


e

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PART - C

ww
w.E
D
asy
En
A
gi nee
rin
SC

g.n
e

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D
asy
En
A
gi nee
rin
SC

g.n
e

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asy
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A
gi nee
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g.n
e

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asy
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g.n
e

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asy
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g.n
e

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UNIVERSITY QUESTIONS:

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2016.


Fourth Semester
Electronics and Communication Engineering
EC6404- LINEAR INTEGRATED CIRCUITS
(Common to Medical Electronics and Robotics and Automation Engineering)
(Regulation 2013)
Time: Three hours Maximum : 100 marks
Answer ALL question.

ww
1.
PART - A (10×2=marks)
Draw the block diagram of a general opamp.
2.
w.E Draw the circuit diagram of a symmetrical emitter coupled differential
amplifier.
3.
asy D
For the opamp shown in figure determine the voltage gain.

En
A
gi nee
rin
SC

g.n
4. Draw the circuit diagram of a peak detector with waveforms. e
5. Draw the block diagram of IC 566 VCO (Voltage Controlled Oscillator).
6. Enlist any four applications of NE 565 PLL.
7. What are the advantages of inverted R – 2R (current type) ladder D/A
converter over R – 2R (voltage type) D/A converter?
8. What is the need for electronic switches in D/A converter.
9. Draw the block schematic of IC 555 timer.
10. What is the function of a voltage regulator? Name few IC voltage
regulators.

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PART B – (5 × 16 = 80 marks)
11. (a) (i) Explain the significance of virtual ground in an opamp (6)
(ii) With diagram explain the operation of an inverting amplifier in closed
loop configuration. Obtain the expression for closed loop gian. (6)
(iii) Assuming a slew rate for 741 ic is 0. 5 v/ µ s. What is the maximum
undistorted sinewave that can be obtained for 12 v peak. (4)
Or
( b) (i) Explain the operation of a current mirror circuit. (6)
(ii) Compare the features of ideal and practical opamp circuit. (6)
(iii) A differential has CMRR = 1000. Differential inputs V 1 = 1100 µ u and V2

ww =900 µ u. Calculate the difference in output voltage if the differential gain AD


= 25000(4)

w.E
12. (a) (i) Differentiate between low pass, high pass, band pass and band reject

(6)

D
filter. Sketch the frequency plot.

asy
En
(ii) Design a second order low pass Butter worth filter for a cut off frequency of 1
A
KHz.(10)

(b) Write short notes on:


gi Or

nee
(i) Clipper and clamper circuits.
rin
SC

(10)
(ii) Integrater.
g.n (6)
13. (a) Explain the operation of a variable transconductance multiplier.
(16)
Or
e
(b) (i) With block schematic explain the working principle of PLL IC NE 565.
(12)
(ii) Brief the application of PLL IC for frequency multiplication. (4)
14. (a) (i) With a neat sketch the working principle of flash type A/D converter.
(10)
(ii) An 8 bit A/D converter accepts an input voltage signal of range 0 to 10 u.
(iii)What is the minimum value of the input voltage required to generate a change if 1
LSB?(3)

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(iv) What input voltage will generate all ‗1‘s at A/D converter output
(3)
Or
(b) With functional block diagram explain A/D converter using voltage to time
converter with input and output waveforms. (16)
15. (a) Write a technical note on:
(8+8)
(i) Isolation amplifier
(ii) opto coupler.
Or

ww (b) (i) Discuss the functionalities and working of switched mode power
supply.(12)

w.E (ii) Design a monostable multivibrator using 555 time for a pluse period of 2
ms. (4)

asy D En
A
gi nee
rin
SC

g.n
e

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B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2016.


Third Semester
Electronics and Communication Engineering
EC6404- LINEAR INTEGRATED CIRCUITS
(Common to Medical Electronics and Robotics and Automation
Engineering)
(Regulation 2013)
Time: Three hours Maximum : 100
marks

ww Answer All Question.


PART A- (10×2=marks)

w.E
1. Find the maximum frequency for sine wave output voltage 10 V peak to peak

D
with an op-amp whose slew rate is 1 µs.

asy
2. Differentiate the ideal and practical characteristics of an op-amp.

En
3. Calculate the output voltage for the circuit shown below:
A
gi nee
rin
SC

g.n
4. Draw the circuit diagram of a comprarator. Mention is applications.
5. What is a four quadrant multiplier ?
e
6. Draw the circuit diagram of a PLL circuit using as a FM detector.
7. A 12 bit D/A converter has resolution of 20 m V/LSB. Find the full scale output
voltage.
8. Draw the binary ladder network of DAC. If the value of the smaller resistance
is 10 k , what is the value of the other resistance ?
9. A Hartely oscillator has L1 = 10 mH, L2 = mH and C = 200 Pf. Calculate the
frequency of oscillation.
10. What is an isolation amplifier? Mention its applications.

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PART – B (5 × 16 = 80 Marks)
11. (a) (i) With a schematic diagram, explain the effect of R E on CMRR in
differential amplifier. (4)
(ii) Discuss about the methods to improve CMRR (12)

OR
(b) (i) Write a note on stability criteria and frequency compensation technique
applied in op-amp. (12)
(ii) A non-inverting amplifier with a gain of 300 having an impact offset voltage of

ww± 3 mV. Find the output voltage when the input is 0.01 ωt volt.
12. (a) (i) Draw the circuit diagram of an instrumentation amplifier and explain its
(4)

w.E
operation. List few applications. (12)

asy D
(ii) How an op-amp can be used as an log amplifier ?

En
OR
(b) (i) Design a second order high pull Butter worth filter having cut off frequency
(4)
A
of 5kHz. (6)

principle of full wave rectifier.


gi
(ii) What is a precision rectifier. With circuit schematic explain the working

nee (6)

rin
(iii) Determine the output voltage for the following circuit shown in figure (4)
SC

g.n
e
13. (a) Explain the working principle of four quadrant variable form
transconductance Multiplier. (16)
OR
(b) (i) Discuss the principle of operation of NE 565 PLL circuit (10)
(ii) How can PLL be modeled as a frequency multiplier? (6)
14. (a) (i) Explain the successive approximnation type A/D converter. (12)
(ii) Narrate the functions of analog switches. (4)
OR
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(b) (i) State the significance of using high speed sample and hold circuits.
Explain its working principle. (12)
(ii) Compare the performance of various DACS. (4)
15. (a) (i) Briefly write the working principle and functionalities of LM 380 audio
amplifier. (8)
(ii) Draw the schematic of a linear IC saw tooth waveform generator and
explain the circuit operation. (8)
OR
(b) (i) Summarise the working principle of IC 723 general purpose voltage
regulator.(12)

ww (ii) A 555 timer is configured in actable mode with R A = 2 k ohm RB = 6 k ohm


and C = 0.1 µF. Determine the frequency of oscillation. (4)

w.E
asy D En
A
gi nee
rin
SC

g.n
e

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B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015.


Fourth Semester
Electronics and Communication Engineering
EC6404- LINEAR INTEGRATED CIRCUITS
(Common to Medical Electronics and Robotics and Automation
Engineering)
(Regulation 2013)
Time: Three hours Maximum : 100 marks

Answer ALL question.

ww PART - A (10×2= 20 marks)


1. Mention two advantages of active load over passive load in an operational

w.E
amplifier.

D
2. Define input bias current and input offset current of an operational amplifier.

asy
3. Determine the output voltage for the circuit shown in Figure 1 when
(a) Vin = -2V and

En
A
(b) Vin = 3V

gi nee
rin
SC

g.n
4. Plot the transfer characteristics of the circuit shown in Figure 2, The OPAMP
e
saturates at ± 12V.

5. Define:
(a) Capture range and

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(b) Look range of Phase Locked Loop (PLL).


6. Mention two applications of analog multiplier.
7. Determine the number of comparators and resistors required for 8 bit fish type
ADC.
8. Mention two advantages of R-2R ladder type Digital to Analog Converter
when compared to weighted resistor type Digital to Analog Converter.
9. What is the purpose of connecting a capacitor at the input and the output side
of an IC voltage regulator?
10. Mention two applications frequency to voltage converter.

ww PART - B (5×6=80 marks)

w.E
11. (a) With a neat diagram, explain the input side of the internal circuit diagram
of IC741.

(b)
asy D En
OR
What is the need for frequency compensation in an OPAMP? With a
A
suitable ilustration, explain the pole-zero frequency compensation technique.
12. (a)
gi
(i) With a neat circuit diagram, explain the working of precision rectifier.
(8)
nee
(ii)
rin
Explain the application of operational amplifier as differentitator.
SC

(8)

g.n
(b) (i) Mention two advantages of active filter over passive filter. Also design
a second order low pass filter uwsing operational amplifier for the upper cut
off frequency of 2 kHz. Assume the value of capacitor 0.1µ F.
(8)
e
(ii) With a neat circuit diagram explain the working of voltage to current
converter.(8)
13. (a) Derive the expression for the capture range and lock range of Phase
Locked Loop.
OR
(b) Explain the application of Phase Locked Loop as
(i) Frequency synthesizer
(ii) AM demodulator and
(iii) FM demodulator
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14. (a) With a block diagram, explain the working of Successive Approximation
type Analog to Digital Converter. Also determine the conversion time of 8 bit
and 16 bit Successive Approximation type Analog to Digital Converter if its
clock frequency is 50 Hz.
OR
(b) With a neat block diagrame, explain the working of two bit flash type
analog to digital Converter

15. (a) With a neat functional diagram, explain the working of 555 timer as
monostable multivibrator and derive an expression for the frequency

ww oscillation with relevant wave forms.


OR

w.E
(b) With a neat circuit diagram, explain the working of linear voltage regulator

asy D
using operational amplifier

En
A
gi nee
rin
SC

g.n
e

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B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2015.


Fourth Semester
Electronics and Communication Engineering
EC6404- LINEAR INTEGRATED CIRCUITS
(Common to Medical Electronics and Robotics and Automation
Engineering)
(Regulation 2013)
Time: Three hours Maximum : 100
marks

ww Answer ALL question.


PART - A (10×2= 20 marks)

w.E
1. A differential amplifier has a differential voltage gain of 2000 and a

D
common mode gain of 0.2 Determine the CMMR in dB.

asy
2. Define Slew rate and what causes the slew rate?

En
3. What is hysteresis and mention the purpose of hysteresis in a
A
comparator?

gi
4. What is the difference between normal rectifier and precision rectifier

nee
5. How do you convert a basic multiplier to a squaring and square root
circuit?
rin
SC

6. What are the applications of PLL for the AM detection?


7. What would be produced by a DAC, whose output range is 0 to 10 V and
g.n
whose input binary numbers is 101111oo (for a 8 bit DAC)?
8. What is over sampling?
9. State the two conditions for oscillation.
e
10. Draw the functional block diagram of 723 regulator.

PART - B (5×16= 80 marks)


11. (a) (i) With simple schematic of differential amplifier, explain the function
of Operational Amplifier. (8)
(ii) Briefly explain about constant current sources. (8)
(b) (i) Briefly explain the techniques used for frequency compensation. (12)
(ii) How do the open loop gain and the closed loop gain of an op-amp differ?
(4)
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12. (a) (i) Determine the rate of change of the output voltage in response to
the first input pulse as shown below for the integrator. The output after the
first pulse. Draw the output waveform. (8)

(ii) Explain in detail about the V to I and I to V converters. (8)


(b) (i) With neat diagram explain the operation of Schmitt trigger. (8)

ww (ii) Design a wideband pass filter having f L = 400 Hz, fH =2kHz and pass

w.E
band gain of 4. Find the value of Q of the filter. (8)

asy D
13. (a) (i) With neat simplified internal diagram, explain the working principle
of Operational Transconductance Amplifier (OTA).
(ii) Explain the application of CCO for FM generation.
Or
En
(10)
(6)
A
gi
(b) Define capture range and lock range. Explain the process of capturing the

nee
lock and also derive for capture range and lock range. (16)

rin
SC

14. (a) Explain in detail about the following Digital to Analog conversion
techniques.
(i) R-2R ladder type DAC g.n (8)
(ii) Weighted resistor DAC
(b) With neat internal diagram, explain the following.
(8)
e
(i) Dual slope ADC (8)
(ii) Successive Approximation (8)
15. (a) (i) Design a phase shift oscillator to oscillate at 100 Hz. (6)
(ii) Describe Monostable multivibrator with necessary diagrams and
derive for ON time and recovery time. (10)
Or
(b) (i) Briefly describe about monolithic switching regulators (10)
(ii) Write short notes on voltage to frequency converters. (6)

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