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AN-9738
Design Guideline on 150W Power Supply for LED
Street Lighting Design Using FL7930B and FAN7621S
Introduction
This application note describes a 150W rating design in the front end and the LLC SRC DC-DC converter in the
guideline for LED street lighting. The application design back end. FL7930B and FAN7621S achieve high efficiency
consists of CRM PFC and LLC SRC with high power factor with medium power for 150W rating applications where
and high power conversion efficiency using FL7930B and CRM and LLC SRC operation with a two-stage shows best
FAN7621S. To verify the validity of the application board performance. CRM boost PFC converters can achieve better
and scheme, a demonstration board 150W (103V/1.46A) efficiency with light and medium power rating than
AC-DC converter was implemented and its results are Continuous Conduction Mode (CCM) boost PFC
presented in this application note. In CRM active PFC, the converters. These benefits result from the elimination of the
most popular topology is a boost converter. This is because reverse-recovery losses of the boost diode and Zero-Current
boost converters can have continuous input current that can Switching (ZCS). The LLC SRC DC-DC converter achieves
be manipulated with peak current mode control techniques higher efficiency than the conventional hard switching
to force peak current to track changes in line voltage. The converter. The FL7930B provides a controlled on-time to
FAN7930B is an active Power Factor Correction (PFC) regulate the output DC voltage and achieves natural power
controller for boost PFC applications that operate in critical factor correction. The FAN7621S includes a high-side gate
conduction mode (CRM). Since it was first introduced in driver circuit, accurate current-controlled oscillator,
early 1990s, LLC-SRC (series resonant converter) has frequency -limit circuit, soft-start, and built-in protections.
became a most popular topology because of its outstanding The high-side gate drive circuit has a common-mode noise
performance in areas such as the output regulation of cancellation capability, which guarantees stable operation
switching frequency, ZVS capability for entire load range, with excellent noise immunity. Using Zero Voltage
low turn-off current, small resonant components using the Switching (ZVS) dramatically reduces switching losses and
integrated transformer, zero current switching (ZCS), and no significantly improves efficiency. ZVS also reduces
reverse recovery loss on secondary rectifier. Figure 1 shows switching noise noticeably, which allows a small-sized
the typical application circuit, with the CRM PFC converter Electromagnetic Interference (EMI) filter.
IL ID
VLINE L VOUT
VIN IDS
Line Filter
The fundamental idea of BCM PFC is that the inductor where VIN,PK is the amplitude of the line voltage and fLINE is
current starts from zero in each switching period, as shown the line frequency.
in Figure 3. When the power transistor of the boost Figure 4 shows how the MOSFET on-time and switching
converter is turned on for a fixed time, the peak inductor frequency change as output power decreases. When the load
current is proportional to the input voltage. Since the current decreases, as shown in the right side of Figure 4, the peak
waveform is triangular; the average value in each switching inductor current diminishes with reduced MOSFET on-time
period is proportional to the input voltage. In a sinusoidal and, therefore, the switching frequency increases. Since this
input voltage, the input current of the converter follows the can cause severe switching losses at light-load condition and
input voltage waveform with very high accuracy and draws too-high switching frequency operation may occur at
a sinusoidal input current from the source. This behavior startup, the maximum switching frequency of FL7930B is
makes the boost converter in BCM operation an ideal limited to 300kHz.
candidate for power factor correction.
IL
Average of input
current
VGS
π ⋅ Io
I ac = sin(ωt ) (3)
2
2 4n ⋅ Vo
8n sin(ωt )
Rac = VRO F n ⋅ VRI F 2n ⋅ Vo
= π
Ro (7)
M = F = =
π
2
F
Vd Vd 4 V Vin
in
sin(ωt )
π 2
By using the equivalent load resistance, the AC equivalent (8)
circuit is obtained, as illustrated in Figure 10, where VdF and ω 2
() (m − 1)
VROF are the fundamental components of the driving voltage, ωo
=
Vd and reflected output voltage, VRO (nVRI), respectively. ω2 ω ω2
( 2 − 1) + j ( 2 − 1)(m − 1)Q
ωp ωo ωo
pk
I ac where:
8n 2 Lp
L p = Lm + Lr , Rac = Ro , m =
π 2
Lr
Lr 1 1 1
Q= , ωo = , ωp =
Cr Rac Lr Cr L p Cr
As can be seen in Equation (8), there are two resonant
frequencies. One is determined by Lr and Cr, while the other
is determined by Lp and Cr.
Equation (8) shows the gain is unity at resonant frequency
(ωo), regardless of the load variation, which is given as:
π ⋅ Io
I ac = sin( wt )
2 2n ⋅ Vo ( m − 1) ⋅ ω p
2
M = = = 1 at ω = ωo (9)
Vin ωo 2 − ω p 2
4Vo
VRI F = sin( wt )
π The gain of Equation (8) is plotted in Figure 11 for different
Q values with m=3, fo=100kHz, and fp=57kHz. As observed
in Figure 11, the LLC resonant converter shows gain
Figure 9. Derivation of Equivalent Load Resistance Rac
characteristics that are almost independent of the load when
the switching frequency is around the resonant frequency, fo.
This is a distinct advantage of LLC-type resonant converter
over the conventional series resonant converter. Therefore,
it is natural to operate the converter around the resonant
frequency to minimize the switching frequency variation.
The operating range of the LLC resonant converter is be divided into two categories; rising current when the
limited by the peak gain (attainable maximum gain), which MOSFET is on and output diode current when the MOSFET
is indicated with ‘Q’ in Figure 11. Note that the peak is off, as shown in Figure 12.
voltage gain does not occur at fo or fp. The peak gain
frequency, where the peak gain is obtained, exists between
fp and fo, as shown in Figure 11. As Q decreases (as load
decreases), the peak gain frequency moves to fp and higher
peak gain is obtained. Meanwhile, as Q increases (as load
increases), the peak gain frequency moves to fo and the peak
gain drops; the full-load condition should be worst case for
the resonant network design.
1 1
fp = fo =
2π L p Cr 2π Lr Cr
Figure 12. Inductor and Input Current
Lr / Cr
Q=
Rac
Because switching frequency is much higher than line
frequency, input current can be assumed to be constant
during a switching period, as shown in Figure 133.
M@ fo =1
[STEP-2] Boost Inductor Design When selecting wire diameter and strands; current density,
window area (AW, refer to Figure 14) of the selected core,
The boost inductor value is determined by the output power and fill factor need to be considered. The winding sequence
and the minimum switching frequency. The minimum of the boost inductor is relatively simple compared to a DC-
switching frequency must be higher than the maximum DC converter, so fill factor can be assumed about 0.2~0.3.
audible frequency band of 20kHz. Minimum frequency near
20kHz can decrease switching loss with the cost of Layers cause the skin effect and proximity effect in the coil,
increased inductor size and line filter size. Too-high so real current density may be higher than expected.
minimum frequency may increase the switching loss and
make the system respond to noise. Selecting in the range of
about 30~60kHz is a common choice; 40~50kHz is
recommended with FL7930B.
The minimum switching frequency may appear at minimum
input voltage or maximum input voltage, depending on the
output voltage level. When PFC output voltage is less than
430V, minimum switching appears at the maximum input
voltage (see Fairchild application note AN-6086). Inductance
is obtained using the minimum switching frequency:
L=
(
η ⋅ 2 VLINE )2 [H]
2 VLINE (13)
4 ⋅ f SW ,MIN ⋅ POUT ⋅ 1 +
V − 2 V Figure 14. Typical B-H Curves of Ferrite Core
OUT LINE
I L ,PK 7.392 Auxiliary winding must give enough energy to trigger ZCD
I L ,RMS = = = 3.017 [ A ]
6 6 threshold to detect zero current. Minimum auxiliary winding
turns are given as:
I L,RMS 3.017
I L ,DENSITY = = = 7.68 [ A / mm2 ]
2
π ⋅ (0.1 / 2 )2 ⋅ 50 1.5 V ⋅ N BOOST
π ⋅ wire ⋅ Nwire
d
2 N AUX ≥ [ Turns] (18)
VOUT − 2 VLINE,MAX
[STEP-3] Inductor Auxiliary Winding Design where 1.5V is the positive threshold of the ZCD pin.
Figure 16 shows the application circuit of the nearby ZCD To guarantee stable operation, it is recommended to add 2~3
pin from auxiliary winding. turns to the auxiliary winding turns calculated in Equation
(18). However, too many auxiliary winding turns raise the
negative clamping loss at high line and positive clamping
loss at low line.
N AUX
2 VLINE,MAX − 0.65 V
N (20)
RZCD ≥ [ Ω]
BOOST
3 mA
Figure 18. Input Current Deterioration by Fast Control Figure 20. Inductor Current at AC Voltage Zero
If on-time is controlled constantly over one AC period, the Negative inductor current creates zero-current distortion and
inductor current peak follows AC input voltage shape and degrades the power factor. Improve this by extending turn-
achieves good power factor. Off-time is basically inductor on time at the AC line input near the zero cross.
current reset time due to Boundary Mode and is determined
by the input and output voltage difference. When input Negative auxiliary winding voltage, when the MOSFET is
voltage is at its peak, the voltage difference between input turned on, is linearly proportional to the input voltage.
and output voltage is small and long turn-off time is Sourcing current generated by the internal negative
necessary. When input voltage is near zero, turn-off time is clamping circuit is also proportional to sinusoidal input
short, as shown in Figure 19 and Figure 20. Though voltage. That current is detected internally and added to the
inductor current drops to zero, the minor delay is explained internal sawtooth generator, as shown in Figure 21.
above. The delay can be assumed as fixed when AC is at
line peak and zero. Near AC line peak, the inductor current
decreasing slope is slow and inductor current slope is also
slow during the ZCD delay. The amount of negative current
is not much higher than the inductor current peak. Near the
AC line zero, inductor current decreasing slope is very high
and the amount of negative current is higher than positive
inductor current peak because input voltage is almost zero.
The current that comes from the ZCD pin, when auxiliary where:
voltage is negative, depends on RZCD. The second role of tON,MAX is calculated by Equation (14);
RZCD is also related to improving the Total Harmonic tON,MAX1 is maximum on-time programming 1;
Distortion (THD). NBOOST is the winding turns of boost inductor; and
NAUX is the auxiliary winding turns.
The third role of RZCD is making the maximum turn-on time
adjustment. Depending on sourcing current from the ZCD RZCD calculated by Equation (20) is normally lower than the
pin, the maximum on-time varies as in Figure 23. value calculated in Equation (21). To guarantee the needed
turn on-time for the boost inductor to deliver rated power,
the RZCD from Equation (20) is normally not suitable. RZCD
should be higher than the result of Equation (21) when
output voltage drops as a result of low line voltage.
When input voltage is high and load is light, not much input
current is needed and control voltage of VCOMP touches
switching stop level, such as if FL7930B is 1V. However, in
some applications, a PFC block is needed to operate
normally at light load. To compensate control range
correctly, input voltage sensing is necessary, such as with
Figure 23. Maximum On-Time Variation vs. IZCD
Fairchild’s interleaved PFC controller FAN9612, or special
With the aid of IZCD, an internal sawtooth generator slope is care on sawtooth generator is necessary. To guarantee
changed and turn-on time varies as shown in Figure 24. enough control range at high line, clamping output voltage
lower than rated on the minimum input condition can help.
Figure 24. Internal Sawtooth Wave Slope Variation A choice close to the value calculated by the control range is
RZCD also influences control range. Because FL7930B recommended. 39kΩ is chosen in this case.
doesn’t detect input voltage, voltage-mode control value is
determined by the turn-on time to deliver the needed current
to boost output voltage. When input voltage increases,
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 • 4/20/11 10
AN-9738 APPLICATION NOTE
[STEP-5] Output Capacitor Selection (Design Example) With the ripple specification of 8Vp-p,
The output voltage ripple should be considered when the capacitor should be:
selecting the output capacitor. Figure 25 shows the line I OUT 0.465
CO ≥ = = 185 [ µF ]
frequency ripple on the output voltage. With a given 2 π ⋅ f LINE ⋅ ∆VOUT ,ripple 2 π ⋅ 50 ⋅ 8
specification of output ripple, the condition for the output
capacitor is obtained as: Since minimum allowable output voltage during one cycle
line (20ms) drop-outs is 330V, the capacitor should be:
I OUT 2 × POUT ⋅ t HOLD
C OUT ≥ [f] CO ≥
2 π ⋅ f LINE ⋅ ∆VOUT ,RIPPLE
(22) (V OUT − 0 .5 ⋅ ∆ V OUT ,ripple )2 − V OUT ,MIN
2
−3
where VOUT,RIPPLE is the peak-to-peak output voltage ripple 2 ⋅ 200 ⋅ 20 × 10
= = 110 [ µ F ]
specification. (430 − 0 .5 ⋅ 8 )2 − 330 2
The output voltage ripple caused by the ESR of the To meet both conditions, the output capacitor must be
electrolytic capacitor is not as serious as other power larger than 140µF. A 240µF capacitor is selected for the
converters because output voltage is high and load current is output capacitor.
small. Since too much ripple on the output voltage may The voltage stress of selected capacitor is calculated as:
cause premature OVP during normal operation, the peak-to-
peak ripple specification should be smaller than 15% of the VOVP,MAX 2.730
VST ,COUT = ⋅VOUT = ⋅ 430 = 469.5 [V ]
VREF 2.500
nominal output voltage.
The hold-up time should also be considered when
determining the output capacitor as: [STEP-6] MOSFET and DIODE Selection
2 ⋅ POUT ⋅ t HOLD Selecting the MOSFET and diode requires extensive
COUT ≥ [f]
(VOUT − 0.5 ⋅ ∆VOUT,RIPPLE) 2
− VOUT,MIN 2 (23) knowledge and calculation regarding loss mechanisms and
gets more complicated if proper selection of a heatsink is
where tHOLD is the required hold-up time and VOUT,MIN is the added. Sometimes the loss calculation itself is based on
minimum output voltage during hold-up time. assumptions that may be far from reality. Refer to industry
resources regarding these topics. This note shows the
Idiode voltage rating and switching loss calculations based on a
linear approximation.
The voltage stress of the MOSFET is obtained as:
VOVP ,MAX
VST ,Q = ⋅ VOUT + VDROP ,DOUT [ V ] (25)
VREF
( )
PQ ,CON = I Q ,RMS 2 ⋅ RDS ,ON [ W ] (27)
where IQ,RMS is the RMS value of MOSFET current, The average diode current and power loss are obtained as:
PQ,CON is the conduction loss caused by MOSFET current,
I OUT
and RDS,ON is the ON resistance of the MOSFET. I DOUT ,AVE = [ A] (31)
η
On resistance is described as “static on resistance” and
varies depending on junction temperature. That variation PDOUT = VDROP,DOUT⋅ I DOUT,AVE [W ] (32)
information is normally supplied as a graph in the datasheet where VDROP,DOUT is the forward voltage drop of diode.
and may vary by manufacturer. When calculating
conduction loss, generally multiply three by the RDS,ON for
more accurate estimation.
(Design Example) Internal reference at the feedback pin is
The precise turn-off loss calculation is difficult because of 2.5V and maximum tolerance of OVP trigger voltage is
the nonlinear characteristics of MOSFET turn-off. When 2.730V. If Fairchild’s FDPF17N60NT MOSFET and
piecewise linear current and voltage of MOSFET during FFPF08H60S diode are selected, VD,FOR is 2.1V at 8A,
turn-off and inductive load are assumed, MOSFET turn-off 25°C, maximum RDS,ON is 0.34Ω at drain current is 17A,
loss is obtained as: and maximum COSS is 32pF at drain-source voltage is 480V.
1 VST,Q =
VOVP,MAX
⋅VOUT +VDROP,DIODE
PQ,SWOFF = ⋅VOUT ⋅ I L ⋅ tOFF ⋅ f SW [W ] (28) VREF
2
2.73
where tOFF is the turn-off time and fSW is the switching = ⋅ 430 + 2.1 = 471.6 [V ]
2.50
frequency.
2
1 4 2 ⋅VLINE (
Boundary Mode PFC inductor current and switching PQ,CON = I L,PK ⋅
− ⋅ RDS,ON
)
frequency vary at every switching moment. RMS inductor 6 9 π ⋅VOUT
current and average switching frequency over one AC
2
1 4 2 ⋅ 85
⋅ (0.34) = 2.23 [W ]
period can be used instead of instantaneous values. = 7.392 ⋅ −
6 9 π ⋅ 430
Individual loss portions are changed according to the input
voltage; maximum conduction loss appears at low line PQ ,SWOFF =
1
⋅VOUT ⋅ I L ⋅ t OFF ⋅ f SW
because of high input current; and maximum switching off 2
loss appears at high line because of the high switching 1
= ⋅ 430 ⋅ 2.613 ⋅ 50 ns ⋅ ( 50 k / 0.8 ) =1.755 [ W ]
2
frequency. The resulting loss is always lower than the
summation of the two losses calculated above. PQ,DISCHG =
1
⋅ (COSS + C EXT + C PAR ) ⋅VOUT
2
⋅ f SW
2
Capacitive discharge loss made by effective capacitance =
1
⋅ 32 p ⋅ 430 2 ⋅ ( 50 k / 0.8 ) = 0.184 [ W ]
shown at drain and source, which includes MOSFET COSS, 2
an externally added capacitor to reduce dv/dt and parasitic Diode average current and forward-voltage drop loss as:
capacitance shown at drain pin, is also dissipated at
MOSFET. That loss is calculated as: I OUT 0.5
I DOUT,AVE = = = 0.56 [ A ]
η 0.9
1
PQ,DISCHG= (COSS + CEXT + CPAR) ⋅VOUT
2
⋅ f SW [W ] (29) PDOUT ,LOSS = VDOUT ,FOR ⋅ I DOUT ,AVE = 2.1 ⋅ 0.56 = 1.46 [ W ]
2
where:
COSS is the output capacitance of MOSFET; [STEP-7] Determine Current-Sense Resistor
CEXT is an externally added capacitance at drain and source
of MOSFET; and It is typical to set pulse-by-pulse current limit level a little
CPAR is the parasitic capacitance shown at drain pin. higher than the maximum inductor current calculated by
Equation (10). For 10% margin, the current-sensing resistor
Because the COSS is a function of the drain and source is selected as:
voltage, it is necessary to refer to graph data showing the
relationship between COSS and voltage. VCS,LIM
RCS = [ Ω] (33)
I L,PK ⋅1.1
Estimate the total power dissipation of MOSFET as the sum
of three losses: Once resistance is calculated, its power loss at low line is
calculated as:
PQ = PQ,CON + PQ,SWOFF+ PQ,DISCHG[W ] (30)
PRCS = IQ2,RMS⋅ RCS [W ] (34)
Diode voltage stress is the same as the output capacitor
stress calculated in Equation (24). Power rating of the sensing resistor is recommended a twice
the power rating calculated in Equation (34).
∧
(Design Example) Maximum inductor current is 4.889A v OUT
= K SAW ⋅
(VLINE )2 RL ⋅ 1
and sensing resistor is calculated as: ∧ 4 VOUT ⋅ L s (36)
v COMP 1+
2π f p
VCS ,LIM 0.8
RCS = = = 0.098 [ Ω ] 2
pk
Iind ⋅1.1 7.392 ⋅1.1 where fp = and RL is the output load resistance in a
2 π ⋅ RL COUT
Choosing 0.1Ω as RCS, power loss is calculated as: given load condition.
PRCS,LOSS = I Q2,RMS ⋅ RCS = 2.4362 ⋅0.098 = 0.58 [W ] Figure 27 and Figure 28 show the variation of the control-
to-output transfer function for different input voltages and
Recommended power rating of sensing resistor is 1.19W. different loads. Since DC gain and crossover frequency
increase as input voltage increases, and DC gain increases
as load decreases, high input voltage and light load is the
[STEP-8] Design Compensation Network worst condition for feedback loop design.
The boost PFC power stage can be modeled as shown in
Figure 26 MOSFET and diode can be changed to loss-free
resistor model and then modeled as a voltage-controlled
current source supplying RC network.
2.5 115 µmho Typically, high RFB1 is used to reduce power consumption
fI = ⋅
(
VOUT 2 π ⋅ CCOMP, LF + CCOMP, HF ) and CFB can be added to raise the noise immunity. The
1 maximum CFB currently used is several nano farads. Adding
where fCZ = a capacitor at the feedback loop introduces a pole as:
2 π ⋅ RCOMP ⋅ CCOMP, LF
1 1
fCP = f FP =
CCOMP, LF ⋅ CCOMP, HF 2 π ⋅ (RFB1 // RFB2 ) ⋅ CFB
2 π ⋅ RCOMP ⋅
1
(40)
CCOMP, LF + CCOMP, HF ≅
[ Hz]
2 π ⋅ RFB2 ⋅ CFB
If CCOMP,LF is much larger than CCOMP,HF, fI and fCP can be
simplified as: where (R FB1 // R FB 2 ) = R FB1 ⋅ R FB 2
R FB1 + R FB 2 .
2.5 115 µmho
fI ≅ ⋅ [ Hz ] Though RFB1 is high, pole frequency made by the
VOUT 2 π ⋅ CCOMP, LF
(38) synthesized total resistance and several nano farads is
1
f CP ≅ [ Hz ] several kilo hertz and rarely affects control-loop response
2 π ⋅ RCOMP ⋅ CCOMP, HF
The procedure to design the feedback loop is:
a. Determine the crossover frequency (fC) around 1/10 ~
1/5 of line frequency. Since the control-to-output
transfer function of the power stage has -20dB/dec
slope and -90o phase at the crossover frequency; it is
G M = 115 µmho required to place the zero of the compensation network
(fCZ) around the crossover frequency so 45° phase
margin is obtained. The capacitor CCOMP,LF is
determined as:
(Design Example) If RFB1 is 11.7MΩ, then RFB2 is: [STEP-9] Line Filter Capacitor Selection
2.5V 2.5 It is typical to use small bypass capacitors across the bridge
RFB2 = RFB1 = 11.7 × 106 = 68kΩ
VOUT − 2.5V 430 − 2.5 rectifier output stage to filter the switching current ripple, as
shown in Figure 30. Since the impedance of the line filter
Choosing the crossover frequency (control bandwidth) at inductor at line frequency is negligible compared to the
15Hz, CCOMP,LF is obtained as: impedance of the capacitors, the line frequency behavior of
the line filter stage can be modeled, as shown in Figure 30.
K SAW (V LINE ) 2.5 ⋅ 115 µ mho
2
= = 823 nF
2 ⋅ 430 2 ⋅199 × 10 − 6 ⋅ 240 × 10 −6 (2π 15 ) The circulating current through the capacitor is added to the
2
η⋅ (V
LINE) ⋅ 2 π ⋅ f LINE ⋅ CEQ
1 1 2
RCOMP = = = 12.8kΩ θ = tan−1 (44)
2π ⋅ f C ⋅ CCOMP,LF 2π ⋅15 ⋅ 823×10−9 POUT
Selecting the high-frequency pole as 150Hz, CCOMP,HF is where CEQ is the equivalent capacitance that appears across
obtained as: the AC line (CEQ=CF1+CF2+CHF).
1 1 The resultant displacement factor is:
CCOMP,HF = = = 82nF
2π ⋅ f CP ⋅ RCOMP 2π ⋅150⋅12.8 ×103
DF = cos(θ) (45)
These components result in a control loop with a bandwidth
of 19.5Hz and phase margin of 45.6°. The actual bandwidth is Since the displacement factor is related to power factor, the
a little larger than the asymptotic design. capacitors in the line filter stage should be selected
carefully. With a given minimum displacement factor
(DFMIN) at full-load condition, the allowable effective input
capacitance is obtained as:
CEA <
POUT
η ⋅ (VLINE )2 ⋅ 2 π ⋅ f LINE
( )
⋅ tan cos−1 (DFMN ) [ F ]
(46)
Po
Pin = (47)
E ff
Input Voltage Range (Vinmin and Vinmax): The maximum
input voltage would be the nominal PFC output voltage as:
2 PinTHU
Vin min = VO.PFC 2 − (49)
CDL
where VO.PFC is the nominal PFC output voltage, THU is a
hold-up time, and CDL is the DC link bulk capacitor.
m 8n2 Vo 2
M min = (50) Rac = (53)
m − 1 @f=fo π 2 Po
which would be the minimum gain because the nominal (Design Example)
PFC output voltage is the maximum input voltage (Vinmax). 8n 2 (Vo + VF ) 2 8 ⋅1.932 ⋅103.9 2
Rac = = = 217 Ω
π2 Po π 2 ⋅150
The maximum voltage gain is given as:
[STEP-14] Design the Resonant Network
V max
M max
= in min M min (51) With the m value chosen in STEP-11, read the proper Q
Vin
value from the peak gain curves in Figure 33 that allows
enough peak gain. Considering the load transient and stable
zero-voltage-switching (ZVS) operation, 10~20% margin
(Design Example) The ratio (m) between Lp and Lr is should be introduced on the maximum gain when
chosen as 5. The minimum and maximum gains are determining the peak gain. Once the Q value is determined,
obtained as: the resonant parameters are obtained as:
V RO m 5
M min = = = = 1.12
Vin max m −1 5 −1 1
Cr = (54)
max
2 2π Q ⋅ f o ⋅ Rac
V in 400
M max = m min = ⋅ 1.12 = 1.31
V in min 341 1
Lr = (55)
Gain (M) (2π f o )2 Cr
Peak Gain
(Available Maximum Gain)
L p = m ⋅ Lr (56)
1.31
Mmax for VINmin
(Design Example)
for As calculated in STEP-11, the maximum voltage gain
1.12 VINmax (M max) for the minimum input voltage (Vinmin) is 1.31. With
min
M 15% margin, a peak gain of 1.51 is required. m has been
( VO.PFC )
chosen as 5 in STEP-11 and Q is obtained as 0.38 from the
peak gain curves in Figure 33. By selecting the resonant
M =
m
= 1.12 frequency as 100kHz, the resonant components are
m −1
determined as:
1 1
fs Cr = = = 19 nF
fo 2 πQ ⋅ f o ⋅ Rac 2 π ⋅ 0.38 ⋅100 ×10 3 ⋅ 217
Figure 32. Maximum Gain / Minimum Gain 1 1
Lr = = = 133 µH
( 2 πf o ) 2 C r ( 2 π ×100 ×10 3 ) 2 ⋅19 ×10 −9
[STEP-12] Determine the Transformer Turns L p = m ⋅ Lr = 665 µH
Ratio (n=Np/Ns)
With the minimum gain (Mmin) obtained in STEP-11, the
transformer turns ratio is given as:
Np Vin max
n= = ⋅ M min (52)
Ns 2(Vo + VF )
where VF is the secondary-side rectifier diode voltage drop.
n(Vo + VF )
N p min = (57)
2 f s ⋅ M V ⋅ ∆B ⋅ Ae
min
n (Vo+VF)/MV
VRI 1/(2fs) Figure 35. Gain Curve
2 f s ∆B ⋅1.11⋅ Ae
min
1.93 ×103.9
= = 26 turns
2 × 82 ×103 ⋅ 0.4 ⋅1.11⋅107 ×10 −6
Choose Ns so that the resultant Np is larger than Npmin: Figure 36. Sectional Bobbin
min
N p = n ⋅ N s = 1.93 × 14 = 27 < N p Table 1. Measured Lp and Lr with Different Gap
Lengths
N p = n ⋅ N s = 1.93 × 15 = 29 < N p min
Gap Length Lp Lr
N p = n ⋅ N s = 1.93 × 16 = 31 > N p min
0.0mm 2,295µH 123µH
N p = n ⋅ N s = 1.93 × 17 = 33 > N p min
0.05mm 943µH 122µH
N p = n ⋅ N s = 1.93 × 18 = 35 > N p min 0.10mm 630µH 118µH
min
N p = n ⋅ N s = 1.93 × 19 = 37 > N p 0.15mm 488µH 117µH
0.20mm 419µH 115µH
0.25mm 366µH 114µH
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
Rev. 1.0.0 • 4/20/11 18
AN-9738 APPLICATION NOTE
π Io π2 −8
I Co RMS = ( )2 − I o 2 = Io (64)
2 2 8
The voltage ripple of the output capacitor is:
π
∆Vo = I o ⋅ RC (65)
2
where RC is the effective series resistance (ESR) of the
output capacitor and the power dissipation is the output
capacitor is:
5.2k Ω
f min = × 100(kHz ) (67)
Rmin
5.2k Ω 4.68k Ω
f max = ( + ) × 100(kHz ) (68)
Rmin Rmax
Figure 39. Frequency Sweep of the Soft-Start
(Design Example) The minimum frequency is 75kHz in (Design Example) Since the OCP level is determined as
STEP-15. Rmin is determined as: 2.5A in STEP-17 and the OCP threshold voltage is -0.6V, a
sensing resistor of 0.24Ω is used. The RC time constant is
100 KHz
Rmin = × 5.2 KΩ = 6.93KΩ set to 100ns (1/100 of switching period) with 1kΩ resistor
f min
and 100pF capacitor.
Considering the output voltage overshoot during transient
(10%) and the controllability of the feedback loop, the
[STEP-21] Voltage and Current Feedback
maximum frequency is set as 140kHz. Rmax is determined as:
Power supplies for LED lighting must be controlled by
4.68KΩ
Rmax = Constant Current (CC) Mode as well as a Constant Voltage
f o × 1.40 5.2 KΩ
( − ) (CV) Mode. Because the forward-voltage drop of LED
100 KHz Rmin varies with the junction temperature and the current also
4.68 KΩ increases greatly consequently, devices can be damaged.
= = 7.88 KΩ
96 KHz × 1.40 5.2 KΩ
( − ) Figure 42 shows an example of a CC and CV Mode
100 KHz 6.93KΩ
feedback circuit for single-output LED power supply.
Setting the initial frequency of soft-start as 250kHz (2.5 During normal operation, CC Mode is dominant and the CV
times of the resonant frequency), the soft-start resistor RSS is control circuit does not activate as long as the feedback
given as: voltage is lower than reference voltage, which means that
5 .2 KΩ CV control circuit only acts as OVP for abnormal modes.
R SS =
f ISS − 40 KHz 5.2 KΩ
( − )
100 KHz Rmin (Design Example) The output voltage (VO) is 103V in
5.2 KΩ
design target. VO is determined as:
= = 3.85 KΩ
250 KHz − 40 KHz 5.2 KΩ R FU
( − ) Vo = 2.5(1 + )
100 KHz 6.93KΩ R FL
[STEP-20] Current Sensing and Protection Set the upper-side feedback resistance (RFU) as 330KΩ. RFL
is determined as:
FAN7621S senses low-side MOSFET drain current as a
2.5 × RFU 2.5 × 330 KΩ
negative voltage, as shown in Figure 40. and Figure 41. RFL = = = 8 .2 K Ω
Half-wave sensing allows low power dissipation in the (Vo − 2.5) (103 − 2.5)
sensing resistor, while full-wave sensing has less switching The output current (ILED) is 1.46A in design target.
noise in the sensing signal. Typically, an RC low-pass filter Assuming the sensing resistor (RSENSE) of 0.1Ω and
is used to filter out the switching noise in the sensing signal. feedback resistor (R202) of 47KΩ are used, the input
The RC time constant of the low-pass filter should be resistor R203 is determined as:
1/100~1/20 of the switching period.
VSENSE × R 202 ( RSENSE × I LED ) × R202
R203 = =
0.36 0.36
(0.1×1.46) × 47KΩ
= = 19KΩ
0.36
VLED 1
ISENSE 2
VAUX 3
1 VFB 4
FB 5
PC1A 6
CP1 PS2561 7
VDC DP1 22nF/630V 8
9
RP1 10
4
5
3
1
2
TM1 FFPF08H60S 390k 2 11
CS8 CS7 CS6 CS5 CS1 CS2 12
EER3019N 47uF 47uF 47uF 47uF 47uF 47uF
RP3 RP4 RP7 RP2
J2
0 1M CON12
RP5 4.3M 4.3M Q1 Q2 2
MMBT2222A MMBT2907A 1
68K/2W
RP6 DP2
0 RS1M RP10 TM2 CON2
6
7
9
8
10
33k RP11 RP9 EER3543
DS3
DS2
10k RP8 1M
LL4148
LL4148
10k D2
CP2 1 16
RP12 33uF/25V
7
1
2 15 FFPF20UA60DN
CS25
CS19
220nF
220nF
24K
Q3 3 14
LM358/ON
LM358/ON
8
4
8
4
OUT
OUT
RP13 RP14 MMBT2222A
4.3M 4.3M RP15 4 13
V-
V-
V+
V+
+
+
-
-
U6B
U6A
ZDP2 47k 5 12
CS6
5
6
3
2
MMSZ5235
0 D1
47k
47k
VAUX
M1 6 11
33uF/25V
RS56
RS33
DP3 RP16 DP4 FCPF11N65 RP17 DP5
27 LL4148 CP4 CP5 CP8 CP6 ZDP1 0 0 10 RS1M 7 10
RS1M
120uF/450V120uF/450V120uF/450V 33uF/25V MMSZ5248 FFPF20UA60DN
8 9
PFC RP18 U2 RP19
U1 FAN7930B 4.7 10
120k
100k
FAN7621S
RS55
RS40
U3
13k
8 7 MMBT2907A
RS35
VCC OUT DS1
4. Schematic of the Evaluation Board
U7
4.7k
22
6.8uF/50V MMBT2222A
RS41
8.RT
TL431
RP22 DP6
3 1 10 LL4148 C1 RP26
COMP INV RP23 RP24 RP25 100nF 33k
CP7
RP27 2k 8.2k 2.7k 680p
8.2k
330k
6 2 RP28 M2
RS59
RS57
5.2K CP10 GND OVP 3.HO 3 FDPF7N60NZ
1uF CP11 RP32 C2
470pF 0 10k
CP14 0 U4 CP13
6.A/R
1k
1uF MMBT2907A 33uF/25V
RS49
CP17 3.3n
2.CTR
10uF/16V
R46
RS44
RS42
4 0 ZDP3
CP21 CP9 RP33 RP29 RP31 CP15 CP16 MMSZ5248
33uF/25V 0.1uF 0.1/5W 75K 75K 1nF 1nF PC1B
0.1
N.C
N.C
VFB
PS2561 RP34 DP7
VLED
VAUX
CP18 10 LL4148
ISENSE
12n 0 M3
14.LO FDPF7N60NZ
3 RP35
9.CS
FAN7621S
3 RP36
12
11
10
9
8
7
6
5
4
3
2
1
10k
J6
RP37
CP19
CON12
0 0 1k 100p U5
10.SG
16.PG
CN1 F1 MMBT2907A
CON3 LF1 LF2
FS101 10mH 10mH
1 1 2 1 2 RP38A
0 0.2
2 RS1
1
ZNR1 RS2 CS3 CS4 CS11 4 - + 2 0
FG VDC
470nF 470nF 220nF
1M
2
3
CS10 CP20
RS3 4.7nF
0.68uF/630V
1M
3 4 3 4
APPLICATION NOTE
www.fairchildsemi.com
AN-9738 APPLICATION NOTE
5. Bill of Materials
Item No. Qty Reference Part Reference Description (Manufacturer)
1 1 BD1 600V/8A Bridge Diode (Fairchild Semiconductor)
2 1 CN1 3PIN Connector
3 1 CP1 630V22nF Film Capacitor
4 5 CP2,CP6,CP13,CP21 33µF/25V SMD Tantal Capacitor
5 3 CP4,CP5,CP8 120µF/450V Electrolytic Capacitor
6 1 CP7 680p/25V SMD Capacitor 2012
7 1 CP9 0.1µF/25V SMD Capacitor 2012
8 2 CP10,CP14 1µF/25V SMD Capacitor 2012
9 1 CP11 470pF/25V SMD Capacitor 2012
10 2 CP15,CP16 33µF/25V SMD Capacitor 2012
11 1 CP17 10µF/16V Electrolytic Capacitor
12 1 CP18 12nF/25V SMD Capacitor 2012
13 1 CP19 100pF/26V SMD Capacitor 2012
14 1 CP20 0.68µF/630V Film Capacitor
15 1 CP22 100p/25V SMD Capacitor 2012
16 6 CS1,CS2,CS5,CS6,CS7,CS8 47µF/200V Electrolytic Capacitor
17 2 CS3,CS4 470nF/400V Film Capacitor
CS19,CS25 220nF/25V SMD Capacitor 2012
Related Datasheets
FL7930B — Single-Stage Flyback and Boundary Mode PFC Controller for Lighting
FAN7621S — Controller for Resonant Half Bridge
FDPF17N60NT — 600V N-Channel MOSFET, UniFET™2
FDPF7N60NZ — 600V N-Channel MOSFET, UniFET™2
Author
WonSeok, Kang
Power Conversion Korea
Senior System and Application Engineer
Wonseok.kang@fairchildsemi.com
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
1. Life support devices or systems are devices or systems which, 2. A critical component is any component of a life support device
(a) are intended for surgical implant into the body, or (b) or system whose failure to perform can be reasonably
support or sustain life, or (c) whose failure to perform when expected to cause the failure of the life support device or
properly used in accordance with instructions for use provided system, or to affect its safety or effectiveness.
in the labeling, can be reasonably expected to result in
significant injury to the user.