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AC-JTAG: Empowering JTAG beyond Testing DC Nets

Sung S.Chung and Sang H. Baeg


Cisco Systems, Inc.
170 W. Tasman Drive
San Jose, CA 95 134

transceiver modules are under development by optical


ABSTRACT vendors for Cisco Systems Inc.
This paper presents the new technology that extends Figure 1 shows two types of interconnections between
today’s JTAG’s capability from DC domain to both AC devices in terms of interconnect testability. The first type
and DC domains. New concept, AC-EXTEST is is a net testable by standard IEEE 1149.1, where DC value
introduced to support AC interconnection test and to have is driven and captured. The second type of nets is AC
backward compatibility with EXTEST. It leverages coupled net, which goes beyond the IEEE 1149.1’s
existing application software available within boundary- capability. Capacitance can be coupled on board or
scan test industry to promote this technology to embedded inside devices, which look like DC nets by
manufacturingfloor with minimal impact. outward appearance.

IEEE 1149.4 [5] addresses analog pins, however current


1 Introduction IEEE 1149.1 defines them as “linkage” so that the signals
Bandwidth requirements for internet devices (e.g. are no longer test resources [ l , 2, 91. IEEE 1149.1 based
switch, router) have increased over multiple Tera-bits per approach was considered as a better candidate for the AC
seconds in today’s network equipments. This type of coupled line test than with IEEE 1149.4 since AC coupled
industry trend promotes use of high-speed serial signal lines carry high speed digital signals rather than
interconnections instead of parallel bus based analog signals. Additional issues listed below prevented
communications in relatively lower speed. The typical further utilization of IEEE 1149.4 as primary means of
serial interconnections can be found in devices such as testing AC coupled nets.
SERDES (SERializer DESerializer) and VCSEL (Vertical
Cavity Surface Emitting LASER) device. SERDES takes IEEE 1149.4 is harder to implement and has higher
parallel data and transforms to serial bit stream or vice area, delay and power overhead than IEEE 1149.1.
versa. It is often interconnected with VCSEL devices to High-speed differential signaling technology requires
transmit or receive optical signals or with SERDES for very tight timing constraint so that fully compliant
high-speed serial connection. Transmission speed in the ABM implementation is difficult with today’s
connection starts from 1 GBPS (Giga-Bits Per Second) in technology.
optical interface. Wide variations of termination methods used in
differential lines add longer test time with IEEE
In many cases, such serial interconnections are AC 1149.4 when there are 100s of such nets within the
coupled nets. For performance reasons, only high device.
frequency signals are delivered to other party and Power budget needed for Parallel Optics modules is
amplified. To increase noise immunity, the not suited for the 1149.4 implementation because it
interconnections are often connected differentially. Since adds substantial area overhead, in turn it adds more
receivers only see the differences of the signals, the noise power dissipation.
appearing both differential lines is canceled out by so Device must work with the DC coupled and AC
called common-mode rejection. The traditional coupled application with existing IEEE 1149.1
interconnection test schemes based on B E E 1149.1 are no environment.
longer valid under such conditions [ I , 2, 5-81. Devices The solution must support interoperability with the
utilizing AC coupled connection in parallel optics existing legacy device within IEEE 1149.1.

Paper 2.1 ITC INTERNATIONALTEST CONFERENCE


30 $10.00 0 2001 IEEE
0-7803-7169-0/01
In this paper, new boundary scan method is proposed to We call this technology as DC-JTAG for
solve testing of AC coupled interconnection nets under convenience. Under DC-JTAG, DC patterns are
IEEE 1149.1 environment. Section 3 discusses objectives applied by drivers and DC patterns are captured by
of this project. The system view of AC-JTAG is explained the counter-part receivers. If there is an AC coupling
in Section 4. The new concept, AC-EXTEST is defined in element on the DC line, the AC signals need to be
section 5. Design examples for boundary scan cells are transmitted and received for proper communication.
shown in section 6. The philosophical aspect of fault When such AC signals are used for interconnect test
coverage is discussed and coverage result is shown for under boundary-scan environment, we call it AC-
LVDS (Low Voltage Differential Signal) in section 7 [3]. JTAG. AC-JTAG and DC-JTAG should be
selectively executable.

Self-contained Technology: AC-JTAG should be


developed, deployed, and executed independently and
should not depend on or be driven from the mission
logic function. It should be portable to migrate
designs easily from one design to different designs
and process technologies. It should also be as
transparent as possible to existing boundary-scan
SmllQIl ATE equipments.

Minimal Impact to JTAG Application Software:


Figure 1: DC and AC Coupled Nets The current boundary scan softwares should be
available with minimal additive enhancement without
2 Definitions invalidating existing functions. This is critical aspect
of the new technology development due to time
AC: Alternating Current pressure on the manufacturing floor.
AC Coupling: if steady state value at the receiving end
of the net is no longer the same value as in driving end, Interoperable with Broader Supply Base: AC-
then the net is so call AC coupled. The net has serial JTAG should use simple and clear protocol so that
coupling with a capacitive component. A DC de-coupled many different devices from different vendors can
net is an AC coupled net. support AC-JTAG. At the same time, legacy devices
AC Boundary-Scan: general term to describe AC should work with devices equipped with AC-JTAG.
coupled net test capable boundary-scan structure. It
consists of a pattern generator and pattern capture with System Overview
optional synchronizing pulse, and a pattern mapping Figuie 2 shows the logical view of the AC-JTAG
mechanism if necessary to map captured AC signals back system. This layer model is introduced to explain and
to the expected DC value. discuss AC-JTAG in IEEE 1149.1 domain. There are
AC pattern: consist of serial bit stream with certain three layers in the system model, application link layer,
clock speed. The pattern has fixed length and repeats itself logical link layer, and physical link layer. When two AC
continually. As a simplest form, it can be a LFSR with boundary-scan cells are communicating each other, they
single feedback, which has polynomial form of f(x) = are communicating through the three layers. The bold
1+Xn. Other known coding sequences also can be used. lines in the figure show the data flow through layers.
AC pattern clock: clock used to generate AC pattern.
DC pattern: test pattern with the constant driving value Application link defines communication protocols
during the entire duration of given test cycle. between devices, and runs boundary-scan test algorithms.
It works over the logical link layer. The protocol is named
3 Objectives as AC-EXTEST and discussed in the next section.
This section discusses the major considerations taken
during the development. Logical link layer provides the foundation under which
interconnection is checked. The link is logically connected
Dual Mode Support for both AC and DC: The when the driven value is same as the received value. The
conventional JTAG is used to test only the DC lines. logical values are either high or low.

Paper 2.1
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Protocol under
AC-EXTEST and RTl
Application Link 1149.1 + 1149.1

0
0 + O
Logical Link
1
1 ) 1

Physical Link
10101o...

010101... - m
-rLnnrL
I/
101010...

010101...

Figure 2: System Layer Model for AC-JTAG


Since we assume the application layer works on the scheme, all AC boundary scan cells receive the same
logical layer, the application software in boundary-scan pattern from the central test generator.
industry doesn't need redevelopment. 0 Serial AC test generation (SATG): this is also a
centralized test generation system like the parallel
Physical link layer represents physical connection scheme. It is different from the parallel scheme in
between two devices. When DC-JTAG is selected, a how patterns are delivered to boundary scan cells. In
driver takes a logical value from logical link and puts it on this scheme, test pattern is fed to boundary scan cells
the physical link. The receiver does the same but in serially through a shift register chain instead of a
reverse order. Note that the values in the physical link are single wire common to all boundary-scan cells as in
same as in the logical link. When AC-JTAG is selected, it the parallel scheme.
takes a logical value from the logical link layer, translates
it to an AC signal, and drives the actual physical link. The PAPG saves hardware overhead paid for each
receiver monitors the AC signal and translates it back to a boundary-scan cell, but in turn needs global wiring from
logical value, which will be passed to the logical link the central pattern generation logic to every AC boundary
layer. scan cells. SATG saves such global routing overhead by
shifting the AC patterns serially but it may need additional
Two major components in the AC-JTAG system are shifting chain for the AC pattern. If BAPG implements a
discussed further in detail: AC pattern generation, and AC simple AC pattern generation mechanism, the expected
pattern sample. overall hardware overhead penalty is not significantly
different among the three approaches. The major
4.1 AC Pattern Generation advantage of PAPG and SATG is to provide rather
AC patterns generation belongs to the physical link complex AC patterns such as 8B/l@B encoding [4]
layer. The patterns are generated and driven from the without adding too much of additional hardware overhead
driving side of the AC boundary scan cells and received when other AC pattern is implemented. A design example
by the receiving side of AC boundary scan cells. Three is shown using BAPG in section 6.
different pattern generation schemes are discussed here.
4.2 AC Pattern Sample
0 Built-in AC pattern generation (BAPG): this The receiving device with help of the driving device
scheme is a distributed test generation system, in should determine the time to sample a constantly varying
which each AC boundary scan cell in a chip has a AC signal. The receiving AC boundary-scan cell is
built-in AC test pattern generator. responsible for decoding a DC value from the AC pattern.
0 Parallel AC pattern generation (PAPG): this is a In order to achieve this goal, the cell must sample the AC
centralized test generation scheme, in which one signal at pre-determined sample intervals. The sampled
centralized test pattern generator drives a group of value(s) are decoded, and then used by traditional test
AC boundary scan cells in a certain sequence. In this

Paper 2.1
32
software for comparison. The decoded value should be the 5 ACEXTEST'
same logical value as on the driving side as a result of the AC-EXTEST defines an application layer protocol to
decoding process. This step corresponds to the procedure enable testing AC coupled nets when AC boundary-scan
from the physical link to the logical link in figure 2. The cells are used.
time interval to sample AC signal can be determined
explicitly or implicitly. 5.1 The AC-EXTEST Instruction
The AC-EXTEST is a public instruction in IEEE
4.2.1 Explicit AC Sample Scheme 1149.1 and is a super set of the mandated EXTEST
Driving device reports the sampling time for a AC instruction. AC-EXTEST works with the AC boundary-
signal to its counter-part receiving device by the explicit scan cell, which is backward compatible with the
signal, called AC capture signal. The receiving device mandated EXTEST instruction when the cell is under the
purely relies on the signal to sample the AC pattern. EXTEST instruction. When the AC-EXTEST instruction
While explicit signaling enables clear communication is selected, the boundary-scan register cells determine the
among devices, it has disadvantage of having multiple state of all system output pins.
extra AC capture signals connected over multiple devices,
especially when a device is receiving AC capture signals As in the mandatory EXTEST instruction defined in the
from multiple driving devices. Board designers may elect IEEE 1149.1 Standard, AC-EXTEST would load data into
one for a master driver to avoid multiple AC capture the latched parallel outputs of boundary-scan shift-register
signals from going to a device. Since the data and clock stages using the PRELOAD instruction. The AC-EXTEST
signals are transmitted together, this scheme requires a capable AC boundary-scan register cells located at system
careful timing adjustment during board design as in source output pins (2-state, 3-state, or bi-directional) can
synchronous designs. generate AC patterns during the Run-Test/IdZe controller
state.
4.2.2 Implicit AC Sample Scheme
In this scheme, no explicit AC capture signal is The snapshot of AC pattern signal is sampled at the
transmitted as in the previous case. The receiving device system input pins during the Run-Test/Idle controller state
recognizes the sample time by processing the protocol at every 16th AC pattern cycles and the falling edge of the
defined in the application link layer. AC boundary scan AC pattern clock as shown in Figure 5 . The 16" cycle is a
cells are timed to sample the AC signals based on such part of implicit synchronization scheme discussed in
protocol. The details are discussed in the next section. section 4 and selected as an interoperability reason.
Explicit synchronization can be used when a device-to-
device interconnection is well defined.

The decoded DC value from sampled value(s) shall be


the same value as the data held in the driving AC
boundary-scan register cell at the system output pins.
Then the sampled value in the AC Boundary-scan cell is
AC-EXTEST Instruction loaded onto the boundary-scan Capture register cell on
the rising edge of TCK in the Capture-DR controller state.
Execute Figure 3 shows the expected execution for AC-EXTEST.

Execution effects after Capture-DR


Net Test Data AC-EXTEST Instruction Instruction AC Scan Cell DC Scan Cell
Results

EXTEST
EXTEST EXTEST EXTEST EXTEST

Table 1: Comparisons of AC-EXTEST and EXTEST

Figure 3: Expected AC-EXTEST Execution

AC-EXTEST is a Cisco's invention

Paper 2.1
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5.2 Link to EXTEST a) Both the system output pins and the system input pins
When the AC-EXTEST instruction is selected, the are interconnected and are under the AC-EXTEST
system. output pins follow rules set by the EXTEST instruction. The test shall work properly regardless of
instruction, except for the system output pins with the AC AC coupling between the interconnections.
boundary-scan cells. The pins equipped with an AC b) If there is no AC coupling between two devices, the
boundary-scan cell apply AC patterns in the Run-TestIIdle system output pin under the EXTEST instruction shall
controller state, instead of steady state logic levels as in operate with the system the input pin under the
the EXTEST instruction. AC-EXTEST instruction.
c> The system output pins under the AC-EXTEST
Table 1 shows the effects of AC-EXTEST compared to instruction shall operate as the EXTEST instruction if
EXTEST. The devices under AC-EXTEST operate as an the TAP controller is not in the Run-Test/Idle
AC-EXTEST only when the TAP controller goes through controller state.
Run-Test/Idle controller state. AC-EXTEST works the
same way as EXTEST if the TAP controller goes to the The system input pins under the EXTEST instruction
Capture-DR controller state without passing through the may not perform the test properly with the system output
Run-TestLdle controller state after each Update-DR or pins under the AC-EXTEST instruction and should be
Update-IR. avoided. The input pins capture unpredictable AC values,
: unknown to the DC world.

Figure 4: Example AC boundary-scan cell BC-I


value. Figures 4 shows the examples of AC capable

Run-TestI Idle
<
!

4,
----y
I

j
I

....
boundary-scan cells and various signals used in the
examples. The major signals are explained as follows:
8--qLrLr
AC Pattern A
AC Pa& A =
AC-Sync1 i j n i i n
....a
AC-Test: a function of the AC-EXTEST instruction
and the Run-TestAdle controller state. It becomes true
....
I
when the TAP controller is in the Run-TestIIdle
controller state under the AC-EXTEST instruction.
Figure 5: Example timing diagram of critical signals AC-Pattern-Clock: the AC pattern generation and
pattern sample logic use the same clock known as
6 Boundary-scan cell Design examples “AC pattern clock”, shown here as
The AC boundary-scan cell can have predefined “AC-Pattern-Clock” to synchronize pattern
function of BC-0 to BC-IO, which carry all the semantics generation and sample operations. The signal
of 1149.1 with additional AC related portions. The AC “AC-Pattern-Clock” is a shared clock for AC pattern
test pattern generation and capture capabilities are added generation and the ClockDR for capturing and
to the existing boundary scan scheme. The AC boundary- shifting of boundary-scan test signals.
scan cells together with the AC capable TAP controller AC-Test-Marker: a single event that is one and a half
have pattern generator, and pattern capture functions, as pattern clock cycle long, and positive going pulse to
well as pattern mapping circuitry if necessary to convert mark the beginning of the AC pattern generation
preloaded DC (logic) value into AC patterns and the sequences. It is used to set the pattern generation flip-
sampled AC signals back to the expected DC (logic) flop with a known value.

Paper 2.1
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0 AC-Test-Ran: used to control the input AC translated to the logical value used by the application
boundary-scan register cells to capture from the layer. Since there are so many types of drivers and
system pin input buffer instead of capturing from AC receivers combined with different technologies, we
pattern sample flip-flop. In special cases where the believe that it is an entirely new area of research to define
AC-EXTEST instruction is executed without going both the sampling and encoding methods.
to the Run-Testhdle controller state, this mode of
operation is enabled and the signal forces the AC In this section, we have shown fault coverage for LVDS
boundary-scan register cell to act like a DC scan cell. (Low Voltage Differential Signal) without adding any
special receiving features for fault detection purposes on
6.1 AC Boundary Scan Cell Design Example normal LVDS receiver to demonstrate the coverage that
The examples in Figures 4 are boundary-scan register plain AC-JTAG without special buffer technology can
cell type BC-1 and maintain compatibility with existing achieve.
EXTEST. AC boundary-scan cells can be mixed into the
design with any of the IEEE 1149.1 Standard compatible 7.1 LVDS Connection
devices. The differential line with point-to-point connection
using LVDS is typically configured as in Figure 6. The
The left portion of Figure 4 shows an AC scan cell with driver is both sourcing and sinking current. The
a built-in AC pattern generator, it generates AC patterns termination registers at the receiving side will provide
using “AC- Pattern-ClocK’ and boundary-scan Capture differential voltage of 350mV. Please see [3] for LVDS
register cell. First, the EXTEST value from the Update specification.
scan cell is copied into the boundary-scan Capture LVDS Urm
Dnw 3 M
Lms
h a v LIIY)
er

register cell with “AC- TesLMarkeT’ and RI

“AC- Pattern- ClocK’. Subsequent 1MChm


3ymV

“AC-Pattern-ClocK’ starts to generate a AC pattern and


the pattern is fed into the system pin. The right portion of
Figure 6: A Typical Point-to-Point LVDS Application
Figure 4 shows an example of input scan cell with the
AC-EXTEST capability. There is an extra AC pattern
sample flip-flop with an “AC-Sync” signal, which can be
generated either explicitly or implicitly as discussed in
Section 4.

When “AC- Test_Ran” signal becomes active,


signifying the AC-EXTEST has been executed under the
Run-TestAdle controller state, the Capture scan cell
captures value from the AC pattern sample flip-flop; Figure 7: Faults inject points in LVDS pair
otherwise, it captures a value from the system pin. This
selection of capture source is controlled by the signal the
“AC- Test_Ran”. Signal before
CAP
7 Fault Coverage Signal after
The application link layer (see section 4) determines the CAP
physical link quality based on the translated logical value.
The DC connection in IEEE 1149.1 is checked pretty well
in this environment because logical representation is Recovered
Signal
identical as in the physical signal value system (i.e. high
and low values). However, AC connection is not easily
mapped to the existing JTAG system due to time variant
nature of AC signals. Figure 8: AC signal transitions
While time factor is removed during transforming AC
signal to a logic value, it is likely to mask out some
7.2 AC Coupled Capacitance
To create AC coupled lines to the differential lines, a
failures. Therefore, test quality purely depends on how
capacitance is added to the receiving end of a LVDS
AC signals are sampled and decoded before they are

Paper 2.1
35
receiver. lOOnf coupling capacitances are used in this recovery logic can be added to handle such cases in thi
experiment; however, the coupling capacitance can be a receiving side before the AC signal is captured by A<
much smaller or higher value. As the coupling capacitance boundary scan cell. Such recovery logic belongs to th
is getting smaller, the signal after coupling capacitance is physical layer. So the AC-EXTET protocol is not affectel
no longer same as the signal before the coupling by such signals behavior. Figure 8 shows the signa
capacitance. Since only the high frequency components transitions through a small coupling capacitance an[
of the incoming signals passes through the capacitance, effects of the signal recovery logic. The signal transition:
the signals in the receiving side will be both positive and are for one leg of the differential pair seen in Figure 7.
negative going pulses at the rising and falling edges of the
incoming square waveform signal respectively. Signal

r7--Number Fault Type Signal

Positive before CAP


AC
Yes
Coverage
AC + DC
Yes
Comments

Positive after CAP Yes Yes I


Negative before CAP Yes I Yes
I

y
Negative after CAP Yes Yes

I Short
Positive before CAP and
Negative after CAP
Positive after CAP and
Negative before CAP
Positive before CAP and No Yes Combining with DC test might
Positive after CAP detect this fault
Short Negative before CAP and No Yes Combining with DC test might
Negative after CAP detect this fault
Stuck-0 Positive before CAP Yes/No Yes/No May require longer simulation time
Stuck-1 Positive before CAP Yes/No Yes/No Depends on Stuck voltage level
I
11 Stuck-0 Positive after CAP Yes Yes I
12 I Stuck-1 Positive after CAP Yes/No Yes/No Depends on Stuck voltage level
13 I Stuck-0 Negative before CAP Yes/No Yes/No May require longer simulation time
Negative before CAP Yes/No Yes/No Depends on Stuck voltage level
Negative after CAP Yes I Yes
16 I Stuck-1 Negative after CAP Yes/No I Yes/No I Depends on Stuckyoltage level
Table 2: Fault injection and coverage for LVDS AC coupled differential lines
7.3 Fault Coverage combined. The coverage analysis is purely based the
Faults are injected using resistors as shown in Figure 7. previously defined AC-EXTEST without assuming any
Certain resistors are initially set to infinite (zero) number special circuitry in the receiver side. To demonstrate the
and changed to zero (infinite) value to create short (open) detection mechanism used in this experiment, two spice
faults. simulation results are shown in Figures 9 and 10. Figure 9
shows the normal behavior and Figure 10 is the behavior
Table 2 summarizes coverage report based on the Spice with fault number 1 in Table 2 . The first two signals in
simulation for the LVDS pair connection through the figures show the input and output pulses. The next
capacitance. The first column represents the fault number. four signals represent the differential signal pairs before
Fault type is shown in the second column. In the third and after the coupling capacitance. The output of circuit
column, fault location is specified. “Positive” and with a fault is different from the normal behavior.
“negative” describe the polarity of differential signals in a
connection.

The forth column in Table 2 shows the coverage when


only AC-EXTEST result is considered and the fifth one
shows the coverage when both AC and DC test results are

Paper 2.1
36
build and execute the instruction. AC pattern generation
and sample methods have been illustrated with design
examples. Fault coverage result is presented using LVDS
U 0 technology.

Acknowledgements
This technology has been presented and reviewed by
many MSA (Multi Source Agreement) partners for Cisco
Parallel Optics module vendors. Authors wish to thank the
those who provided advice and feedback, especially
Pandu Sharma at Cisco Systems Inc., and Robert Schuelke
at AMCC.
Figure 9: Normal LVDS behavior

References
[ l ] IEEE Standard 1149.1a-1993, “IEEE Standard Test
Access Port and Boundary-Scan Architecture”,
IEEE Standards Board, New York, October 1993.
[2] Supplement to IEEE Standard 1149.1-1990, “IEEE
Standard Test Access Port and Boundary-Scan
Architecture”, IEEE Standards Board, New York,
March 1995
[3] TIA/EIA-644-1996: “Electrical Characteristics of
Low Voltage Differential Signaling (LVDS)
Figure 10: Behavior with fault number 1 Interface Circuits”.
[4] A. F. Benner “Fibre Channel: Gigabit
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the short faults will not be detected since the short line New York, March 1999
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not broken in this LVDS case since original LVDS is Proc. International Test Conference, 1995, pp 851-
working properly without the coupling capacitance. 860
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because of the coupling cap, so the fault is detected by an Symbolic Simulation-basedANSVIEEE Std 1149.1
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8 Conclusion Academic Publishers, 1998,, pp 251-253
We have introduced a new AC-JTAG technology. It
allows testing of AC coupled nets in the boundary-scan
environment. In addition, adopting this technology into a
manufacturing board test process can significantly reduce
board test cost. ACEXTEST is a public instruction,
which enables this technology. All the elements and
protocols between devices have been described to help

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