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Exam will be closed book and no 1.3 How are switches arranged
notes. to form the AND function?
Exam questions will be like these on
the study guide. Numbers and exact 1.4 How are switches arranged
things asked for will vary. Exam to form the OR function?
covers up to 1 flag block
communications model (Not 2 flag). 1.5 What is a CMOS pass
switch?
Please ensure you answer all the
items asked for in a question. Many 1.6 What is a Tri-State gate?
will have several parts.
Exam will be time limited. (Too 2.2 Draw schematics for a CMOS
many have another class after 287) mux based latch
There will be variations on the exam.
2.3 Draw schematics for a CMOS
Don’t panic if you have different
pass gate based latch
answers from you class mates.
They probably got a different version
of the exam. 2.4 Make a rising edge triggered
D flip-flop
Due to class size and policy, you will
need to present a picture ID when 2.5 Make a falling edge triggered
turning in your exam. JK flip-flop with reset and
clear
Please bring:
2.6 Explain Master/Slave flip-flop
• Pencil
operation.
• Scratch paper
2.7 Add reset and clear to any of
• Calculator the above flip-flops
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2.10 What precautions should be 3.8 Why are there design rules
taken when sending signals for ASIC engineers? What
between flip-flops on do they help in the ASIC
different clocks? process? List 3 such rules.
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4.9 Why will timing only be 6.6 Analyze a circuit to
“estimated” until physical determine if there is a race or
design is complete? long path.
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7.5 What happens if all the cells
in a design become larger?
8 Block communications
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