University of Notre Dame

CSE/EE 40462/60462, Fall 2013

VLSI Circuit Design

Lecture 9
24th September 2013

Ismo Hänninen
(Visiting Assistant Professor, Dr. Tech.)
Department of Electrical Engineering
University of Notre Dame, USA
Room: Cushing 227A
Tel: +1 574 631 0996
Cel: +1 574 386 4761
Email: ismo.hanninen@nd.edu
 University of Notre Dame, CSE/EE 40462/60462
VLSI Circuit Design, Outline
29 lectures in 15 weeks (27th Aug.— 12th Dec. 2013)

Course Wk Lecture Homework

1 L1: Overview
L2: Physics & Semiconductor Devices H0: Pre-course knowledge quiz (due wk 2 Monday before noon)
2 L3: CMOS Circuits #1 H1: Basic CMOS Transistor Circuits (due wk 3 Tuesday)
L4: CMOS Circuits #2
3 L5: MOS Transistor Theory H2: MOSFET Theory & Modeling (due wk 4 Tuesday)
L6: MOSFET Circuits
4 L7: MOSFET Real World Effects H3: Circuit Level Simulation Using SPICE (due wk 6 Tuesday)
L8: Basic CMOS Fabrication Process
5 L9: CMOS Layout Design & Design Rules H4: Fabrication & Layouts (due wk 6 Tuesday)
L10: Standard Cells & Stick Figure Layouts
6 L11: Layouts & Simulation
L12: Review for EXAM 1/3 EXAM 1/3 handout (due wk 7 Tuesday)
7 L13: Verilog #1 H5: Verilog (due wk 8 Tuesday)

CSE/EE 40462/60462 VLSI Circuit Design, Ismo Hänninen 2

 9. CMOS Layout Design

VLSI DESIGN
Ismo Hänninen
University of Notre Dame
Fall 2013

Based on material from

Profs. Peter Kogge, Joseph Nahas, Jay Brockman,
University of Notre Dame
And Prof. David Harris,
Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html

Slide 3 VLSI Circuit Design, 9. CMOS Layout Design

 Outline

Future Transistors

CMOS Structure & Layout Overview

Determining Rules & Mask Biases
Design Rules
Circuit Interconnect Layout

Slide 4 VLSI Circuit Design, 9. CMOS Layout Design

 Future Transistors

NOT AS GOOD AS YOU WOULD WISH

Slide 5 VLSI Circuit Design, 9. CMOS Layout Design

Miniaturization IS Good

Dimensions 1/K
Channel Width 1/K
Channel Length 1/K
Gate Oxide Thickness 1/K
Gate Capacitance 1/K
Voltage 1/K
Substrate Doping K
Circuit Area 1/K2 }
Moore’s Law Big Win
= 2 Speed K
every 2.5 years Current 1/K
Power Big Win 1/K2
Power per Unit Area 1
Slide 6 VLSI Circuit Design, 9. CMOS Layout Design
 MOS Generations, about every 2.5 Years
=1 = 1/ 0.7

Dimensions 0.7 X
Channel Length 0.7 X
Channel Width 0.7 X
Gate Oxide Thickness 0.7 X
Gate Capacitance 0.7 X
Stopped
Voltage 0.7 X In ~2005
Substrate Doping 1.4 X
Circuit Area
Peak Speed
0.5 X
1.4 X } Big Win
Current 0.7 X
Power
Power per Unit Area X
1/2 X
1
No Longer True
Now Dominates Design Process
Slide 7 VLSI Circuit Design, 9. CMOS Layout Design
 Moore’s Law

Circuit Density - 32% per year

Circuit Speed
Scaling - 15% / year
Architecture and Circuit Design - 10%/year
Overall - 26%/year
Chip Size - 15%/year
Architecture/Parallelism - 35%/year

66% performance improvement per year

before hitting the Power Wall of 2005

Now Just Architecture/Parallelism

Slide 8 VLSI Circuit Design, 9. CMOS Layout Design

 Transistors Degrade By Every Generation

Minimum-sized transistors get weaker and

weaker in every technology generation

Leakage current increases, important in all

sub-micron technologies
In 65-90nm, subthreshold leakage up to 10s of nA
In 45nm, oxide is so thin that gate leakage becomes
comparable to subthreshold

State-of-the-Art and Predicted Future

Transistor are not properly OFF
Era of dark silicon
Turn off power from parts of chip

Slide 9 VLSI Circuit Design, 9. CMOS Layout Design

 Deep Sub Micron Progress

http://www.nature.
com/nnano/journal
/v7/n3/fig_tab/nna
no.2012.7_F2.html

http://www.zdnet.com/blog/computers/why-intels-22nm-technology-really-matters/5703

Slide 10 VLSI Circuit Design, 9. CMOS Layout Design

 CMOS Structure & Layout

PHYSICAL FABRICATION

SPECIFYING MASKS

DRAWING LAYOUTS

Slide 11 VLSI Circuit Design, 9. CMOS Layout Design

 Example Structure

Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Slide 12 VLSI Circuit Design, 9. CMOS Layout Design
 Example Structure

GND substrate tap nMOS transistor pMOS transistor well tap VDD

Slide 13 VLSI Circuit Design, 9. CMOS Layout Design

 Mask Views

Six masks for n-well

a very simple n well

process
Polysilicon
Polysilicon

n+ diffusion
n+ Diffusion

p+ diffusion
p+ Diffusion

Contact
Contact

Metal
Metal

Slide 14 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Start with blank wafer

Build inverter from the bottom up

p substrate

Slide 15 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

n-well: Oxidation

Slide 16 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

n-well: Photoresist

Slide 17 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Mask

n-well: Lithography
Light

Photoresist
SiO2

p substrate

Slide 18 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

n-well: Etch

Slide 19 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

n-well: Diffusion

Slide 20 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

n-well: Strip Oxide

Slide 21 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Forming the Gates

Polysilicon
Thin gate oxide

n well
p substrate

Slide 22 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Polysilicon

Gate: Polysilicon Patterning

Polysilicon
Thin gate oxide

n well
p substrate

Slide 23 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Transistor formation:
Self-Aligned Process

n well
p substrate

Slide 24 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

n+ Diffusion
Transistor: N-diffusion

n well
p substrate

Slide 25 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Transistor: N-diffusion

n+ n+ n+
n well
p substrate

Slide 26 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Transistor: Strip Oxide

n+ n+ n+

n well
p substrate

Slide 27 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Transistor: P-Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

Slide 28 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

Forming Contacts

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

Slide 29 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

M e ta l
Metalization

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

Slide 30 VLSI Circuit Design, 9. CMOS Layout Design

 Fabrication Steps

GND substrate tap nMOS transistor pMOS transistor well tap VDD

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

Slide 31 VLSI Circuit Design, 9. CMOS Layout Design

 Drawing Layouts

Specifying Masks

GND substrate tap nMOS transistor pMOS transistor well tap VDD

Slide 32 VLSI Circuit Design, 9. CMOS Layout Design

 Layout Overview
Chip/Die designs are specified with set of masks
Minimum dimensions of mask features determine:
Transistor size and die size
Hence speed, cost, and power

“Historical” Feature size f = gate length (in nm)

Set by minimum width of polysilicon
Other minimum features tend to be 30 to 50% bigger
Feature size improves 30% every 2 years or so
= 1/ 0.7 reduction factor every “generation”
from 1 m (1000 nm) in 1990 to 22 nm in 2012.
10 generations in 20 years
1000, 700, 500, 350, 250, 180, 130, 90, 65, 45, 32, and 22 nm

Rules for designing masks called Design or Layout Rules

Often “normalized” for portability across generations

Slide 33 VLSI Circuit Design, 9. CMOS Layout Design

 Determining a Design Rule
and a Mask Bias

Slide 34 VLSI Circuit Design, 9. CMOS Layout Design

 Determining a Design Rule

What is the minimum spacing between a poly gate and a contact?

?

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
Slide 35 VLSI Circuit Design, 9. CMOS Layout Design
 Factors Determining a Design Rule

Mask alignment accuracy

How accurate is one mask aligned to another mask?

Process variation
If cutting a hole, how much do the sides of the cut vary?
If implanting dopants, how much does the width of the diffusion vary?

How conservative do you need to be to assure good process yield?

30 to 40 mask levels
5 to 10 process steps per mask level

Slide 36 VLSI Circuit Design, 9. CMOS Layout Design

 Mask Sequence

Align each mask to n-well

the previous mask n well

Polysilicon
Polysilicon

n+ diffusion
n+ Diffusion

p+ diffusion
p+ Diffusion

Contact
Contact

Metal
Metal

Slide 37 VLSI Circuit Design, 9. CMOS Layout Design

 Alignment Marks

How close can one mask be aligned to another in a 0.5 m process?

Example:
Mean: 0 nm
Standard Deviation: 50 nm
= 50 nm = 84% Contact
= 100 nm = 98% P
= 150 nm = 99.87%
o
l
y
But alignment is not direct
Contact aligns to P+active
P+active aligns to N+active
N+active aligns to poly

How much variation is the alignment from Contact to Poly?

Slide 38 VLSI Circuit Design, 9. CMOS Layout Design
 Poly Variation

How much does the width of the poly vary with processing?
Example:
Mean (one side) = 60 nm (undercut)
Standard Deviation (one side) = 30 nm
= 90 nm

? Mask biased to compensate

for mean undercut

Resist

Undercut Poly

Silicon

500 nm

Slide 39 VLSI Circuit Design, 9. CMOS Layout Design

 Contact Hole Variation

How much does the size of the contact hole vary?

Example:
Mean = + 50 nm
Standard Deviation = 40 nm
= 120 nm

? Mask biased to compensate

for mean undercut

Resist Resist
Undercut
SiO2 SiO2

Silicon

600nm

Slide 40 VLSI Circuit Design, 9. CMOS Layout Design

 Minimum Oxide Width

Cannot have source or drain short to the gate

What is minimum spacing with variation?
Example: 200 nm

WMIN

SiO2
Al SiO2
Poly

Silicon

Slide 41 VLSI Circuit Design, 9. CMOS Layout Design

 Design Rule Summary

Mask Alignment
variation is 3 * 150 nm = 260 nm
Poly Variation
= 90 nm
Contact Variation
= 120 nm
Minimum Contact-to-Poly Breakdown Space
200 nm
Sum of the minimum and variations:
670 nm
Is this the correct value for the rule?
Design Rule:
nm Why?
What about Bias/Offset?
Slide 42 VLSI Circuit Design, 9. CMOS Layout Design
 How can the rule be improved?

Change alignment sequence

Align poly to n-well
Align n+active to poly
Align p+active to poly
Align contact to poly
Align metal to contact

Change alignment from t3 to t1

Alignment variation reduces from 260 nm to nm

Design Rule changes from nm to nm

Slide 43 VLSI Circuit Design, 9. CMOS Layout Design

 What do you do with Biases?

Layout is done without biases

Biases are added post layout in mask processing
Example: Contacts
Layout

600 nm 600 nm 600 nm

Mask
Contact is shrunk by
50 nm on each side
during Mask Making
process
500 nm 700 nm 500 nm

Slide 44 VLSI Circuit Design, 9. CMOS Layout Design

 Circuit Interconnect Layout

Slide 45 VLSI Circuit Design, 9. CMOS Layout Design

 Simplified CMOS Process

SiO2 gate oxide polysilicon

NMOS PMOS SiO2

field
n well oxide
n diffusion
p diffusion
p silicon substrate

Slide 46 VLSI Circuit Design, 9. CMOS Layout Design

 Wiring with Metal and Contacts

Metal (Al)

NMOS PMOS

Contact cut

Slide 47 VLSI Circuit Design, 9. CMOS Layout Design

 Transistors of Same Type in Series

Can’t do this with opposite types!

NMOS NMOS

connected by shared diffusion

Slide 48 VLSI Circuit Design, 9. CMOS Layout Design

 Connecting Poly and Diffusion
Can’t contact poly to diffusion directly!

NMOS NMOS

Slide 49 VLSI Circuit Design, 9. CMOS Layout Design

 The Book’s 65nm Process

Slide 50 VLSI Circuit Design, 9. CMOS Layout Design

 The Book’s 65nm Process - Up to Metal 2

MOSIS Design Rules

Slide 51 VLSI Circuit Design, 9. CMOS Layout Design
 The Book’s 65nm Process - Metals

MOSIS Design Rules

Slide 52 VLSI Circuit Design, 9. CMOS Layout Design

 65nm Design Rules Rule Description
65nm
(nm)
5.1, 6.1 Width (exact) 80

poly or active)
Contact (to
5.2b, 6.26 Overlap by poly or active 10
5.3, 6.3 Spacing to contact 100
5.4, 6.4 Spacing to gate 70
65nm 5.5b Spacing of poly contact to other contact
Rule Description (nm) 5.7b, 6.7b
6.8b
Spacing to active/poly for mult. Contacts
Spacing of active contact to poly contact
1.1 Width 500 7.1 Width 90
Well

Metal3 Metal2 Metal1

1.2 Space to well at different potential 700 7.2 Spacing to same layer of metal 90
1.3 Space to well at same potential 700 7.3,8.3 Overlap of contact or via 10
7.4 Spacing to metal for lines wider than 10 300
2.1 Width 100
(diffusion)

9.1…. Width 100

2.2 Spacing to active 120
Active

9.2, … Spacing to same layer of metal 100

2.3 Source/drain surround by well 150 9.3, … Overlap of contact or via 10
9.4, … Spacing to metal for lines wider than 10 300
2.4 Substrate/well contact surround by well 150
15.1 Width 100
2.5 Spacing to active of opposite type 250 15.2 Spacing to metal3 100
3.1 Width 65 15.3 Overlap of via2 10
Spacing to metal for lines wider than 10
Poly (i.e.

3.2 Spacing to poly over field oxide 100 15.4 300

Gate)

3.2a Spacing to poly over active 100 15.1 Width 400

Metal
15.2 Spacing to metal3 400

8-9
3.3 Gate extension beyond active 100 15.3 Overlap of via2 100
3.4 Active extension beyond poly 100 15.4 Spacing to metal for lines wider than 10 500
3.5 Spacing of poly to active 70 8.1,14.1 Width (exact) 100
Via Via1
3…6 Via2
8.2.14.2 Spacing to via on same layer 100
4.1 Spacing from substrate/well to gate 150
(n or p)
Select

8.1,14.1 Width (exact) 100

4.2 Overlap by poly or active 120 8.2.14.2 Spacing to via on same layer 100
4.3 Overlap of substrate/well contact 120 8.1,14.1 Width (exact) 200
7,8
Via

4.4 Spacing to select 200 8.2.14.2 Spacing to via on same layer 200

Slide 53 VLSI Circuit Design, 9. CMOS Layout Design

 A Simplified Rule System

RULES

Slide 54 VLSI Circuit Design, 9. CMOS Layout Design

 Rules

A simplified, technology generations independent design rule system

Express rules in terms of = f/2

E.g. = 0.3 mm in 0.6 mm process
Called “Lambda rules”

Lambda rules are NOT used in commercial applications

Lambda rules need to be very conservative and thus waste space

Lambda rules are good for education!

MOSIS SCMOS SUMB Rules
See Book Front Inside Cover

Slide 55 VLSI Circuit Design, 9. CMOS Layout Design

 Simplified Design Rules

Conservative rules to get you started (W&H Fig. 1.39) Missing Rule:
Poly to Dif Contact

http:// http://www3.nd.edu/~cse/2013fa/40462/links.html

Slide 56 VLSI Circuit Design, 9. CMOS Layout Design

 Transistor Width and Length

Dimensions of Gate Overlap over Source/Drain Diffusion

= Active area of a transistor

Transistor Width W Transistor Length L

Perpendicular to traveling Parallel to traveling
direction of carriers direction of carriers

Typically Width >> Length

Slide 57 VLSI Circuit Design, 9. CMOS Layout Design

 Substrate and Well Taps

Substrate needs to be tied to Ground

Why?

N-well needs to be tied to VDD

Why?

Slide 58 VLSI Circuit Design, 9. CMOS Layout Design

 Rules (compared to 65 nm)
Green: lambda rules significantly smaller Red: lambda rules significantly larger

Lambda Rules
65nm Eqvt
Rule Description (nm) 65nm in 180 130 90 65 45 32 28 22 10
1.1 Width 500 390 12 1080 780 540 390 270 192 168 132 60
Well

1.2 Space to well at different potential 700 585 18 1620 1170 810 585 405 288 252 198 90
1.3 Space to well at same potential 700 195 6 540 390 270 195 135 96 84 66 30
2.1 Width 100 98 3 270 195 135 98 68 48 42 33 15
(diffusion)

2.2 Spacing to active 120 98 3 270 195 135 98 68 48 42 33 15

Active

2.3 Source/drain surround by well 150 195 6 540 390 270 195 135 96 84 66 30
2.4 Substrate/well contact surround by well 150 98 3 270 195 135 98 68 48 42 33 15
2.5 Spacing to active of opposite type 250 130 4 360 260 180 130 90 64 56 44 20
3.1 Width 65 65 2 180 130 90 65 45 32 28 22 10
Poly (i.e.

3.2 Spacing to poly over field oxide 100 98 3 270 195 135 98 68 48 42 33 15
Gate)

3.2a Spacing to poly over active 100 98 3 270 195 135 98 68 48 42 33 15

3.3 Gate extension beyond active 100 65 2 180 130 90 65 45 32 28 22 10
3.4 Active extension beyond poly 100 98 3 270 195 135 98 68 48 42 33 15
3.5 Spacing of poly to active 70 33 1 90 65 45 33 23 16 14 11 5
4.1 Spacing from substrate/well to gate 150 98 3 270 195 135 98 68 48 42 33 15
(n or p)
Select

4.2 Overlap by poly or active 120 65 2 180 130 90 65 45 32 28 22 10

4.3 Overlap of substrate/well contact 120 33 1 90 65 45 33 23 16 14 11 5
4.4 Spacing to select 200 65 2 180 130 90 65 45 32 28 22 10

Slide 59 VLSI Circuit Design, 9. CMOS Layout Design

 Rules (compared to 65 nm)
65nm Eqvt
Rule Description (nm) 65nm in 180 130 90 65 45 32 28 22 10
5.1, 6.1 Width (exact) 80 65 2 180 130 90 65 45 32 28 22 10
poly or active)
Contact (to

5.2b, 6.26 Overlap by poly or active 10 33 1 90 65 45 33 23 16 14 11 5

5.3, 6.3 Spacing to contact 100 98 3 270 195 135 98 68 48 42 33 15
5.4, 6.4 Spacing to gate 70 65 2 180 130 90 65 45 32 28 22 10
5.5b Spacing of poly contact to other contact 163 5 450 325 225 163 113 80 70 55 25
5.7b, 6.7b Spacing to active/poly for mult. Contacts 98 3 270 195 135 98 68 48 42 33 15
6.8b Spacing of active contact to poly contact 130 4 360 260 180 130 90 64 56 44 20
7.1 Width 90 98 3 270 195 135 98 68 48 42 33 15
Metal3 Metal2 Metal1

7.2 Spacing to same layer of metal 90 98 3 270 195 135 98 68 48 42 33 15

7.3,8.3 Overlap of contact or via 10 33 1 90 65 45 33 23 16 14 11 5
7.4 Spacing to metal for lines wider than 10 300 195 6 540 390 270 195 135 96 84 66 30
9.1…. Width 100 98 3
9.2, … Spacing to same layer of metal 100 98 3
9.3, … Overlap of contact or via 10 33 1
9.4, … Spacing to metal for lines wider than 10 300 195 6
15.1 Width 100 163 5 450 325 225 163 113 80 70 55 25
15.2 Spacing to metal3 100 98 3 270 195 135 98 68 48 42 33 15
15.3 Overlap of via2 10 65 2 180 130 90 65 45 32 28 22 10
15.4 Spacing to metal for lines wider than 10 300 195 6 540 390 270 195 135 96 84 66 30
15.1 Width 400 0 0 0 0 0 0 0 0 0
Metal

15.2 Spacing to metal3 400 0 0 0 0 0 0 0 0 0

8-9

15.3 Overlap of via2 100 0 0 0 0 0 0 0 0 0

15.4 Spacing to metal for lines wider than 10 500 0 0 0 0 0 0 0 0 0
8.1,14.1 Width (exact) 100 65 2 180 130 90 65 45 32 28 22 10
Via Via1
3…6 Via2

8.2.14.2 Spacing to via on same layer 100 98 3 270 195 135 98 68 48 42 33 15

8.1,14.1 Width (exact) 100 0 0 0 0 0 0 0 0 0
8.2.14.2 Spacing to via on same layer 100 0 0 0 0 0 0 0 0 0
8.1,14.1 Width (exact) 200 0 0 0 0 0 0 0 0 0
7,8
Via

8.2.14.2 Spacing to via on same layer 200 0 0 0 0 0 0 0 0 0

Slide 60 VLSI Circuit Design, 9. CMOS Layout Design