Tanner Tools Tutorial PDF

Table of Contents
Table of Contents
Chapter 1 Introduction..................................................................................................................... 6
1.1. Typographic Conventions ................................................................................................... 6
1.2. Installation .......................................................................................................................... 7
Chapter 1 S-Edit Introduction .......................................................................................................... 8
Chapter 2 Getting Started with S-Edit .............................................................................................. 9
2.1. Loading a design ................................................................................................................. 9
2.2. Viewing the Design ........................................................................................................... 10
2.3. Navigating the Design Hierarchy....................................................................................... 11
2.4. Elements of a Symbol View............................................................................................... 12
2.5. Elements of a Schematic View .......................................................................................... 16
Chapter 3 Evaluated Properties ..................................................................................................... 20
3.1. Annotate Port Properties .................................................................................................. 21
Chapter 4 Callbacks ........................................................................................................................ 24
Chapter 5 Saving Designs ............................................................................................................... 27
Chapter 6 Creating a New Schematic Cell ...................................................................................... 28
6.1. Placing Instances ............................................................................................................... 28
6.2. Making Connections ......................................................................................................... 31
6.3. Placing Input and Output Ports......................................................................................... 33
6.3.1. Moving Instances with Rubberbanding ...................................................................... 35
Chapter 7 Creating a New Symbol ................................................................................................. 37
7.1. Automatic Symbol Generation and Update...................................................................... 37
7.2. Editing the Symbol ............................................................................................................ 37
Chapter 8 Checking the Schematic................................................................................................. 39
Chapter 9 Highlighting Nets ........................................................................................................... 41
Chapter 10 Simulating the Design .................................................................................................. 43
10.1. Simulating a design ........................................................................................................... 43
10.2. W-Edit ............................................................................................................................... 46
10.3. Probing Voltages, Currents, and Charges ......................................................................... 50
Chapter 11 Viewing Voltages, Currents, and Charges on the Schematic....................................... 58
11.1. Viewing results on the schematic ..................................................................................... 58
2
Table of Contents
Chapter 12 Busses and Arrays ........................................................................................................ 60

Chapter 13 Customizing the setup ................................................................................................. 62
Chapter 14 L-Edit Introduction....................................................................................................... 64
Chapter 15 Getting Started with L-Edit .......................................................................................... 65
15.1. Loading a design ............................................................................................................... 65
15.2. Introduction to L-Edit’s User Interface ............................................................................. 66
15.3. Zoom and Pan Operations ................................................................................................ 67
15.4. Navigating the design hierarchy ....................................................................................... 67
15.5. Select Operations .............................................................................................................. 71
15.6. Drawing and Editing Operations ....................................................................................... 76
15.7. Reviewing the Layout ........................................................................................................ 81
15.7.1. Showing and Hiding Objects ....................................................................................... 81
15.7.2. Showing and Hiding Layers......................................................................................... 82
Chapter 16 SDL Introduction .......................................................................................................... 86
Chapter 17 Getting started with L-Edit Schematic Driven Layout (SDL) ........................................ 87
17.1. Opening the design ........................................................................................................... 87
17.2. Setting up cell blocks for SDL ............................................................................................ 88
17.3. Importing a netlist using SDL ............................................................................................ 89
17.4. Using flylines to place devices .......................................................................................... 92
17.5. Tagging geometry on manually placed routes.................................................................. 94
17.6. Setting up the automatic router ....................................................................................... 96
17.7. Automatic routing ............................................................................................................. 98
17.8. Ripping up nets ............................................................................................................... 101
17.9. Importing an Engineering Change Order (ECO) .............................................................. 101
Chapter 18 T-Cell Builder: Automatically Construct T-Cells ......................................................... 103
18.1. Creating a mosfet with T-Cell Builder ............................................................................. 103
18.2. Stretching Elements And Defining Parameters............................................................... 103
18.2.1. Repeating Elements Instead Of Stretching............................................................... 105
18.3. Choose Layer ................................................................................................................... 106
18.4. Define Conditional Inclusion ........................................................................................... 107
18.5. Select T-Cell Objects........................................................................................................ 108
18.6. Creating a resistor with T-Cell Builder ............................................................................ 109
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Table of Contents
Chapter 19 HiPer PX Quick Start Guide ........................................................................................ 110

19.1. Running HiPer PX ............................................................................................................ 110
19.2. Finding or Creating the Technology Files ........................................................................ 110
19.3. Exporting Layout Data..................................................................................................... 111
19.4. Extracting Layout ............................................................................................................ 112
4
List of Exercises
List of Exercises
Exercise 1 - Load an existing S-Edit Design ...................................................................................... 9
Exercise 2 - Setting up and simulating a design in S-Edit ............................................................... 43
Exercise 3 - Viewing results in W-Edit ............................................................................................ 47
Exercise 4 - Working with Traces in W-Edit ................................................................................... 56
Exercise 5 - Load an existing L-Edit Design .................................................................................... 65
Exercise 6 - Zooming and Panning ................................................................................................. 67
Exercise 7 - Investigating the Design Navigator ............................................................................. 68
Exercise 8 - Opening a cell ............................................................................................................. 70
Exercise 9 - Selecting and editing objects and edges..................................................................... 72
Exercise 10 - Drawing Objects........................................................................................................ 76
Exercise 11 - Editing Objects .......................................................................................................... 79
Exercise 12 - Show/Hide Objects ................................................................................................... 81
Exercise 13 - Show/Hide Layers ..................................................................................................... 83
5
Chapter 1 1.1 Typographic Conventions
Introduction
Chapter 1
Introduction
Tanner Tools is a complete flow for IC design including schematic capture, analog simulation,
physical layout and verification. In this tutorial you will learn about:
 Schematic capture with S-Edit
 Analog simulation with T-Spice
 Waveform viewing with W-Edit
 Physical design with L-Edit
 Schematic driven layout with SDL
 Creating T-Cells from layout with T-Cell Builder
 Physical Verification with HiPer
 Parasitic Extraction with PX
1.1. Typographic Conventions

This section describes typographic conventions that are used in this document.
Bold Indicates elements that are a part of L-Edit, such as toolbars, menus, and buttons.
Italics Indicates elements that are part of the tutorial design, such as cell names,
instance names, and properties.
6
Chapter 1 1.2 Installation
Introduction
1.2. Installation
The first time you run L-Edit after installation, the following dialog appears, asking if you wish to
setup the examples and tutorial.
If you installed the tutorial when you first installed L-Edit, then the tutorial can be found in the
location that you specified for the tutorial files. The default location for the tutorial on XP is My
Documents\Tanner EDA\Tanner Tools v16.0\L-Edit\Tutorial. The default location for the
tutorial on Vista and Windows 7 is Documents\Tanner EDA\Tanner Tools v16.0\L-Edit\Tutorial.
Tutorial and example files may be installed at any time by invoking Help > Setup Examples and
Tutorial from L-Edit, or by invoking All Programs > Tanner EDA > Tanner Tools v16.0 > Setup
Examples and Tutorial from the Windows start menu.
After running the tutorial, modified tutorial files can be replaced with a fresh copy of the
tutorial files by invoking Help > Setup Examples and Tutorial, and choose Repair, when asked
to select between Modify, Repair, or Remove.
7
Chapter 1 1.2 Installation
S-Edit Introduction
Chapter 1
S-Edit Introduction
S-Edit is a schematic capture tool for use by circuit design engineers. In this tutorial you will
learn about:
 Opening a design
 Viewing designs and navigating design hierarchy
 Elements of a symbol
 Elements of a schematic
 Saving designs
 Creating your own schematic and symbols
 Simulating Designs and probing results
 Highlighting nets
8
Chapter 2 2.1 Loading a design
Getting Started with S-Edit
Chapter 2
2.1. Loading a design

Use the File > Open > Open Design command to load an S-Edit design.
Exercise 1 - Load an existing S-Edit Design
Step 1. Invoke File > Open > Open Design…, press the Browse button, ( ), in the Open
Design dialog, and browse to the RingVCO.tanner file in the RingVCO folder of the
tutorial folder. The default location for the this design is My Documents\Tanner
EDA\Tanner Tools v16.0\Designs\RingVCO, although you may have installed it in
another location. Press OK in the Open Design dialog.
The RingVCO tutorial will load into S-Edit, and look like this. On the left side of the application
window, we have the Library Browser, on the bottom, we have the Command/Log window,
and on the right, we have the Properties Browser. In the center is the top level schematic of
our design.
9
Chapter 2 2.2 Viewing the Design
Properties
Library Browser
Browser
List of Schematic
cells Window
Symbol
preview Command /
Log Window
This project consists of a design called Ringvco, which references several libraries. The libraries
referenced are Devices, Misc, SPICE_Commands, and SPICE_Elements. The design is shown in
black, and libraries are shown in blue in the list of libraries in the top pane of the Library
Browser.
2.2. Viewing the Design

Let’s examine the Library Browser, located on the left side of the application.
 Select the design or one of the libraries in the top pane, and you can see the
list of cells contained in that library. You can select multiple libraries in the
top pane and see all the cells in the selected libraries. Use Shift+Click or
Ctrl+Click to select multiple libraries.
 Select all the libraries in the design in the top pane. You can filter the list of
cells shown in the cell list by typing a substring match in the filter field. Type
MOS into the filter field, and see now only those cells containing a substring
MOS are shown in the list of cells.
 Click on the Filter dropdown in the library browser and change it to Top-
level. Top-level filter will show only those cells that are not instanced
anywhere in the design. You can type a substring match into the filter to
further filter the results.
 Click on the filter dropdown and select Leaves. Leaves are cells that have
no instances in their schematic. You can type a substring match here too, to
further filter results. Return the Filter dropdown to Filter and clear out the
filter substring.
 Select different cells in the cell list, and see a preview of their symbol in the
Preview Pane below the cell list.
10
Chapter 2 2.3 Navigating the Design
Getting Started with S-Edit Hierarchy
 You can right-click anywhere on the Library Browser and toggle on/off
display of the Preview Pane.
Let’s pan and zoom around the design.
 Use the +/- keys to zoom in and out of the design.
 Scroll the mouse wheel to zoom in and out of the design, centered at the
cursor.
 Use the arrow keys to pan up/down/left/right.
 Press and release the Z key, then click and drag the left mouse button over
a region to zoom into that region (“create a zoom box”).
 Use the Home key to fit the entire contents to the window.
2.3. Navigating the Design Hierarchy

Now let’s navigate around the design. There are several ways to open a schematic or symbol
view of a cell.
Double click on the symbol in the center labeled RingVCO to open its schematic.
 Double click on one of the Diffcell symbols to view its schematic.
 You can also open symbol or schematic views by right clicking on the
desired cell in the cell list of the Library Browser, selecting Open View,
then choosing the view you want to open. The view type is indicated first,
followed by the view name. The view name is only displayed if there are
multiple views of the same type. Open the symbol view of the 4-terminal
NMOS cell using this method. If you don’t see NMOS in the cell list, then you
need to select the Devices library in the list of libraries. You call also select
all the libraries in the list to see all cells.
 Views can also be opened by double clicking on a cell in the cell list. The
view opened (symbol, interface, or schematic) will be of the same type as
the last opened view. Double click on cell NFET in the list of cells to open
the symbol view of NFET. If multiple views exist, a list will be displayed to
select the desired view.
 You can also select a cell and press the Open button in the Library browser
to open a cell. This behaves the same way as double click. Select the
DiffCell cell in the cell list, and press the Open button to open its symbol
view.
11
Chapter 2 2.4 Elements of a Symbol
Getting Started with S-Edit View
 Pressing the drop down arrow next to the Open button lets you pick the
specific view of the selected cell you wish to open. Open the schematic view
of the control cell in this manner.
 Lastly, views may be opened using the Cell > Open View command. Use
this method to open the schematic view of cell RingVCO_TestBench in this
manner.
 When opening a view, you can force the new view to open in a new window
by holding the Ctrl key down when opening the new view.
 You can use the View Symbol ( ) and View Schematic ( ) toolbar
buttons to open the Symbol or Schematic view that corresponds to the
currently active window. Close all windows, and open the schematic view of
DiffCell. Press the View Symbol button to see the symbol for DiffCell.
Pressing the “?” key will toggle between symbol and schematic views of a
cell. Close all open views.
 The Back and Forward buttons ( ) on the Standard toolbar can be
used to navigate to previous and next views. The forward button is only
enabled after backing up using the back button. Open the Schematic view of
RingVCO_TestBench. Double click on the symbol for RingVCO to open the
schematic for RingVCO. Now double click on one of the symbols of DiffCell
to open its schematic. Now use the Back and Forward buttons to navigate
back and forward to previous views and to next views. Now close all views.
2.4. Elements of a Symbol View

Now let’s examine a symbol. Open the symbol view of cell PMOS, a PMOS transistor, using any
method.
12
Port
Symbol
Graphics
Properties
 A symbol view contains the following elements:
 Symbol Graphics: Symbol graphics comprise the graphical image of the

symbol. This is the image you see when the symbol is instanced. Symbol
graphics can be boxes, polygons, paths, or circles, and are shown in green
above.
 Labels: Text labels can be added to a symbol, and are visible when the
symbol is instanced.
 Ports: Ports define the connection points that can be made to the symbol
when the symbol is instanced. In the figure above, these are the S, D, G, and
B shown in purple. When instanced, ports do not show their text, but appear
as an open circle “hot spot” for connecting a wire.
 Properties: Properties are name-value pairs that are usually used to describe
some characteristic of a device, such as a transistor length, width, or
Source/Drain areas and perimeters. Properties can also be used for other
purposes, such as controlling the SPICE statements written for a device.
Properties on a symbol provide the default values when that symbol is
instanced, but may be overridden on an instance-by-instance basis.
 The toolbars used for creating the objects on a symbol are:

 The Draw toolbar for creating symbol graphics and labels:
13
 The Electrical toolbar for creating Ports and Properties: Ports may be of type
In, Out, In/Out, Other, and Global.
Lets examine symbol properties in more detail:

 Properties for the symbol are visible on the symbol itself, and also in the
Properties browser. User properties such as Drain Area (AD), Source Area
(AS), Length (L) etc. are shown in the User area of the Properties Browser.
System properties such as the Design/Library from which the symbol comes
(Design), and the cell name (Cell) are shown in the System area of the
properties Browser.
14
 The properties on a symbol are default properties that are used when the
symbol is instanced.
 You can easily change the value of any property by placing the cursor in the
value entry of the property grid and entering a new value. Properties can
also be added using the Add button on the toolbar, and deleted using the
Delete button.
 Properties can be an explicit value, can reference another value, and can be
an expression. For example, the value of L is 0.25u and the value of W is
2.5u. Property TW, the total width of the PMOS is an expression which
references the value of properties M and W using the “$” as a reference.
When the PMOS is instanced, the value of TW will get resolved to TW =
M*W. If the values of M and W are not locally overridden on the instance,
then TW = 1*2.5u = 2.5u.
 Properties AD, AS, PD and PS use expressions with the “if (expr, expr,
expr)” function to calculate the source and drain areas and perimeters based
on the length “L”, the width “W”, the multiplicity “M”, and the
GatePerimeterFactor. Note that Calc.Odd and Calc.OuterArea are sub-
properties of property Calc. Sub-properties are referenced using a period as
separator between levels.
 A property on a symbol can be made visible, hidden, or only the value visible
when the symbol is instanced. Click on the (+) next to the AD property, and
see its Display value is set to Hidden. Click on the grid on the word Hidden
and Click the drop down control to see the possible choices Hidden,
Visible, and ValueOnly. Close the properties for AD by pressing the (+)
next to AD, and inspect the Display property for L, see its Display property is
Visible. Hidden and Visible/Value Only properties are rendered in slightly
different colors on the screen to easily distinguish which are visible and
which are hidden. The Display property specifies how the property is
displayed when in evaluated mode. The DisplayWhenNotEvaluated property
sets how the property is to be displayed when not in evaluated mode.
 Inspecting the properties on the symbol for PMOS, we see that W, L, and M
have their Display set to Visible, ANNOTATE.Drain, ANNOTATE.Gate, and
ANNOTATE.Source have their Display set to ValueOnly, and all other
properties have their display set to hidden.
 Properties may also be edited in place, without the properties grid. Double
click on property W to get the following dialog to edit its value. Press Cancel
to dismiss the dialog.
15
Chapter 2 2.5 Elements of a Schematic
 Properties may also be moved to different locations. Right click on a

property to select it, and then hold the middle mouse button to move the
property.
2.5. Elements of a Schematic View

Now let’s examine a schematic. Open the schematic view of cell DiffCell.
Properties
Symbol
Instance
Port
Net
 A schematic view contains the following elements:
16
 Instances of symbols: Instances of symbols refer to a particular symbol in a

cell. A schematic may contain many instances of the same symbol or of
different symbols. Instances contain graphics, which provide the illustration
of the symbol, and ports, which provide connection points for attaching nets.
Ports on the symbol and ports on the instance are different in that ports on
the symbol are shown as their port name, whereas ports on the instance do
not show the port name but are simply a “hot spot” for connecting a net.
 Nets: A net is a wiring connection between two or more instance ports. A net
can be a single wire, or can be a collection of wires called a bus or a bundle.
 Properties: Properties are name-value pairs that are usually used to describe
some characteristic of a device, such as a transistor length, width, or
Source/Drain areas and perimeters. Properties can be put on an instance to
override symbol values, or new properties can be created on an instance.
 Ports: Ports on the schematic correspond to the ports on the symbol. Ports
on the schematic define how connections made to ports on symbol instances
connect to nets on the schematic for that symbol.
 Annotation graphics: Annotation graphics are non-electrical objects such as
boxes, polygons, paths, and labels used to add comment or illustrations to
the schematic.
Now let’s examine the contents of DiffCell:

 Annotated in square brackets in the list of cells in the Library browser you
can see what cells and how many of each cell are instanced in the
schematic. Make sure both Ringvco and Devices are selected in the library
list. Cell DiffCell contains 1 instance of Gnd, 2 instances of NMOS, 4
instances of PMOS, and 1 instance of Vdd.
Let’s examine some instance properties in more detail:

 Select instance N1 of cell NMOS located near the bottom of the schematic.
You can see all the properties of the instance N1 in the properties browser.
17
 Notice that only those properties that were designated as Visible or Value
only on the symbol of NMOS are visible on the instance N1 in the schematic
window.
 Values may be overridden on an instance-by-instance basis. Property
values that are only on an instance and not on the symbol, or are overrides
over symbol values are shown in black in the properties browser, property
values that are inherited are shown in blue. For instance N1, notice that
property L has a value of 2.0u, which overrides the value of 0.25u on the
symbol.
 You can revert an overridden property value back to its symbol value by
selecting that property and pressing the Reset button (blue up-arrow) on the
property browser. Select the L property of instance N1 in the property
browser, and press the reset button. See the value changes from 2.0u (and
18
black, meaning local override) to 0.25u (and blue, meaning inherited). Press
Ctrl-Z to undo the change.
 You can modify the values of multiple instances at once. Select the
instances N1 and N2, the bottom two NMOS instances in the schematic.
The property browser displays those values that are the same for all
selected instances, and leaves blank those property values that are different
for the selected instances. Change the value of L to 10u. Select each
instance individually and see that each now has the new values. Change the
values back to 2.0u.
 You can use the Library browser to easily select all instances of symbol and
then change properties on all of them. Select an instance in the schematic.
Note that the selection in the list of cells in the Library browser is updated to
correspond to the selected symbol. Select an instance of cell PMOS on the
schematic or select PMOS directly in the list of cells. Now press the Find
button and all instances of cell PMOS will be selected in the schematic. You
can now change properties on all the selected symbols, or do any other
operation on the selections.
 Properties may also be edited in place, without the properties grid. Hold
down the Ctrl key, and double click on a property a dialog to edit its value.
Press Cancel to dismiss the dialog.
 Properties may also be moved to different locations. Hold down the Ctrl key
and right click on a property to select it, and then hold the middle mouse
button to move the property.
Close all views, and open the schematic view of RingVCO_TestBench.
19
Evaluated Properties View
Chapter 3
Evaluated Properties
We saw in Elements of a Symbol View, properties can be an explicit value, or can be an

expression. We will now explore the full capability of evaluated properties. Expressions support
standard mathematical operators -, *, /, **, as well as standard functions sin(), cos(), etc.
Expressions can also reference the vales of other properties using the following prefix operators:
 %T (or %{T}) references the name of the node connected by the terminal
T. When viewing a cell "in context" (see Probing Voltages, Currents, and
Charges) this name is the hierarchical name of the net.
 $P corresponds explicitly to another property on the same instance, or in
symbol view to another property on the symbol. For example,
TW=$W*$M, references the width and the multiplicity of the same
device. This option corresponds to the Cadence iPar() function.
 ?P references the parent cell's property, but only looks up one level. As
usual, overridden properties on the instance of the parent have higher
priority than the default value on the symbol. This option corresponds to
the Cadence pPar() function.
 @P (or @{P}) in a property value references the highest-level definition
of P. If we have a cell TOP which contains an instance of MID, which
contains an instance of BOT, then the priority order of a property P
"inside" BOT is then (high to low): global, MIDINST.P, MIDSYM.P,
BOTINST.P, BOTSYM.P.
 We have already seen the $ prefix used to compute the value of the TW
property as TW = ${W}*${M}, in the symbol view of the 4 terminal PMOS.
 Open the schematic view of DiffCell, Select P4 (the rightmost instance), and
see in the properties browser that the value of W is ?W. To find the value of
?W we look up one level, i.e. on the instance of DiffCell to find the value of
W. We see that all the instances of DiffCell have the same value of W, which
is ?WP. Looking up one level at the instance of RingVCO, we see it as a
property WP = 5.00u. Therefore, the value of W on P4 will be 5.00u.
 To see the values of evaluated properties we must navigate through the
hierarchy “in context”. Viewing a schematic “in context” refers to viewing a
specific hierarchical path of that schematic. Since evaluated properties refer
to other properties on a hierarchical path, we must have a hierarchical path
in order to evaluate properties.
 To navigate the hierarchy in context, first select an instance, then press the
Push into context button ( ) on the toolbar. To pop back up the
hierarchy, press the Pop context button, ( ). Select the RingVCO symbol
20
Chapter 3 3.1 Annotate Port Properties
and push into the RingVCO. You can also push into a cell by double clicking
on its symbol with the cursor in selection mode. Push into the third from the
left DiffCell instance, Xa3.
 When you push in context into a cell, S-Edit will display the hierarchical path
on the title bar of the schematic window. In our example we started in cell
RingVCO_TestBench, pushed into instance X1 of cell RingVCO, and then
into Xa3 of cell DiffCell, so the title bar of the schematic window will display
RingVCO_TestBench/X1/Xa3.
 To display the values of evaluated properties, press the Display Evaluated
Properties button ( ). We can now see the evaluated

value of W on P4 on the schematic view as 5u. Also, properties in the
property browser display their evaluated values. Values are shown in green
in the property browser to indicate we are showing evaluated values.
 Now select P1 (topmost instance of PMOS). See the values of AD, AS, PD,
PS display their evaluated values.
 If you Display Evaluated Properties without a hierarchical path, property
values will display as <property is not evaluated>.
3.1. Annotate Port Properties

Using evaluated properties, we can display several values of interest at the ports of an instance.
These include:
 Port name
 Net name
 DC Voltage
 DC Current
 DC Charge
The first two of these are always available to display, the next three depend on values being
present from a DC simulation run.
 We saw on the symbol view of the 3 or 4 terminal PMOS , there were some
special properties on the symbol of our MOSFET:
 ANNOTATE.Drain = [annotate port D]
 ANNOTATE.Gate = [annotate port G]
 ANNOTATE.Source = [annotate port S]
 ANNOTATE.Bulk = [annotate port B] (4 terminal PMOS only)
 The key elements of these properties are i) only the property value is
important, the property name can be anything, and, ii) the property value
contains the string annotate port portname in square brackets, where
portname is the name of a port on the symbol. Open the symbol view of the
4 terminal PMOS and see these properties.
 These annotate properties, when placed on a symbol (or on individual
instances), can display the port name, net name, DC voltage, DC current,
DC charge, or nothing. Which of these values is displayed is controlled by
21
the Display Evaluated Properties button and dropdown on the Simulation

toolbar.
 Next open RingVCO_TestBench, and run Tools > Design Checks. This is
needed to extract the netlist, we will discuss more on design checks later.
Open the RingVCO in context by double clicking on it, then open Xa3 in
context. Press the Display Evaluated Properties button (selecting the
Annotate Port dropdown as Name if not already selected). See the
annotate properties now display the port names, S, G, D (B is not shown
because it’s Display property is set to hidden):
 Now select Net in the Display Evaluated Properties dropdown to make the
annotate properties display the hierarchical net names, Vdd, X1/Vb1,
X1/Vb2, X1/Xa3/N_1, and X1/Xa3/N_20:
 You can also choose None to display nothing for the annotate properties.
22
23
Callbacks
Chapter 4
Callbacks
Callbacks provide the ability to call a tcl command upon changing a property value. The
callback command is usually a user written function. Typical uses of callbacks are to perform
validity checking of the input or to modify other properties that should change in order to
maintain consistency with the modified property.
 Open the symbol view of the 4 terminal PMOS, and in the property grid,
expand property “L” and see that it has a callback function named
CheckSpecificDimension.
 The function CheckSpecificDimension checks that the value the user
has entered is in a specified range, is snapped to a specified grid, and
returns an error message if these conditions are not met.
 Open the schematic view of cell DiffCell, and select P1 (near the top of
the schematic). Note that it has values L=0.25u. Now change the value of L
to 0.25 (remove the u) and see the following message:
This dialog is coming from the callback function.
24
Callbacks
 Functions CheckSpecificDimension are user written functions listed

below:
proc CheckSpecificDimension { sDimensionName sPropertyName
nMinMaxBoth sMinimumDimension sMaximumDimension
{ sProcName "" } } {
global dMfgGrid
global gdTOLERANCE
set dMinimumDimension [ stod $sMinimumDimension ]
set dMaximumDimension [ stod $sMaximumDimension ]
set dDimension [ stod [ property get $sPropertyName ] ]
set dSnappedDimension [ gNearestMultiple $dDimension

$dMfgGrid ]
if { [expr abs($dDimension-$dSnappedDimension) ] >
$gdTOLERANCE } {
set sMsg "$sDimensionName is not on the
manufacturing grid. $sDimensionName has been
snapped to [dtos $dSnappedDimension]"
tk_messageBox -message $sMsg -type ok -icon error
property set $sPropertyName -value [dtos

$dSnappedDimension ]
set dDimension $dSnappedDimension
}
set sMsg ""

if { ($nMinMaxBoth == 0) && ($dDimension <
$dMinimumDimension) } {
set sMsg "$sDimensionName is too small. [dtos
$dMinimumDimension] <= $sDimensionName"
} elseif { ($nMinMaxBoth == 1) && ($dDimension >
$dMaximumDimension) } {
set sMsg "$sDimensionName is too big.
$sDimensionName <= [dtos $dMaximumDimension]"
} elseif { ($nMinMaxBoth == 2) && (($dDimension <
$dMinimumDimension) || ($dDimension >
$dMaximumDimension)) } {
set sMsg "$sDimensionName is out of range.
[dtos $dMinimumDimension] <= $sDimensionName
<= [dtos $dMaximumDimension]"
}
if { $sMsg != "" } {
tk_messageBox -message $sMsg -type ok -icon error
return $sMsg
}
if { $sProcName != "" } {
eval $sProcName
}
}
 The callback functions must be defined in S-Edit before they can be called.
This is done either by dragging the file containing the callbacks into the
25
Callbacks
command window, or by placing the file in one of the folder locations from
which scripts get automatically loaded:
Scripts placed in a folder scripts/open.design in the design folder will get
automatically loaded when the design is opened. We have placed the file
GeneralCallbacks.tcl in this location in the Devices library.
Other locations from which scripts are automatically loaded are:
To load script when any C:\Documents and Settings\<username>\Application Data\Tann
er EDA\scripts\open.design
design is opened, place script
in:
To load script when S-Edit is C:\Documents and Settings\<username>\Application Data\Tann
er EDA\scripts\startup
started, place script in:
To load script when S-Edit is C:\Documents and Settings\<username>\Application Data\Tann
er EDA\scripts\shutdown
shutdown, place script in:
26
Saving Designs
Chapter 5
Saving Designs
Before we proceed with the tutorial, let’s learn how to save the design, so we can save the
modifications we will be making in the next section. The File > Save menu is shown below:
There are four ways of saving a file:

 File > Save > Save Design DesignName saves modifications to the design,
but does not save modifications to any libraries.
 File > Save > Save Design DesignName and Its Libraries saves
modifications to the design and all libraries.
 File > Save > Save # Selected Design/Libraries saves those
Design/Libraries that are selected in the list of libraries in the Library
browser.
The Save Copy of … command saves a copy of the selected Design and Libraries in the Library
Browser to a new location on disk. The Save Copy of … command is not the same as a Save As
command in that after the command is issued, the application is still editing the original design,
not the newly saved design.
27
Chapter 6 6.1 Placing Instances
Creating a New Schematic Cell
Chapter 6
Now let’s learn how to create our own schematic. If you wish to skip the steps to create the
inverter cell, we have provided a completed cell called InverterFinished.
 First, create a new cell called Inverter. Invoke Cell > New View. We want to
create the new cell inside the design Ringvco, so enter the following into the
New View dialog:
Design: Ringvco
Cell: Inverter
View type: schematic
View name: view_1
Interface name: view_1
 After pressing OK, you will get an empty drawing area for a new schematic
view.
6.1. Placing Instances

 Select PMOS in the cell list from the Devices library, and press the Instance
button below the cell list. The Instance Cell dialog will appear, as shown
below. You can zoom in and out using the +/- keys or the mouse scroll
wheel, or pan using the arrow keys, before placing the instance.
 In the Instance Cell dialog, you can change the instance name or properties
of the cell you are about to instance. Changing properties will make local
overrides over the symbol default values. Change the instance name to P1.
Make sure the Interface and Symbol View are PMOS4, for the 4-terminal
PMOS.
 Place an instance of PMOS by clicking on the schematic drawing window.
28
Drag
instance with
mouse, click
to place.
Change
property
values before
placing an
instance
using the
Instance Cell
dialog.
 Additional instances of PMOS can be placed by continuing to click the

mouse to place instances. Instances can be flipped horizontally or vertically
prior to placement by pressing the “H” or “V” key and may be rotated prior to
placement by pressing the “R” key. Properties for each instance can be
modified in the Instance Cell dialog prior to each placement. In the
schematic for the inverter, we only need one PMOS, so we’ll proceed to
change the cell we are instancing.
 You can change the instance name by entering a new Instance Name in the
Instance Cell dialog. You can also change the cell being instanced by
selecting a new Cell name in the Instance Cell dialog.
29
Change instance
name.
Choose a new cell

to instance.
 Select cell NMOS in the Instance Cell dialog, change the instance name to
N1, make sure the Interface and Symbol View are NMOS4, and place the
NMOS below the PMOS by clicking on the schematic view at the location
you wish to place the instance.
 Now place an instance of the Gnd connected to the bottom (source) port of
the NMOS and an instance of Vdd connected to the top (source) port of the
PMOS. The Gnd and Vdd symbols are in the Misc library.
 Notice that ports on symbols are displayed with an unfilled red box when
they are not connected. When connected either directly to another symbol,
or with a wire, the box becomes filled, indicating that a connection has been
made.
 Exit instance mode by either pressing the right mouse button, pressing the
ESC key, or pressing the Done button on the Instance Cell dialog.
 The placed instances should appear as follows:
30
Chapter 6 6.2 Making Connections
Vdd
PMOS
NMOS
Gnd
6.2. Making Connections

 Connect the gate (G) ports of the two MOSFETs together by drawing a wire
from one to the other. To draw a wire, select the Wire drawing button on the
toolbar, ( ), the click the left mouse button to place the first vertex,
subsequent clicks with the left mouse button will place additional vertices.
Clicking the right mouse button ends the wire without placing a vertex, and
double clicking the left mouse button will end the wire with placing a vertex
at the double click location. Pressing the ESC key will abandon the entire
wire.
 Unconnected symbol ports and unconnected wire ends are shown as open
circles. When a wire end is properly connected to a symbol port, the open
circles disappear, indicating that they are properly connected. Similarly for
two ports or two wires connecting directly to each other.
 Now you try connecting the two gate ports together. Click the left mouse
button on the open circle of the gate port of the PMOS symbol, drag the
mouse down to draw the wire, click the left mouse button on the open circle
of the NMOS symbol, then click the right mouse button to end the wire.
31
Chapter 6 6.2 Making Connections
Connect
gate ports
together
 Now connect the two drains together.
Connect
drain ports
together
 Now connect the source and bulk ports of the PMOS to Vdd and connect the
source and the bulk ports of the NMOS to Gnd.
32
Chapter 6 6.3 Placing Input and Output
Creating a New Schematic Cell Ports
Connect PMOS
bulk to Vdd
Connect
NMOS bulk to
Gnd.
6.3. Placing Input and Output Ports

 Now let’s place input and output ports on our inverter. Ports may be of type
In, Out, In/Out, Other, and Global. To place an In port, click the In Port
button on the Electrical toolbar ( ), drag the mouse over the schematic
and place the port on the schematic by clicking the left mouse button. Place
the port to the left of the schematic, approximately vertically centered.
Place In
port
33
 After clicking the left mouse button to place the port, a dialog will appear to
set the port name, and size and justification parameters. Give the port the
name “A” and set Orientation to “West”, and press OK.
 Multiple ports can be consecutively placed by selecting Enable Auto-

repeat. This will allow you to continue click-placing ports. If Confirm text of
each object is checked, then the dialog appears after each click allowing you
to change the port name. If Confirm text of each object is not checked then
the dialog will not subsequently appear, and you can place as many ports as
you wish. Press the right mouse button or press the ESC key to exit port-
placing mode. If the port name ends in a digit, then when multiple ports are
placed in succession, the number will increment by the Auto-repeat value in
the dialog.
 Now connect port A to the wire that connects the gates.
Connect port A
34
 Now place a port named “Y” of type Out as shown, and connect it to the wire
that connects the two drains. Use the Out port button ( ) to start. Give the
Out port Right alignment.
Place and
connect port Y
6.3.1. Moving Instances with Rubberbanding

Now lets look at S-Edit’s rubberbanding capability that keeps wires connected to instances
when moving instances.
 Select the PMOS and Vdd instances at the top of the schematic, as well as
the attached wires, by drawing a selection box as shown below. First enter
selection mode by pressing the Select toolbar button ( ), then press and
hold down the left mouse button, drag a rectangle as shown, then release
the mouse button.
35
 Now press and hold the middle mouse button while dragging the mouse up
or down to move the two instances without breaking any connections.
 You can move instances, forcing them to detach from connected wires by
invoking Draw > Force Move (ALT-M shortcut key) before performing the
move operation. Invoke force move, then select the PMOS instance by right
clicking on it, then press and hold the middle mouse button and drag the
mouse to move it. See that the instance moved, breaking away from its
connections. Invoke Edit > Undo (Ctrl-Z) to return the instance to its original
position.
36
Chapter 7 7.1 Automatic Symbol
Creating a New Symbol Generation and Update
Chapter 7
Creating a New Symbol
Now let’s make a symbol for our inverter.

 Invoke Cell > New View, and select Ringvco for design, Inverter for the
cell, and symbol for view type. Enter view_1 for View name and Interface
name.
 After pressing OK, you will get an empty drawing area for a new symbol
view
7.1. Automatic Symbol Generation and Update

 S-Edit can auto-generate a symbol from the ports on the schematic. Invoke
Cell > Update Symbol, and S-Edit will create a symbol as shown below:
 If the symbol view is empty, Update Symbol will create simple graphics and
place ports corresponding to those on the schematic. It will also place text
labels corresponding to each port. If a symbol already exists with graphics or
ports, Update Symbol will add the new ports from the schematic to the
symbol view, but will not modify the graphics or remove any existing ports.
7.2. Editing the Symbol

 We can now easily modify this symbol to make a symbol more suitable for
an inverter. Draw a triangle for our symbol using the path drawing tool. To
37
Chapter 7 7.2 Editing the Symbol
Creating a New Symbol
draw a path, select the Path drawing button on the toolbar, ( ), then select
the All Angle button on the segment toolbar, ( ), then click the left mouse
button to place the first vertex, subsequent clicks with the left mouse button
will place additional vertices. Clicking the right mouse button ends the wire
without placing a vertex, and double clicking the left mouse button will end
the path with placing a vertex at the double click location.
 Draw a circle at the right vertex of the triangle by pressing the circle drawing
button on the toolbar. Press the left mouse button at the center of the
desired circle, and drag the mouse to create the circle.
 Delete the box that was placed by Update Symbol. Press the Select button
on the toolbar ( ), click on the box to select it (it will highlight when
selected) and press the delete key to delete the box.
 Move the ports and labels onto the new graphics you have drawn, as shown
below. When in selection mode, you can drag a region with the mouse to
select all objects in the region. Then hold the middle mouse button and
move the mouse to move objects. You can also change the text size of the
ports and labels using the properties browser.
 Your completed symbol should look like this:
38
Checking the Schematic
Chapter 8
S-Edit’s Design Check tool can check the schematic for many of the common mistakes made
during the schematic creation process. These are categorized into errors, which will prevent a
proper connectivity from being formed, and warnings, which do not prevent connectivity
extraction but may be unintended mistakes by the user. Some of the common items the design
checker will check for include:
 Dangling wires – wires with unconnected ends.
 Dangling ports – ports on instances with no connection
 Instances with no name or non-unique name.
 Nets have at most one output port reference connected to them.
 Ports with the same name have the same type.
Now let’s place our inverter in the RingVCO_TestBench and check for errors. If you skipped the
steps to draw the inverter, you can use the inverter_finished cell provided.
 Open the schematic of RingVCO_TestBench and place an instance of
Inverter to the right of the schematic.
Place
instance of
Inverter
39
 Draw a wire to connect net Out to the input of the Inverter. However, we will
intentionally leave a gap in the connection for the design checker to catch
later. Place an instance of PrintVoltage and connect to the output of the
inverter, as shown below. Next, we aim to place a net label called Buffered
on the net from the output of the inverter to the PrintVoltage, however lets
misplace it slightly off the net.
Leave gap in
connection.
Misplace
netlabel
off the
wire
 Now, invoke Tools > Design Checks, or press the Check view and
hierarchy button ( ), to perform a schematic check. The design checker
will report warnings for the unconnected wire end, the unconnected symbol
port, and the unconnected net label. The following warnings appear in the
log window:
# CHK Warning: Cell: RingVCO_TestBench, Port "A" on instance "inv1" is dangling.
# CHK Warning: Cell: RingVCO_TestBench, Wire: Out is dangling.
# CHK Warning: Cell: RingVCO_TestBench, netlabel: Buffered is dangling.
# CHK Warning: Cell: RingVCO_TestBench, Net: "Buffered" in schematic: is not connected to any port.
# SED Design check complete. Design: RingVCO and 0 libraries, 5 cells and 10 views have been checked. 0
errors and 4 warnings were found.
 Click on the link “A” to pan and zoom the schematic to the unconnected port
on the inverter.
 Fix the connection from net Out to the inverter, and move the netlabel
“Buffered” onto the net from the inverter to the PrintVoltage instance.
 The design checker will find errors and warnings in the active schematic
view, and in any schematic view in its hierarchy.
40
Highlighting Nets
Chapter 9
Highlighting Nets
Now let’s highlight some nets.

 Close all windows, and open the schematic view of cell
RingVCO_TestBench. Select any object on the net that is the input to the
RingVCO. Select the netlabel “In”, for example.
Select
netlabel “In”
 Double click on the RingVCO, and see that the net is highlighted as you
push into an instance.
 Double click on the rightmost DiffCell, instance Xa9, and see that the net
continues to be highlighted as you navigate down the hierarchy.
41
Highlighting Nets
 Now click on port Outp, and pop up a level of hierarchy using the Pop
context button ( ), and see that nets can be traced both up and down
hierarchy.
 In schematic of RingVCO, select port Outm on the right. Highlight the entire
net Outm within the current schematic view by invoking Tools > Highlight
Net, or press the Highlight Net toolbar button ( ). See the selected net is
highlighted. You can select any object on a net and invoke Highlight Net to
highlight a net.
 You can also highlight nets by name. In the Command Window, type find
net VTune, and see the VTune net is highlighted.
42
Chapter 10 10.1 Simulating a design
Simulating the Design
Chapter 10
Now let’s run SPICE simulation using the T-Spice engine. First let’s examine the simulation setup.
In this section you will navigate the design hierarchy and learn different ways to open a cell.
10.1. Simulating a design
Exercise 2 - Setting up and simulating a design in S-Edit
Step 1. Close all windows and open the schematic view of RingVCO_TestBench.
Step 2. The schematic view of RingVCO_TestBench has been setup with 2 DC voltage source
as inputs to the circuit. Print commands have been placed on the input net, and on the
output net. These designate the nets for which voltages will be plotted in the waveform
viewer during simulation.
Step 3. Press the Simulation Setup button on the toolbar to invoke the Simulation Setup
dialog. We have selected to run a DC Operating Point Analysis, a Transient Analysis,
and a parametric sweep.
43
Step 4. Arguments for each type of simulation may be set by selecting that simulation type in
the list. Click on different types to see their parameters. For our transient analysis, we
have set a Stop time of 100ns, and a step time of 100ps. We also selected Powerup
as our Startup mode. Power-up will ramp up the DC voltage sources from 0 to their
values during the first 1ns of the simulation. The default power-up length is 2ns but in
this simulation we have set it to 1ns.
44
Step 5. We have setup a parameter sweep of the Cap parameter which sets the parasitic
capacitance on the output of the RingVCO.
Step 6. Click the Run Simulation button in the Simulation Setup dialog.
In S-Edit, use the Simulate button, ( ), to run the simulation.
Results will appear in W-Edit, displaying the voltage waveforms for the nodes we
indicated with the PrintVoltage commands.
45
Chapter 10 10.2 W-Edit
10.2. W-Edit
Simulation
Navigator Traces
Navigator
Variation
Navigator
The Simulation Navigator lets you open and close chartbooks, and add and remove simulations.
Each new simulation gets added to the simulation navigator with the latest simulation being at
the end/bottom of the list.
The Variation Navigator lets you turn on or off the display of different variations (sweeps, alter,
etc.) in the simulation and also set dependent variables so they can be assigned display
characteristics.
The Traces Navigator is used to manage which traces are displayed in a chart. The traces from
all open simulations are loaded in the navigator list. You can filter the traces to easily find the
traces you want to plot. The Traces Navigator supports flat or hierarchical browsing of signals,
and you can filter by signal name, by type (V, I, Q) and by analysis in multi-analysis simulations.
Traces are colored in the Traces Navigator to indicate their type as follows:
 Black – not currently loaded to a chart.
 Brown – used in the active chart and originally from a simulation, including scalars.
46
 Red – present in database but not from simulation and not arithmetic.
 Blue – arithmetic traces.
 Gray – hidden traces.
 Green – scalars.
You can drag and drop a trace from the navigator list to load and display it in a chart. When a
scalar is the result of a sweep, then the drag and drop operation into a DC/Parametric chart will
plot the scalar versus the sweep variable.
You can also right-click anywhere within the traces navigator to access Add to Active Chart, as
well as a variety of other trace commands.
Shift+dragging and dropping a measurement scalar into a chart creates a dynamic text label
with the value “name=[measure calc name]” which will display the measurement result from T-
Spice.
Exercise 3 - Viewing results in W-Edit
Step 1. To change the color for each variation of a sweep, first change the Variable 1: in the
Variation Navigator to the sweep variable Cap.
Step 2. Open the Setup – Trace Styles dialog using Setup > Trace Styles.
Step 3. Change the Color dropdown to use Variable1 for the different colors and click
Close.
47
Step 4. To view only a single variation of the simulation, right click on the variation in the
Variation Navigator, and select Hide all But Selected Variations.
Change the Trace Styles back to Traces to color each trace with a different color.
Step 5. Open the Setup – Trace Styles dialog using Setup > Trace Styles.
Step 6. Change the Color dropdown to use Traces for the different colors and click Close.
Step 7. To view a measurement versus a sweep variable, first create a DC/Parametric plot
using Chart > New Chart.
48
Step 8. Select the DC/Parametric type for the chart and give it a title.
Step 9. Click the exclude other traces filter button ( ) on the Traces Navigator to
only display those traces that are valid for the active chart’s type.
Step 10. Drag and drop RingFreq from the Traces Navigator to the plot.
49
Chapter 10 10.3 Probing Voltages,
Simulating the Design Currents, and Charges
10.3. Probing Voltages, Currents, and Charges

 We can probe voltages on any net in the circuit by first selecting the Probe
Voltage button, ( ), then clicking on the node we wish to probe. The
voltage of the probed node will then display in W-Edit.
 Switch back to the Chart1 in W-Edit by clicking on its tab.
 Select the Probe Voltage tool, and then probe net OutP in the schematic of
RingVCO_TestBench. The waveform of the voltage of OutP will be
displayed in W-Edit, as shown below.
 We can also probe results down the hierarchy. Using the voltage probe tool,
double click on the VCO symbol (instance named X1) to push in context into the
instance of that symbol.
50
Double click
on instance
of ringvco
with Voltage
probe tool
 Click on the bottom net (labeled Outp) to probe the voltage on that net.
Click to probe
net Outp
 Using the probe tool again, push into the third instance from the left of
DiffCell (instance named Xa3). To push into an instance, you can also select
the instance with the probe tool, then press the Push into context button (
) on the toolbar. To pop back up the hierarchy, press the Pop context
button, ( ).
51
Click on
net to
probe
voltage
 Probe the voltage on the internal node as shown above. Results will display
in W-Edit.
52
 You can probe Currents into the port of a symbol by selecting the Probe
Current button, ( ), then clicking on the port you wish to probe.
 Click on the red square showing the connection to the gate of instance N1,
as shown below, to probe the current into that gate.
53
Click on a
port to
probe
current
 The current of the probed port will then display in W-Edit.
54
 Similarly, if the simulation is setup to do so, charges can be probed by

selecting the Probe Charge button, ( ), then clicking on the terminal you
wish to probe. The simulation in this tutorial is not setup for probing charges.
 You can also display the small signal parameters of a primitive device by
probing that device. Double-click on the top instance of PMOS to see its
small signal parameters.
 Try navigating the hierarchy in context and probe different nodes.

 You can also export the SPICE netlist for the currently active schematic
view into T-Spice, and then in T-Spice you can add additional commands
for simulation. Open the schematic view of RingVCO_TestBench, and press
the T-Spice button, ( ), on the toolbar.
55
Exercise 4 - Working with Traces in W-Edit
You can select a trace by click on trace in the plot the with the left mouse button or by
clicking on its name in the trace legend.
Step 1. Click on the trace name Out:V(Cap=5f) in the trace legend to select that trace in the
plot. The cursor will turn to a hand when you can select the trace name.
You cannot click on the box before the trace name select a trace. The box indicates
the color of the trace in the plot.
Notice the selected trace is displayed in Yellow and its name becomes the last name in
the Trace Legend.
56
Step 2. You can expand the select trace into a new plot using the expand plot button ( ). If
no traces are selected, then it will expand each trace into its own plot.
You can also collapse the plots into a single plot by selecting traces in each plot and
then clicking the collapse plot button ( ).
57
Chapter 11 11.1 Viewing results on the
Viewing Voltages, Currents, and Charges on schematic
the Schematic
Chapter 11
Viewing Voltages, Currents, and Charges on the Schematic
11.1. Viewing results on the schematic

If you have not already done so, then begin this section of the tutorial by opening the schematic
view of RingVCO_TestBench and running simulation. Probe in context into the RingVCO, then
into the third DiffCell from the left, Xa3.
 DC operating point Voltages, Currents, and Charges can be displayed at the
ports of primitive elements using annotate port properties, as discussed in
the section Annotate Port Properties.
 Enable Display Evaluated Properties and select Voltage in the dropdown
to make the annotate properties display the DC operating point voltages at
the corresponding port locations:
58
Viewing Voltages, Currents, and Charges on schematic
the Schematic
 Select Current in the Display Evaluated Properties dropdown to make the

annotate properties display the DC operating point currents at the
corresponding port locations:
59
Busses and Arrays schematic
Chapter 12
Busses and Arrays
S-Edit supports arrays, busses and net bundles. First let’s describe nets, buses, bundles, and
arrays, then we’ll look at some examples. A net is the fundamental single unit of connection. A
bus is a set of connections with the same name and a numerical identifier and increment, and a
bundle is collection of nets and busses.
 An array is created by assigning an instance with an instance name
containing array syntax.
 Naming an instance array_name<n1:n2:step> creates an array of
instances named array_name<n>, where n starts at n1, ends at n2, and
increments by step. Step is 1 by default, and may be omitted. The
instance name U<0:7> defines an array of instances, with elements U<1>,
U<2>,…U<7>. Two-dimensional arrays may be created by naming an
instance U<n1:n2:step1><n3:n4:step2>. The second range increments
first. The instance name U<0:7><0:3> creates an array of instances
named
U<0><0>, U<0><1>, U<0><2>, U<0><3>,
U<1><0>, U<1><1>, U<1><1>, U<1><3>,
U<2><0>, U<2><1>, U<2><1>, U<2><3>,
…
U<7><0>, U<7><1>, U<7><1>, U<7><3>
 A bus is created by assigning a net a name using bus syntax.
 Similarly to arrays, naming a wire, using the net label tool,
bus_name<n1:n2:step> creates a bus of nets named bus_name<n>,
where n starts at n1, ends at n2, and increments by step. Step is 1 by
default and may be omitted. The name A<0:7> creates an 8 bit wide bus,
with nets A<1>, A<2>, … A<7>. Two-dimensional buses may be created
by naming a wire bus_name <n1:n2:step1><n3:n4:step2>. As with arrays,
the second range increments first.
Now we will look at our tutorial example.
 Cell RingVCO_ArrayBus is a redesigned copy of cell RingVCO, using an
array and buses. Close all windows and open the schematic view of cell
RingVCO_ArrayBus. See how we have redesigned the ringvco using an
array of diffcells.
60
Busses and Arrays schematic
 We have created an array of 9 diffcells by giving the diffcell instance the

name DiffCell<0:8>, The <0:8> component of the name designates the
instance as an array. Note the bundle Outm, N<0:7> connected to the inp
port of the diffcell and the bundle N<0:7>, Outm connected to the Outm port
of the diffcell. Also observe that buses can by named in the compact form
bus_name<n1:n2, step>, or can be expanded explicitly, naming each
component.
 Open cell RingVCO_TestBench, and replace the instance of RingVCO with
an instance of ringvcoBus.
 Export the SPICE netlist for RingVCO_TestBench, by pressing the T-Spice
button, ( ), on the toolbar. Note the arrays have been expanded into
individual subcircuits and the buses have been expanded into individual
connections, as SPICE does not support arrays and buses.
 Close T-Spice and press the Simulate button to run T-Spice simulation.
Additional examples of buses and arrays are available in the Examples folder that can be
installed from S-Edit, C:\Documents and Settings\<username>\My Documents\Tanner
EDA\Tanner Tools v16.0\Designs\BusesAndArrays.
61
Customizing the setup schematic
Chapter 13
Customizing the setup
Settings for various configuration parameters are available in the Setup menu.
 The following is the list of settings that are available:
 Colors – Sets the colors of objects in the schematic, such as wires,
symbol graphics, ports, labels, etc.
 Grids – Sets the Major, Minor, and Snap grids.
 Units – Sets the Units (mm, cm, meter, inch) and the size of an internal
unit.
 Validation – Sets the tcl procedures to call for validating cell names,
instance names, view names, port text and net labels.
 Protection – Set the Allow Edit option.
 General – Sets windowing behavior, to reuse windows or open a new
window each time a view is opened.
 Selection – Sets Selection options
 Text Editor and style – Sets Text Editor options.
 Invoke Setup > Technology >Schematic Colors
 Select different colors for Wires, Graphics, and various other elements. Note
that your changes take effect immediately. To save the new settings to the
design folder so they will be automatically present next time you load the
design, select {project setup folder} in the To/From folder, and press the
62
Customizing the setup schematic
Save button. If you do not save the settings, they will be in effect until you
close the design, but will not be there when you reload.
 Try changing some other settings on other pages in the Setup dialog.
63
L-Edit Introduction schematic
Chapter 14
L-Edit Introduction
L-Edit is an easy-to-use, high performance layout editor combining the fastest rendering
available with powerful features that exceed the needs of the most demanding user. This
leading analog/mixed signal IC design tool enables you to get started with minimal training. You
can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools.
In this tutorial you will learn about:
 Getting Started with L-Edit
64
Chapter 15 15.1 Loading a design
Getting Started with L-Edit
Chapter 15
This chapter guides you through some typical L-Edit viewing and editing operations used to
design IC layouts. You will create a new layout database file, navigate a design’s hierarchy, and
view layout.
This chapter covers:
 Loading a design
 Introduction to L-Edit’s User Interface
 Zoom and Pan Operations
 Navigating the design hierarchy
 Select Operations
 Drawing and Editing Operations
 Reviewing the Layout
15.1. Loading a design

Use the File > Open command to load an L-Edit design.
Exercise 5 - Load an existing L-Edit Design
Step 1. Open the design database for the tutorial using File > Open.
Step 2. In the Open Design dialog, browse to the file Tutorial.tdb in the RingVCO folder
of the tutorial folder.
The default location for the tutorial is My Documents\Tanner EDA\Tanner Tools

v16.0\L-Edit\Tutorial, although you may have installed it in another location.
65
Chapter 15 15.2 Introduction to L-Edit’s
Getting Started with L-Edit User Interface
Step 3. Press the Open button in the Open dialog and the design will load into L-Edit.
End of Exercise
15.2. Introduction to L-Edit’s User Interface

In L-Edit, layout designs are saved in a single database file with extension TDB (Tanner Data
Base). A complete L-Edit design is composed of layers, technology settings, and layout cells. You
can open as many design files simultaneously as your hardware allows. L-Edit displays the name
of the active file in the title bar.
Below are the major items of the L-Edit User Interface
 The Layer Palette displays the layers for the active design.
 The Design Navigator shows all cells in a design in a hierarchical display that includes
information about parent and child cells.
 The Mouse Button Bar displays the current function of each mouse button
66
Chapter 15 15.3 Zoom and Pan Operations
 The Aerial View shows the position of the current viewing window relative to the cell
boundary.
 The Details Button creates a text file containing a textual description of the selected objects.
15.3. Zoom and Pan Operations

You can zoom into or out of the current view to see more or less of the design. You can also
move (pan) around the design to see different portions of it at the current level of
magnification. All view commands affect only the active cell.
Exercise 6 - Zooming and Panning
Step 1. Open cell RingVCO_Completed using the Cell > Open command.
Step 2. Press the Home key on your keyboard. This will magnify the cell view such that all the
objects in the cell are shown.
Step 3. Use the + or – keys on your keyboard to zoom in and out from the current view.
Alternately, you can use Ctrl+Mouse wheel to zoom in and out.
Step 4. Select a specific object in the cell by clicking on the object with the right mouse button
RMB and then hit the W key. This will zoom to the selected object.
Step 5. Use the X key to toggle between the current view and the previous view.
Step 6. Use the arrow keys on your keyboard for panning. Shift+Mouse wheel will pan
the view horizontally. The mouse wheel will pan the view vertically.
Step 7. Select an object and use J and K keys to pan to the left/top or Right/bottom of the
object, respectively.
Step 8. Click File > Close to close Tutorial.tdb without saving.
End of Exercise
15.4. Navigating the design hierarchy

The Design Navigator is like a Windows Explorer for your design where it lists all the cells in a
design in a hierarchical structure, including information on T-Cells (parameterized cells), cell
status, number of instances used, XrefCell (externally referenced cell) and XrefFiles (external
library).
Menu: View Default Shortcut: F10 Toolbar: Standard Icon:
67
Chapter 15 15.4 Navigating the design
Getting Started with L-Edit hierarchy
The Design Navigator displays cells within the file similar to the way Windows
Explorer displays the files on your hard drive.
Pressing the F10 key arranges Design Navigator on the left and all layout and text windows on
the right.
If the layout window was originally maximized, pressing the F10 key toggles the
windows in L-Edit from normal mode to maximized mode.
Exercise 7 - Investigating the Design Navigator
Step 1. Open the design database for the tutorial using File > Open.
Step 2. In the Open Design dialog, browse to the file Tutorial.tdb in the RingVCO folder
of the tutorial folder.
Step 3. Click on the + button next to the DiffCell cell in the Design Navigator.
This will expand the hierarchical structure of the DiffCell and show all the sub-level
cells that are instanced in DiffCell. The number beside the cell name in brackets
indicates the number of times the cell has been instanced in the active cell.
68
The cells with link icon ( ) are XRefCells that are linked to a cell in another TDB
file. The cells with the lock icon ( ) are locked cells.
Step 4. Click on the view type dropdown in the Design Navigator and change it to Top down
– non-instanced.
An instance is a reference to another cell. This allows you to reuse parts of your layout
to make the design more modular, to layout the design more quickly and to make
updating the design easier. The Top down - non-instance filter will show only those
cells that are not instanced (referenced) anywhere in the design.
When a GDSII file is imported into L-Edit, the Top down- non instanced filter will
usually allow you to quickly find the top level cell of the design.
Step 5. Expand the + sign next to the RingVCO_Completed cell to see its hierarchical
structure.
The numbers in brackets indicate the number of times the lower-level cell has been
instanced in the parent cell.
Step 6. Click on the view type dropdown in the Design Navigator and select Bottom up –
all cells.
In this mode, cells are listed in terms of where they are instanced. When a cell is
instanced in other cells it is marked with a + and the cells which contains it as an
instance are listed below it. This allows you to look up the hierarchy so if you change a
cell, you can see which other cells will be affected.
Step 7. Click on the view type dropdown in the Design Navigator and select Top-down all
cells.
In this view, cells are hierarchically listed showing the instances they contain. This
allows you to look down the hierarchy.
End of Exercise
When a cell has been modified and not saved, it is written in bold letters in the
Design Navigator. When a cell or a file has been modified and not saved, an asterisk
symbol appears next to the cell name and file name in the title bar of the layout
window or application.
69
In this section you will navigate the design hierarchy and learn different ways to open a cell.
Exercise 8 - Opening a cell
Step 1. Double click on DiffCell in the Design Navigator.

This will open the DiffCell cell in a new window.
Step 2. Press the F10 key on your keyboard.
This will arrange the cell window and the Design Navigator to fit the L-Edit window.
Step 3. Close the DiffCell cell window by clicking the x in the upper left corner of the layout
window.
Step 4. Expand the + sign for Diffcell and select the subcell NMOS_Auto_2u_2.5u_1.
Step 5. Open the cell using the Cell > Open command.
This will open the T-Cell auto generated NMOS layout cell (NMOS_Auto_2u_2.5u_1) in
a new layout window.
Step 6. Close the NMOS_Auto_2u_2.5u_1 cell window.
Note that the focus returns to the Design Navigator.
Step 7. Click on the title bar for the Control cell window or anywhere in the Control cell
layout to move the focus to the layout window.
Step 8. Select the Cell > Open command and select the NFET cell .
This will display the NMOS T-Cell code in a text window.
Step 9. Select the File > Close command to close the T-Cell text window.
End of Exercise
70
Chapter 15 15.5 Select Operations
15.5. Select Operations

Selecting objects allows you to view information on the objects, edit the objects either
graphically or textually, or move the objects. More than one object may be selected at a time.
The selection tool is the first tool in the Drawing toolbar.
In selection mode, you can select objects and edges. You can also use your right
mouse button (RMB) to select objects and edges in any other drawing mode.
If several objects overlap each other, you can select a specific object by cycling through the
selections. This is done by continuing to click on the object without moving the mouse. It will
select next object after each click and the last click in the cycle will be no selection and then the
cycle repeats.
When cycling through selections, it is best to watch the status bar in the lower left
of the application to see which object is currently selected in the cycle.
Here is a table of common selection commands in L-Edit.

Select All F +A
Deselect All E +A
Add to Selection
G+ (RMB)
Remove From Selection

E+ (RMB)
Select Edge
F+ (RMB)
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Add Edge
F +G + (RMB)
Remove Edge
F +E + (RMB)
The ESC key (L) will cancel a drawing or editing operation. Pressing L again will
switch to the selection tool.
By default, selected objects are displayed with a black outline. Use the Setup >
Layers command (Rendering tab) to change the manner in which selected object’s
are displayed on a specific layer.
Exercise 9 - Selecting and editing objects and edges
We will now select single and multiple drawn objects, in order to edit them.
Step 1. Open cell Exercise 5.
Step 2. Place the mouse cursor inside the green box.
Step 3. Click with right mouse button (RMB) to select the box.
Step 4. Hold the G key down and click with RMB on the red box to add the box to
selection. Make sure you are not over both the red and purple box.
Step 5. Drag the middle mouse button (MMB) to move the selected objects by a small
distance.
When multiple objects are selected, editing operations such as Rotate, Flip, Slice,
Move By, etc. will affect all of the selected objects.
Step 6. Now click anywhere in the cell to deselect the selected objects.
We will now practice multiple edge selection and editing.
72
Step 7. Hold down the F key and using the RMB , click and drag starting at the top
center of the green box dragging horizontally to include the entire purple box and let
go when you get to just outside the lower left corner of the red box. See the diagram
below.
Step 8. You should have selected two edges and an entire box. While still holding down the
F key, use the MMB to click and drag to the right of the red box in order to
stretch the two edges and move the purple box.
This is very useful when the gates of MOSFETs need to be stretched to make room for
extra contacts.
73
Step 9. While still holding down theF key, use the MMB to click on the edge of the all
angle blue polygon to select its edge.
When holding down the F key, you will notice that the middle mouse function
changes to ARC, indicating that the MMB can be used to create a curved edge.
The middle mouse button operation changes to ARC when the F key is down,
only when the drawing mode is set to All Angle & Curves in Setup > Application –
General tab and the selected object is a polygon (not a box).
Step 10. With F key pressed, drag the selected edge using the MMB to create a
concave or convex arc as shown below.
74
Multiple edges can be added to a selection by using F+G+ (RMB) click on

the edges to be selected. Alternately, a drag box can be drawn around the edges to
be selected while holding the F key down.
Step 11. Deselect the selected edge by clicking anywhere in the cell where there are no
objects.
Step 12. Select the left edges of the red and green box as shown below:
Step 13. To select multiple edges, select the first edge by holding the F key down and
clicking with the RMB .
Step 14. Then select the next edge by holding the F+G key down and clicking with the
RMB .
75
Chapter 15 15.6 Drawing and Editing
Getting Started with L-Edit Operations
Step 15. Select Draw > Move By to move the edges by 5 um in the horizontal direction.
This will stretch both the objects 5um from their current position.
End of Exercise
15.6. Drawing and Editing Operations

There are several types of objects you can draw in L-Edit. Use View > Toolbars and check the
drawing checkbox to turn on the Drawing toolbar.
By default, L-Edit starts up in All Angle mode. All Angle & Curves mode can be changed by
going to Setup>Application- General tab and changing the Drawing mode in the Toolbars
group. You can also change it by right-clicking on the Drawing toolbar and selecting the mode
at the bottom of the context sensitive menu. When in All Angle mode, you cannot draw curved
objects. When in All Angle & Curves mode, you can draw curved objects and convert edges to
curves.
Exercise 10 - Drawing Objects
Step 1. Click Cell > New to open the Create New Cell dialog.
Step 2. Type the cell name as _Temp and press the OK button.
76
Step 3. Select layer Poly in the Layer Palette.
Step 4. Select the Box drawing tool by clicking on box icon in the Drawing toolbar.
Step 5. Draw a box of any size by using left mouse button (LMB) .
To turn on mouse tooltips, use the Setup > Application – Mouse tab and set the
option to Both Text and Pictures to show mouse button function under the mouse
cursor. This can help new users learn the different mouse functions more quickly.
Step 6. Now select the Orthogonal Polygon tool ( ) and draw an orthogonal polygon. To
draw the polygon, use LMB to place each vertex and use the RMB to
complete the polygon.
Step 7. Now draw an object using 45 degree polygon tool( ) and the all-angle
polygon tool ( ).
77
Step 8. Now draw a wire by using the orthogonal wire tool. To draw the wire, use the LMB
to place each vertex and use the RMB to complete the wire.
The default wire width for each layer is defined in Setup > Layers – General tab.
Step 9. Draw another wire using the 45 degree wire tool ( ) and use the drop down list
( ) to select a different wire width (select option other…,

and type width = 2) for the wire to be drawn. This will override the default wire width.
The ESC key (L) can be used to abort the drawing operation and to return to
selection mode ( ).
End of Exercise
78
You can edit objects graphically, using your keyboard or mouse. You can move, resize and
reshape objects, stretch edges, add vertices to polygons or wires, rotate, slice, merge, or nibble
(cut) objects.
These functions are available in the Draw menu or you can use the Editing toolbar (shown
below) to edit selected objects.
The icons in the Editing toolbar are enabled only when one or more objects are
selected in the active cell.
Exercise 11 - Editing Objects
Step 1. Select an orthogonal polygon you drew in the previous exercise by clicking on it with
the RMB .
When the mouse cursor is inside or outside a selected object(s), the MMB can be
used to move the object. For a two-button mouse, you can simulate the MMB by
79
holding down the E key and using the LMB . For a two-button mouse with a
wheel, the wheel can be pressed down as the MMB .
Step 2. With your mouse cursor inside the selected object, use your MMB to drag the
object and move it.
When the mouse cursor is on or near the edge of an object, dragging the MMB
will stretch the edge of that object.
Step 3. Place your mouse cursor on the edge of the selected object (until you see the Mouse
Button status bar MMB indicate Edit rather than Move) and use your MMB to
stretch it.
80
Chapter 15 15.7 Reviewing the Layout
Step 4. Select any object and click on the Rotate icon ( ) in the Editing toolbar.
This will rotate the object by 90 degrees in the counter clock wise direction.
Step 5. Similar to Step 4, flip the object by using one of flip icons.
Step 6. Select objects and try other functions in the Editing toolbar.
End of Exercise
L-Edit has the ability to do implicit object selection. If no objects are selected, pressing and
holding the MMB over an object will begin a move operation. If the cursor is near an
object’s edge (within the selection range) then pressing and holding the MMB begins an
edit or stretch operation. This can really streamline the editing process because you don’t have
to explicitly select objects or edges in order to modify them. Note that implicit selection is
governed by the values set for selection range and deselection range in the Setup > Design –
Selection tab.
You can have L-Edit highlight objects when you are within the selection range to
show implicit selections by setting the Highlight implicit selections option on the
Setup > Application – Selection tab. You can also turn off implicit selections on this
tab.
15.7. Reviewing the Layout

15.7.1. Showing and Hiding Objects
You can show or hide all objects of a specific type in a design. When you hide objects, L-Edit
indicates the hidden state by shading the object icon on the Drawing toolbar.
While object types are hidden, you cannot draw, select, edit, move, or delete those types of
objects.
To show and hide objects, you can check/uncheck each object type with the View > Objects
command.
Exercise 12 - Show/Hide Objects
Now we will show/hide the objects drawn in previous exercise.

Step 1. Keep the _Temp cell open.
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Step 2. Right-click on the Box tool ( ) and uncheck the Show option.
This will hide any boxes drawn in the active cell. You can also use the icons on the
Drawing toolbar to toggle the hidden state of a particular object type by positioning
the mouse cursor over the desired object’s toolbar icon and clicking the middle mouse
button.
Step 3. Click the middle mouse button on the Orthogonal polygon tool ( ).
This will hide all polygons drawn in the active cell.
Drawing tools such as Orthogonal Polygon, 45-Degree Polygon, All Angle Polygon,
Pie Wedge and Torus are grouped together such that a MMB click on anyone of
these tool icons will show/hide all the tools in this group.
Step 4. Now show all objects by right-clicking on any of the drawing tools and selecting
the Show All option.
When all objects are shown, to hide all objects except for a particular object type, position the
mouse cursor directly over the desired object icon in the Drawing toolbar and hold the F key
down and click with the MMB .
Observe the Mouse button status bar for functionality associated with each mouse
button when the cursor is over a Drawing toolbar icon.
End of Exercise
15.7.2. Showing and Hiding Layers

At any time, layer(s) can be shown or hidden for layout reviewing purpose. Hiding a few layers
also allows to user to clearly view how connectivity is established on certain layers. While a
layer is hidden, you cannot draw on that layer.
82
To show and hide layers, you can check/uncheck each layer with the Setup > Layers command.
The Layer Palette and its major parts are shown below.
Exercise 13 - Show/Hide Layers
Now we will show/hide the objects drawn in previous exercise.

Step 1. Open the Control cell in Tutorial.tdb.
Step 2. Right-click on the Metal1 layer in the Layer Palette and check the Hide > Hide
All but “Metal1” option.
This will hide all geometry on all layers except Metal1 throughout the hierarchy in the
active cell.
Step 3. Now click the MMB on the Poly layer in the Layer Palette.
This will show objects on the Poly layer in the active cell. Metal 1 will also be showing
because we showed that layer in step 2. You can also show or hide a layer by checking
or unchecking the box in the Hidden column ( ) for each layer in the Layer Palette.
83
The layer name in the Layer Palette will be filled with gray color when that layer is
hidden.
Step 4. Now show all objects on all layers by right-clicking on any layer and selecting
the Show > Show all option. The Show/Hide operation can be performed on multiple
layers at one time.
Step 5. Switch the Layer Palette filter to In Use in Cell + Hierarchy.
Step 6. Click on the layer header icon to sort the layers in alphabetical order.
Step 7. In the Layer Palette, select the Abutment layer.
Step 8. Hold the G key down and select the Keepout-Metal3 layer.
Step 9. Right-click on the selected layers and select the Hide > Hide Selected option.
84
Step 10. Right-click on any layer and select Show > Show All.
With the F key pressed down, click with the MMB on the layer name to
show/hide all layers except the one you are clicking on.
End of Exercise
85
SDL Introduction
Chapter 16
SDL Introduction
SDL is a schematic driven layout add on to L-Edit. In this tutorial you will learn about:
 Setting up cell blocks for Schematic Driven Layout (SDL)
 Importing a netlist using SDL
 Using flylines to place devices
 Tagging geometry on manually placed routes
 Setting up the automatic router
 Automatic routing
 Ripping up nets
 Importing an Engineering Change Order (ECO)
86
Chapter 17 17.1 Opening the design
Getting started with L-Edit Schematic Driven
Layout (SDL)
Chapter 17
Getting started with L-Edit Schematic Driven Layout (SDL)
17.1. Opening the design

Step 1. First, we need to open the design database for the tutorial. Invoke File > Open… and
browse to the Tutorial.tdb file in the tutorial folder. The default location for the tutorial
is My Documents\Tanner EDA\Tanner Tools v16.0\Designs\RingVCO, although you
may have installed it in another location. Press Open in the Open dialog.
Step 2. The RingVCO tutorial will load into L-Edit, and look like this. On the left side of the
application window, we have the Layer Palette. In the center left is the Design
Navigator, which provides a tree view of the cells and the hierarchy of the design and
in the center right is the layout for a portion of our design.
87
Chapter 17 17.2 Setting up cell blocks for
Getting started with L-Edit Schematic Driven SDL
Layout (SDL)
Layer
Palette
Design
Navigator
Layout
Window
Mouse
Buttons
Aerial
View
This project consists of a design called RingVCO, which contains T-Cells named NMOS
and PMOS, Contact Cells named Cnt_Active, Cnt_NTAP, Cnt_Poly,
Cnt_PTAP, Via_M1M2, Via_M2M3, and Via_M3M4. Additionally, the design
contains cell blocks named Control and DiffCell.
17.2. Setting up cell blocks for SDL

1. Let’s examine the Control cell to view the requirements for a cell block to be used
with SDL.
 Double-click the Control cell in the Design Navigator to open the cell layout if
it is not already open.
 Each device that is listed in your netlist should be a cell with pre-defined layout or
as a T-Cell prior to running SDL. The device name in the netlist must match the
cell name in your TDB file for that device to be instantiated during SDL from your
netlist. Cells that do not exist or do not match by name may be optionally
generated upon importing of the netlist for later layout.
2. First, let’s look at the ports that are used in the block.
 Hide everything in the layout but ports by CTRL+middle-mouse clicking the

Switch to drawing ports icon or by right-clicking the Switch to drawing
ports icon and selecting Hide All.
88
Chapter 17 17.3 Importing a netlist using
Layout (SDL)
 There are seven ports in the layout. Ports Vdd and Gnd are placed on the
Metal1 layer, Port Abut is placed on the Icon/Outline layer, and Ports Vb1, Vb2,
Vbias, and Vtune are placed on the Metal2 layer.
 Each I/O port must be placed on a routing layer for the SDL router to connect to it
and should be placed such that it is near the edge of the cell or can be easily
accessed with routes. If they are placed too close to one another, the SDL router
may not be able to connect to all the I/O ports. Ideally, the ports should be
placed on a specific routing grid so that the SDL router can directly access the
ports without having to branch off-grid.
 The dimensions of the ports will define the width of the routes that will connect to
that port. In this example, all the ports are box ports. In this case, the smaller
dimension of the port will determine the route width. If the smaller dimension is
less than the minimum specified route width, the minimum route width will be
used. For example, assuming the minimum route width specified for Metal1 and
Metal2 is 0.35u, Vdd and Gnd will be connected to using a 1.00u wire, as their
smallest dimension is 1.00u. Likewise, Vb1, Vb2, Vbias, and Vtune will be
connected to using a 0.65u wire. If two ports with different dimension are to be
connected together, the smaller of the two dimensions will be used.
 Unhide the objects previously hidden by CTRL+middle-mouse clicking the
Switch to drawing ports icon or by right-clicking the Switch to drawing
ports icon and selecting Show All.
3. Next, let’s look at the keepout region defined for the Control cell.
 Hide all layers with the exception of the keepout layers by selecting both
Keepout – Metal2 and Keepout – Metal3, right-clicking, and invoking Hide >
Hide all but selected.
 One keepout layer for each routing layer may be defined in the layout. The
keepout layer defines the region(s) where the routes may not go. In this
example, the routes may not pass over the active region of the transistors.
 Unhide the layers previously hidden by right-clicking any layer and invoking
Show > Show all.
4. Now, we need to make sure that there are contact cells defined
 Contact cells CNT_M1M2, CNT_M2M3, CNT_M3M4, and CNTPolyM1 are pre-

defined in the layout and will be assigned later in the router setup in order to
define how connections between layers are to be made.
17.3. Importing a netlist using SDL

5. First, let’s look at the netlist we will be importing into the layout.
 Open cell RingVCO by double-clicking the cell name in the Design Navigator.
89
Layout (SDL)
 Invoke Tools > SDL Navigator > Show SDL Navigator or right-click on the
toolbar and select SDL Navigator.
 Select the Load Netlist icon on the SDL Navigator toolbar to open the
Import Netlist dialog.
Select to
open Import
Netlist dialog
 Select Browse… to locate and load in the netlist RingVCO_Testbench.sps

into the From File: field. The file is located in the following location:
My Documents\Tanner EDA\Tanner Tools v16.0\L-Edit and
LVS\Tutorial\RingVCO_TestBench.sp
Press Edit to
view netlist.
Browse to
locate netlist.
90
Layout (SDL)
 Press Edit… to view the netlist. Scroll to the middle of the netlist to view the
subcircuit definition for RingVCO. The devices listed inside the subcircuit will be
instantiated into the RingVCO cell upon importing the netlist using SDL. Notice
there is one Control block and nine DiffCell blocks.
 SDL may be run on multiple blocks using the same top-level netlist file. If the
subcircuit name in the netlist does not match a cell name identically, the top-level
schematic will be used from the netlist.
 Close the netlist window.
6. Now, let’s import the netlist using SDL.
 Select the Load Netlist icon again on the SDL Navigator toolbar to open the
Import Netlist dialog.
 Select the following Modify layout and Create New Ports settings in the Import
Netlist dialog as shown.
91
Chapter 17 17.4 Using flylines to place
Getting started with L-Edit Schematic Driven devices
Layout (SDL)
Change Modify
layout settings as
shown.
Change Create
New Ports
settings as
shown.
Press OK to import
the netlist
 Press OK to import the netlist.
 Close the resulting log file.
17.4. Using flylines to place devices

7. Flylines can now be used to facilitate placing the blocks such that the layout is
compact and the routes are optimized.
 The devices are automatically placed next to each other in the layout and are all
selected.
 The SDL Navigator will contain the checklist of all nets in the layout that need to
be routed.
 To ensure all devices in the RingVCO cell are selected, press CTRL+A to select
all. There should be 6 ports and 10 instances selected.
 To view the flylines for all nets, select the Command Menu icon on the SDL
Navigator toolbar and invoke Add Selection Flyline. Colored flylines should
appear on the layout for each net segment as shown below.
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Chapter 17 17.4 Using flylines to place
Getting started with L-Edit Schematic Driven devices
Layout (SDL)
Select
Command
Menu
followed by
Add
Selection
Flyline.
 Select and drag each port or instance to create the shortest routing paths
possible for the design. The flylines will update as you move the ports and
instances.
 If you prefer to work with one or two nets at a time during placement, clear the
flylines by selecting the Remove All Markers icon on the SDL Navigator
toolbar. Select the net(s) in the SDL Navigator checklist that you want to work
with, and press the Flyline icon on the toolbar. Alternately, you may right-
click the net name(s) and invoke the Flyline selection.
 To toggle the flylines off and on, select the Toggle Markers icon on the SDL
Navigator toolbar. To clear the flylines, select the Remove All Markers icon
.
 You can view cell RingVCO_Placed for one example of how the instances and
ports may be placed.
93
Chapter 17 17.5 Tagging geometry on
Getting started with L-Edit Schematic Driven manually placed routes
Layout (SDL)
17.5. Tagging geometry on manually placed routes

8. Once the ports and instances are placed in the layout, critical nets may be manually
routed to ensure they have the shortest path and will not be routed by the SDL auto
router.
 Open cell RingVCO_Placed by double-clicking the cell name in the Design

Navigator.
 In this design, Vdd and Gnd are considered critical nets that should be manually
routed.
9. Manually placed routes should be tagged with their net name so that all geometry
associated with the net segment can be ripped up if needed.
 In this cell, the Vdd net segment was connected by overlapping the Vdd rails on
all instances. Therefore the Vdd checkbox is checked to indicate the completion
of routing for that net segment. No geometry was placed; therefore the net
segment does not need to be tagged.
 Geometry was added to the Gnd rail at the top of the layout to connect the XXC1
Control block to the XXa9 DiffCell block. To view the geometry already
placed and tagged, right-click net segment Gnd in the SDL Navigator checklist
and invoke Select Net. There should be 3 boxes and 2 instances selected and
all are tagged with the net name “Gnd”, as can be viewed in the Status Bar at
the bottom left of the L-Edit window.
10. Let’s complete the routing of the Gnd net segment and tag the geometry we place.
 Expand the symbol to the left of the Gnd net segment in the SDL Navigator to
view the pins associated with that net segment. Notice that XXa1/Gnd and
XXC1/Gnd are the only pins not checked off.
 Select the Gnd net segment in the SDL Navigator and press the Flyline icon
on the toolbar. This shows the connection that needs to be made between the
top and bottom Gnd rail.
 We want to make a wide metal (1.00u) connection between the rails on Metal1
along the left side of the layout. To do this, select the Metal1 layer from the
Layer Palette and the Switch to drawing orthogonal wires icon on the L-
Edit toolbar.
 Select the dropdown from the toolbar to set the wire width and select 1.000.
94
Chapter 17 17.5 Tagging geometry on
Getting started with L-Edit Schematic Driven manually placed routes
Layout (SDL)
 Enable object snapping to Midpoint by selecting the Setup Object Snap icon
on the L-Edit toolbar.
Select
Command
Menu
followed by
Add
Selection
Flyline.
 Right-click the Gnd net segment in the SDL Navigator and select Active Net.
Alternately, you can click on the Gnd net segment in the SDL Navigator with the
middle-mouse button to activate the net. The net name font will change to italics
to indicate that it is the active net. All geometry placed while the net is active will
be tagged as the Gnd net segment.
Activate the
Gnd net to
tag
geometry.
95
Chapter 17 17.6 Setting up the automatic
Getting started with L-Edit Schematic Driven router
Layout (SDL)
 Draw a wire connecting the upper Gnd rail to the lower Gnd rail.
Draw the
Gnd net
segment
using a 1.00u
wide wire.
 Turn off the active net by clicking on the Gnd net segment in the SDL Navigator
with the middle-mouse button.
 If geometry for a net segment is placed without first activating the net for tagging,
the geometry can still be tagged with the net name. Just make the desired net
the active net using the steps shown above, select the geometry you would like
to tag, and invoke the Command Menu icon on the SDL Navigator toolbar
followed by Tag Selections with active net.
 Check off the Gnd net segment checkbox in the SDL Navigator to indicate that
the entire net segment has been completed.
17.6. Setting up the automatic router

11. We will want to create a routing region to define the area in which the automatic
router will be constrained to.
 Select the Routing Region layer from the Layer Palette and the Switch to
drawing boxes icon on the L-Edit toolbar.
 Draw a box covering the entire layout. This will allow the router to place routes
outside of the minimum bounding box of the I/O ports.
96
Chapter 17 17.6 Setting up the automatic
Getting started with L-Edit Schematic Driven router
Layout (SDL)
Draw a
routing
region using
the Routing
Region
layer.
12. Prior to using the SDL automatic router, some routing information must first be
defined.
 Open the Setup Router dialog by selecting the Command Menu icon on the
SDL Navigator toolbar and invoking Setup Router….
 Verify the following settings in the Setup Router dialog:
97
Chapter 17 17.7 Automatic routing
Layout (SDL)
 For this example, we will be routing in Metal2 and Metal3 as can be seen via the
Setup Router dialog Route checkboxes. The first routing layer will generally be
used to route in the horizontal direction and the second will be used in the
vertical direction.
 The Poly and Metal1 layers are not used as routing layers but are specified in
order to define parameters for connecting routes to those layers. They are used
mainly to define which via or contact cell should be used for connection to ports
on that layer.
 The Width field defines the minimum width to be used for routes on that layer.
As mentioned earlier in the tutorial, the size of the port box will define actual
width of the route to be used. If connecting to a point port, the width in this dialog
is used. If connecting to a line port, the width of the line port is used unless the
line port is smaller than the width specified in this dialog. When connecting to
box ports, the smaller dimension of the box port is used unless that dimension is
smaller than the width specified in this dialog.
 The Spacing field defines the minimum spacing to be used between objects
placed on that layer. Routes will also be spaced away from any object on the
same layer that is present at the current level of hierarchy that is being routed.
 The Keepout layer defines the area in which each routing layer should not route.
Keepout – Metal2 and Keepout – Metal3 were defined in the lower level cells
and cover the active region of the transistors. This keeps the routes from
crossing over the transistors.
 Via cell defines via cell to use for the specified layer when transitioning to the
next layer. The last routing layer does not require a via cell to be defined as it
does not have a subsequent layer it needs to connect to.
 Same-net via pitch defines the center-to-center spacing to be used when
placing vias on wide metal traces or on the same net.
 Routing extent polygon on layer defines the layer that defines the area in
which the router is allowed to place routes. Here we selected the Routing
Region layer that we previously created.
 X Spacing, Y Spacing, X Offset, and Y Offset are all used to define a custom
grid for routing. In this case, all are set to a value of 0 allowing the router to
automatically calculate the grid to use.
 Select OK in the Setup Router dialog to accept any changes.
17.7. Automatic routing

13. Once the routing setup is entered, the SDL automatic router may be used to route a
single net or all nets that have not been completed.
 In cell RingVCO_Placed, select the Route All icon in the SDL Navigator to
automatically route the remaining nets. Nets that have been checked off in the
checklist will not be touched by the router.
98
Layout (SDL)
 A warning will appear stating the number of nets that were routed and indicating
that a net segment was unable to be routed.
 All geometry that was placed by the automatic router has been tagged with the
name of the its net.
 The SDL Navigator view will automatically change from viewing By Net to
viewing By Unrouted Segment.
 Switch to view By Net and notice that each net segment is marked with a visual
indication of whether the route completed or failed. To change the SDL
Navigator view, select the Netlist view icon and select to view By Net, By
Instance, or By Unrouted Segment. Completed nets are marked with and
uncompleted are marked with .
 Make sure the view is switched back to view By Unrouted Segment.
 Expand the symbol to the left of the Outp net segment in the SDL Navigator
to view the coordinates of the portion of the net that could not be routed.
Expand the
+ to view
coordinates.
99
Layout (SDL)
 Click in the layout to deselect all the routes that were added.
 Select the coordinates and press the Marker icon to view the connection that
could not be completed.
Select
coordinates
and press
Marker
 The marker may be different than the flyline if a portion of the net segment was
routed but not completed. Notice in this case that the marker indicates a missing
route between a port and a wire.
Marked
segment
that was
unable to be
routed
 Instead of routing all nets at once, a single net or selected nets may be routed by
selecting the net(s) in the SDL Navigator, right-clicking the net name and
invoking Route.
 Make sure to check off the nets that are completed so that subsequent automatic
routing does not affect those completed routes.
100
Chapter 17 17.8 Ripping up nets
Layout (SDL)
17.8. Ripping up nets

14. If you are not happy with the path of a route, you can ripup the nets you want to
reroute.
 Switch back to view By Net in the SDL Navigator.

 Right-click the VTune net segment in the SDL Navigator and invoke Ripup Net.
A message will appear indicating how many objects were deleted from the net
and the routing status indication for the net is removed. All geometry that was
tagged for that net has been removed.
 The net can now be re-routed manually or by using the automatic router.
17.9. Importing an Engineering Change Order (ECO)

15. Many times changes to the design or an ECO will be issued on a design after the
layout has been created. If the layout was created using SDL, an ECO netlist may
be loaded to view the differences between the new netlist and the previous netlist.
 Close cell RingVCO_Placed and reopen cell RingVCO. Select the Load Netlist
icon on the SDL Navigator toolbar to open the Import Netlist dialog.
Select to
open Import
Netlist
dialog
 Select Browse… to locate and load the netlist RingVCO_Testbench_ECO.sp

into the From File: field. The file is located in the following location:
My Documents\Tanner EDA\Tanner Tools v16.0\Designs\

RingVCO\RingVCO_TestBench_ECO.sp
101
Chapter 17 17.9 Importing an Engineering
Getting started with L-Edit Schematic Driven Change Order (ECO)
Layout (SDL)
Browse to
locate ECO
netlist.
Select
Compute
and display
differences
from the
current
netlist.
 The ECO processing section will now be enabled.

 Select Compute and display differences from current netlist.
 Select OK to bring in the ECO changes. Close the resulting log file.
 Expand the symbol to the left of the N_8 net segment in the SDL Navigator.
The icon indicates a difference between netlists for that net segment. A
indicates that a pin was added in the new netlist while a indicates that a pin
was removed.
 Notice that renamed nets are indicated with both the new net name and the old
net name. In this case, net segment N_10 was renamed to N_Rename.
102
Chapter 18 18.1 Creating a mosfet with T-
T-Cell Builder: Automatically Construct T-Cells Cell Builder
Chapter 18
T-Cell Builder: Automatically Construct T-Cells
18.1. Creating a mosfet with T-Cell Builder

Design Features By Tool\L-Edit\T-Cells\T-CellBuilder.tdb
Cell mosfet
The T-Cell Builder features, accessed from the Cell > T-Cell... menu, allow T-Cell code views to
be automatically generated from layout views. The resulting T-Cells are parameterized, and
contain geometry elements whose appearance can depend on these parameters. Because the
user does not need to write any UPI code directly, this feature is very useful for those users
who are unfamiliar with UPI programming.
The code view is constructed by executing the Cell>T-Cell>Construct T-Cell... command. This
command analyzes the geometry of the current cell, and creates a code view for that cell. An
existing code view will be (optionally) overwritten. Geometry in the layout view will be
generated by the code view. Optionally, geometry elements can be stretched, moved or
repeated according to the T-Cell's parameters, and they can be optionally included and/or have
their layers set (again, as a function of the T-Cell's parameters).
18.2. Stretching Elements And Defining Parameters

A common desired operation is that a dimension of some object(s) is set by a cell parameter.
For example, a simple MOSFET is parameterized by its channel length and width. To create this
T-Cell, we first create a template.
Note that stretch axes are defined by ports on a (user-selectable) layer. These ports define both
the name of the parameter that controls the stretch, the direction of the stretch, and the
default value of the stretch. The default value of the parameter is taken from the size of the
port, or by declaring it in the port string in the form “parameterName=defaultValue”.
These ports must be line ports (i.e. have exactly one dimension and be non-zero). By default, all
objects which are intersected by this port, extended to infinity in both directions, will be
stretched. Objects that are entirely on one side of the port may be moved, depending on the
direction of the stretch.
The direction of the stretch is controlled by the port text orientation; in general, geometry on
the same side of the port as the port text will move in the direction of the port text (if the port
text is center aligned, then geometry on both sides of the port will be modified).
103
Chapter 18 18.2 Stretching Elements And
T-Cell Builder: Automatically Construct T-Cells Defining Parameters
Invoke Cell > T-Cell > Construct T-Cell… to create a T-Cell from the above layout. L-Edit will
open the following dialog.
After you construct the T-Cell, you can instance it into layout by invoking Cell > Instance…
(shortcut I). In the following example, we will change the default width to a width of 20.
L-Edit generates the layout shown below.
104
Chapter 18 18.2 Stretching Elements And
T-Cell Builder: Automatically Construct T-Cells Defining Parameters
18.2.1. Repeating Elements Instead Of Stretching

Sometimes it is not appropriate to simply stretch elements, but instead it is necessary to repeat
them. This operation is accomplished by first selecting the objects in question, and then
executing Cell > T-Cell > Define Repeat Group...
The options to defining a repeat group are:
Horizontal/Vertical None: if selected, the object in question is neither
Repeat repeated, nor is it stretched. This choice is appropriate
for items such as contacts, which must remain a
specific size.
Count: the parameter is taken to be an integer, and
determines the number of times the object is
repeated
Fill: the object is iterated to fill the distance specified
by the named parameter
Stretch: this is the default, and confirms that this
object is free to stretch in the indicated direction, if it
is intersected by a stretch axis
Parameter Name The parameter that controls this repeat
Stepping Distance The pitch between adjacent repeated objects
Repeat Direction The original object is the "anchor" object; new objects
are created to the left, to the right, or equally to the
left and right.
Select the two contact boxes in cell mosfet, invoke Cell > T-Cell > Define Repeat Group…, and
apply the following setting to define their repeat parameters.
105
Chapter 18 18.3 Choose Layer
Invoke Cell > T-Cell > Construct T-Cell… to create the T-Cell, or to regenerate the T-Cell code if it
had been previously created. Now when you the mosfet T-Cell, with Width = 20, you will get the
layout shown below.
18.3. Choose Layer

The layer that an object is placed on can be made into a parameter of the T-Cell by selecting the
object and invoking Cell > T-Cell > Choose Layer…. If applied to an object, the layer of that
object becomes a parameter to the T-Cell.
Select the box on layer N Select and assign it a layer parameter called “Select Layer” and
regenerate the T-Cell to pick up this change.
106
Chapter 18 18.4 Define Conditional
T-Cell Builder: Automatically Construct T-Cells Inclusion
Now when we instance the mosfet, SelectLayer is a parameter to the T-Cell. We can change
from P Select to N Select.
18.4. Define Conditional Inclusion

An object can be included or excluded based on a Boolean or a logical condition. Select the box
on layer HV-Oxide and apply a condition parameter called HighVoltage, with a default value of
True, and regenerate the mosfet T-Cell.
107
Chapter 18 18.5 Select T-Cell Objects
Now when the T-Cell is instanced, HighVoltage is a parameter to the T-Cell. Selecting True will
include the object on that layer when the T-Cell is generated, selecting false will exclude it.
Conditional exclusion can also be based on a logical expression by entering an expression such
as width >10. Here width is a parameter that may be previously defined by ports on the layout.
In this case the default value is not relevant. If the condition is true then the object is included.
18.5. Select T-Cell Objects

This operation causes all objects which have been tagged for repeat, conditional inclusion or
layer parameterization to be selected. This operation is useful to find these objects, in order to
understand how the T-Cell will be created.
108
Chapter 18 18.6 Creating a resistor with T-
T-Cell Builder: Automatically Construct T-Cells Cell Builder
18.6. Creating a resistor with T-Cell Builder

Design tcellbuilder
Cell res
This example illustrates a resistor device generator. The boxes on Poly are part of a repeat
group, as shown in the figure below.
109
Chapter 19 19.1 Running HiPer PX
HiPer PX Quick Start Guide
Chapter 19
HiPer PX is driven from L-Edit, and requires a space tech setup. The tech setup typically
includes layer derivations, device recognition, connectivity descriptions, as well as
physical parameters such as resistivity, dielectric constants, layers thickness and edge
geometry, etc.
The creation of a tech setup is beyond the scope of this document, but the basic
required files are:
 space.def.s – human readable tech setup source file
 space.def.p – extract preferences
Other files may be required, depending on tech setup details.
19.1. Running HiPer PX

HiPer PX is found in the L-Edit menus under Tools->Parasitic Extractor.
19.2. Finding or Creating the Technology Files

The first dialog, “Define Technology…” is used to select which technology setup will be
used by this design.
110
Chapter 19 19.3 Exporting Layout Data
The process path is the name of the folder containing the space technology setup
(space.def.s, space.def.p, etc). This field can be an absolute path (ie
C:\path\to\tech\setup) or a relative path. If a relative path is specified, it will specify the
tech folder’s relationship to the folder containing the design file.
If the tech setup has already been compiled, click Apply to set this design’s tech folder
path. If you have modified the space.def.s file, or this is the first time you have used this
tech setup, you will need to compile it. Clicking on Create will generate the following
files in the process folder:
 space.def.t – the compiled form of space.def.s, used by PX to perform extraction
 maskdata – the list of design layers that will be exported to space. Layers
included in this file are drawn layers in L-Edit which have a GDS number defined
and are mentioned in the space.def.s file. For compatibility with space.def.s, all
characters in the layer’s name except letters and numbers will be replaced with
underscore (‘_’).
 default_lambda – the manufacturing grid for this process.
19.3. Exporting Layout Data

HiPer PX works with a separate database of the layout, optimized for parasitic extraction.
L-Edit automatically manages this database, and will update it before each extract run.
The “Export Database…” dialog controls the location of this database and L-Edit’s update
behavior.
111
Chapter 19 19.4 Extracting Layout
The path to the database can be absolute, or relative to the design file.
Choosing to export “All data” will cause the database folder to be completely deleted
and rebuild before each extract run. This is incompatible with incremental extract and
selective resistance extraction (described below). Exporting “Modified cells only” is
recommended. In this mode, L-Edit will check each cell in the PX database, and if it has
been changed in the L-Edit design file, it will be overwritten.
Pressing OK will create the database path if necessary and export the current cell and its
hierarchy to the PX database.
19.4. Extracting Layout

Once you have set a process folder and database path for the design, you will only need
to use the extract dialog for future extractions.
112
 Output file – the extracted spice netlist. If a file exists with this name, it will be
overwritten. The path can be absolute or relative to the design file.
 Hierarchy – Flat or Hierarchical – In Fast (2D) mode, the hierarchical extraction
mode is available. In this mode, the design will be extracted based on the layout
hierarchy. This mode requires careful design practices, since interactions
between hierarchy levels are limited to ports. If a short is created outside of a
port, it will extract as an open. Also, parasitic coupling capacitances between
layout features of different cells don’t fit in a hierarchical circuit description. It is
recommended to verify that a design passes LVS using an extract without
parasitics before relying on simulations from a hierarchical extract.
Within the hierarchical mode, the incremental mode will use existing extractions
of sub-cells rather than re-extracting them if the layout has not been modified.
This allows mixed mode extract, since a sub-cell can be extracted in Accurate
mode and combined with a higher level cell extracted in Fast mode.
113
 Capacitance extraction
o No extraction – no parasitic capacitors will be extracted
o Fast – uses a 2D interpolated model to extract parasitic capacitors
o Accurate – uses a 3D boundary element model to parasitic capacitance
o Types of parasitic capacitors extracted
 Capacitances to substrate – only parasitic (area and fringe)
capacitance to the substrate will be extracted.
 Cap(acitance)s to substrate & vertical coupling cap(acitance)s –
parasitic capacitance to the substrate will be extracted, as will
crosstalk capacitance between overlapping interconnect layers.
(Fast mode only)
 Cap(acitance)s to substrate, vertical & lateral coupling
cap(acitance)s – all parasitic capacitance will be extracted,
including capacitance to the substrate and crosstalk capacitance
between nearby interconnect nodes.
 Interconnect Resistance Extraction
o No extraction – no interconnect resistance will be extracted
o Fast – uses an efficient finite-element method to extract interconnect
resistances
o Accurate – uses a similar finite-element method, but applies a mesh
refinement which increases the accuracy and relevance of the extracted
interconnect resistors. See “Mesh Refinement Application Note”
(an0309.pdf) for details of the algorithm.
o Limiting resistance extraction by node - If desired, the user may specify
nodes for which interconnect resistance is, or is not performed. These
nodes are specified by coordinate and layer in a file named sel_con and
placed in the database folder (<database_path>\<tdb file
name>\sel_con). The format of the file ’sel_con’ is as follows. On each
line, an x position, an y position and a layername is specified. When an
interconnect has the specified layer on the specified layout position, that
interconnect is specified in the file. Coordinates are specified in ½
manufacturing grid units. (Ex. “ 200 150 cpg “ specifies st4 node in the
Oscilx.tdb file. Since the manufacturing grid is 0.05u, the coordinates in
micros is x=10u, y=7.5u)
Note that, this file should be added to the folder after exporting layout
data. Then you should change it “Modified cells only”, otherwise it will
be deleted.
 Circuit reduction – complex RC networks on large designs can be slow on some
simulators. HiPer PX provides an algorithm to reduce the complexity of the RC
networks without sacrificing accuracy. When extracting resistances together
with capacitances, the extractor will add lumped capacitances to the nodes of
the initial resistance network to model the distributed capacitive effects. In that
case, the node reduction will proceed such that the Elmore time constants
114
between the nodes in the final network are unchanged with respect to their
value in the fine RC mesh. This can be done in a frequency independent method,
or a more aggressive method which is accurate up to a user-specified frequency.
The higher the value of max frequency the more nodes will be retained in the
final network,
115

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Table of Contents

Chapter 12 Busses and Arrays ........................................................................................................ 60

Chapter 19 HiPer PX Quick Start Guide ........................................................................................ 110

 Schematic capture with S-Edit

 Analog simulation with T-Spice

 Waveform viewing with W-Edit

 Physical design with L-Edit

 Schematic driven layout with SDL

 Creating T-Cells from layout with T-Cell Builder

 Physical Verification with HiPer

 Parasitic Extraction with PX

1.1. Typographic Conventions

 Viewing designs and navigating design hierarchy

 Creating your own schematic and symbols

 Simulating Designs and probing results

2.1. Loading a design

Exercise 1 - Load an existing S-Edit Design

2.2. Viewing the Design

2.3. Navigating the Design Hierarchy

2.4. Elements of a Symbol View

 A symbol view contains the following elements:

 Symbol Graphics: Symbol graphics comprise the graphical image of the

 The toolbars used for creating the objects on a symbol are:

Lets examine symbol properties in more detail:

 Properties may also be moved to different locations. Right click on a

2.5. Elements of a Schematic View

 A schematic view contains the following elements:

 Instances of symbols: Instances of symbols refer to a particular symbol in a

Now let’s examine the contents of DiffCell:

Let’s examine some instance properties in more detail:

We saw in Elements of a Symbol View, properties can be an explicit value, or can be an

Properties button ( ). We can now see the evaluated

3.1. Annotate Port Properties

the Display Evaluated Properties button and dropdown on the Simulation

This dialog is coming from the callback function.

 Functions CheckSpecificDimension are user written functions listed

set dSnappedDimension [ gNearestMultiple $dDimension

property set $sPropertyName -value [dtos

set sMsg ""

There are four ways of saving a file:

6.1. Placing Instances

 Additional instances of PMOS can be placed by continuing to click the

Choose a new cell

6.2. Making Connections

 Now connect the two drains together.

6.3. Placing Input and Output Ports

 Multiple ports can be consecutively placed by selecting Enable Auto-

6.3.1. Moving Instances with Rubberbanding

Now let’s make a symbol for our inverter.

7.1. Automatic Symbol Generation and Update

7.2. Editing the Symbol

Now let’s highlight some nets.

10.1. Simulating a design

Exercise 2 - Setting up and simulating a design in S-Edit

In S-Edit, use the Simulate button, ( ), to run the simulation.

Exercise 3 - Viewing results in W-Edit

10.3. Probing Voltages, Currents, and Charges

 The current of the probed port will then display in W-Edit.

 Similarly, if the simulation is setup to do so, charges can be probed by

 Try navigating the hierarchy in context and probe different nodes.

Exercise 4 - Working with Traces in W-Edit

then clicking the collapse plot button ( ).

11.1. Viewing results on the schematic