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MBB ATN+CX IDEAL (Seamless

MPLS) Solution Clock


Synchronization Implementation and
Configuration

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Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.


Foreword
 Among various communication networks, mobile networks have the
highest requirements on clock frequency synchronization. As networks are
evolving from circuit switched synchronous digital hierarchy (SDH)
networks to packet switched IP networks, packet switched networks (PSNs)
are required to have the clock and time synchronization capabilities,
accommodating the development trend to IP interfaces on IP backhaul
networks and wide application of Ethernet access devices.

 PSNs were designed to transmit packet services, and therefore do not


have strict requirements on synchronization between network nodes. In
other words, PSNs are asynchronous transport networks. However, a
packet switched IP backhaul network requires both clock and time
synchronization capabilities.

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page2
Objectives
 After completing this course, you will be able to:

 Describe differences for two clock deployment solutions.

 Describe Synchronous Ethernet Clock Guideline.

 Describe 1588v2 Time Synchronization Guideline.

 Describe configuration Roadmap - IPRAN Area & IP Core.

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page3
Contents
1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page4
Contents
1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page5
Inter-AS Clock Solution Deployment
Solution 1: The clock is deployed in the Solution 2: The clock is deployed
same way as in a metropolitan area in centralized manner.
network.
GPS
GPS GPS GPS

BITS BITS BITS BITS

IPRAN 1588v2 IP Core


SyncE 1588v2
SyncE

Aggregation
Access ASG1 RSG2
MASG1
ABR1

CSG
SGW/MME

ASG2 RSG2
ABR2 MASG2

After comprehensive comparison of the two solutions, solution 1 is


recommended for inter-AS LTE bearer solutions.

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page6
Contents
1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page7
Synchronous Ethernet Clock

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page8
1588v2 Time Synchronization

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page9
Contents
1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page10
Configuration Roadmap - IPRAN
Area
Master BITS

Last Mile

CSG1 ASG3 ASBR1


E1
E0/3/1 G1/0/1 G1/0/0 G1/0/0
E0/3/0

BTS

G1/0/1
G1/0/2
E0/3/0

FE/GE E0/3/1 G1/0/1 G1/0/0 G1/0/0

NodeB CSG2 ASG4 ASBR2

Synchronous Ethernet

Backup BITS

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page11
Configuration Roadmap - IP Core
Master BITS

Clock pri 10
ASBR3 Clock pri 10 MASG1
GE1/0/1
GE1/0/0
GE2/0/1
Clock pri 20

Clock pri 10
GE2/0/1
GE1/0/0
GE1/0/1
ASBR4 Clock pri 10 MASG2
Clock pri 20

Clock Tracking Path BackupBITS


Clock pri n Priority of a reference clock source at a port

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page12
Contents
1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page13
Parameters Planning - Synchronous
Ethernet Clock
Device Port Priority
ASBR1 CLK0 5

G1/0/0 10

ASG3 G1/0/0 5

G1/0/1 10

CSG1 E0/3/1 5

E0/3/0 10

CSG2 E0/3/0 5

E0/3/1 10

ASG4 G1/0/1 5

G1/0/0 10

ASBR2 G1/0/0 5

CLK0 10

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page14
Parameters Planning - 1588v2 Time
Synchronization
Configuratio Parameter Value Remark
n Item s
All devices that synchronize time with one another using
IEEE 1588v2 packets must belong to the same IEEE
Clock domain 9
1588v2 clock domain.The value range is 0–255. The
default value is 0.
Basic The clock type is set to BC on all of the CSGs, AGGs, and
Clock type BC
parameters RSGs.
Delay
measuremen Pdelay -
t mechanism
Pdelay One-step
The smaller value, the higher priority. Both ASBR1 and
ASBR2 are connected to an external clock source. The
priority of clocks on ASBR1 and ASBR2 must be the
ASBR1: highest on the network, so that NEs can trace the external
Local 6 clock source of ASBR2 when the external clock source of
Clock priority
reference ASBR2: ASBR1 fails.
7 An IEEE 1588v2 device will select the following clocks in a
descending order of priority during dynamic source
selection based on the BMC algorithm: priority 1 > clock-
class > clock-accuracy > priority 2.
Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page15
Summary
1. Differences for two clock deployment solutions.

2. Synchronous Ethernet Clock Guideline.

3. 1588v2 Time Synchronization Guideline.

4. Configuration Roadmap - IPRAN Area & IP Core.

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page16
Thank you
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