Académique Documents
Professionnel Documents
Culture Documents
Junctionless MOSFET
Abstract — Junctionless MOSFETs (JLT) have a number of dielectric-semiconductor interface, where the surface traps of
advantages over traditional ones in terms of simplicity of design, charge carriers are located.
manufacturing technology and reducing the impact of short-
channel effects on the device characteristics. However, the known Despite of all the JLT advantages over the inversion MOS
experimental nanowire Junctionless MOSFETs have high transistor, such a device has one significant drawback. At the
subthreshold currents due to the parasitic bipolar transistor moment there are only publications that describe MOS JLTs
appearance in the closed state. In order to solve this problem, a based on silicon nanowires with channel sizes of only
design with a low impurity concentration in the working body 20x10 nm. It follows that at a low concentration of the dopant
and strongly doped contacts to the drain-source areas was in the body of the device, the number of main charge carriers
proposed. In the developed planar JLT model, the subthreshold is very small and insufficient for the operation of the transistor.
current is 4 orders of magnitude smaller – 1013 cm-3, the With such channel size at an impurity concentration of 10 15 cm-
saturation current is approximately the same as in the inversion 3
, the number of impurity atoms is 0.002, at 10 16 – 0.02, at
and nanowire MOSFETs – 6*10-5 cm-3, and the ratio is 1017– 0.2, at 1018– 2, at 1019 – 20. Thus, in order to there was
significantly larger – 108 cm-3. some conductivity, it is necessary to increase the impurity
concentration to 1019 [1].
Keywords — junctionless MOSFET; subthreshold current;
saturation current; drain/source regions; threshold voltage Also, a high concentration of dopant leads to an increase in
leakage currents in the off state of the JLT because of the
I. INTRODUCTION interband tunneling of carriers from the valence band of the
Recently, a new semiconductor device – a JLT MOSFET – channel to the conduction band of the drain in the channel-
has gained a lot of popularity. Such transistor is created on the drain transition region as a result of the occurrence of a high
basis of silicon-on-isolation (SOI), a structure in which the electric field strength.
channel, drain and source regions are in a silicon film doped
with one type of impurity. In essence, such a device is a field- III. KNOWN SOLUTIONS OF THE PROBLEM
controlled resistor. The current-voltage characteristics of such In the last five years, the developers of the JLT MOSFET
transistor (output and transfer) are similar to those of a have been trying to find a solution to the problem of large
traditional MOS transistor with an inversion channel. leakage currents in the JLT in the off state [2-5]. To date, there
are four ways to reduce the subthreshold currents in a
The JLT MOSFET has many advantages over a junctionless transistor based on a local decrease in the
conventional MOSFET. First of all, this is the fact that the magnitude of the electric field in the channel-drain transition
design of such a device is much simpler and therefore the region.
process of its formation is simpler. In the working region of
the transistor there are no p-n junctions, and consequently, The first method [2] proposed in 2012 is to increase the
there are no space charge regions (SCRs) associated with them. thickness of the gate oxide on the channel boundary and
As a result, there are no short-channel effects, for the drain/source areas. Due to this design, the transverse electric
suppression of which it is necessary to complicate the field in the channel-drain transition region decreases, the
structure of the transistor by introducing additional regions interband tunneling effect is suppressed and the subthreshold
such as LDD, Halo and Pocket. currents decrease.
II. THE MAIN PROBLEM OF JLT The second method [3], developed a year later (2013), uses
a local variation of the gate electrode material in the channel-
Unlike traditional MOSFETs that can work either in drain transition region, leading to a change in the gate-to-
depletion mode or in accumulation mode, a junctionless channel potential difference, which reduces the magnitude of
transistor operates in an incomplete depletion mode, which the electric field, and therefore suppresses the interband
ensures a high mobility of carriers in the channel of the device, tunneling.
since it is located in the volume and is isolated SCR from the
1381
concentration in the film of 6*1016 cm-3, the threshold voltage VI. CONCLUSIONS
is 0.48 V, which is within the specified range. In the course of the work, a structural model of a planar
As a result of the research, the optimum values of the size SOI JLT MOSFET was developed in accordance with the
of the drain/source regions were found to be 250 nm, the film technology standards of 90 nm, a route of mathematical
concentration was 6*1016 cm-3, and the film thickness was 70 modeling was created, and the impurity concentration effect in
nm. Let us compare the obtained structure with an the silicon oxide film of SOI JLT MOSFETs on the threshold
conventional MOS transistor and a nanowire JLT. The transfer voltage, saturation currents and subthreshold currents was
characteristics of these transistors are shown in Fig. 4. analysed using the TCAD.
The most optimal size of the spacer thickness is 250 nm, in
which the influence of n + n junctions and the consecutive
resistance of the drain/source region is minimized on the
parameters of the SOI JLT MOSFET.
It is shown that at impurity concentrations in the working
body of the device below 1017 cm-3, there is no interband
tunneling effect, subthreshold currents are reduced to 10 -13
A/µm, while maintaining saturation currents at an acceptable
level, which is significantly lower than for traditional MOS
transistors.
REFERENCES
[1] C. Lee, A. Afzalian, J. Colinge «Junctionless multigate field-effect
transistor» Appl. Phys. Lett., vol. 94, no. 5, pp. 346–358, 2009.
[2] JP. Colinge et al., «Nanowire transistors without junctions», Nature
Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
Fig. 4 Transfer CVCs of the developed SOI MOS JLT, Nanowire MOSFET [3] S. Gundapaneni, M. Bajaj, A. Kottantharayil, K. Murali «Effect of
and conventional MOS transistor band-to-band tunneling on junctionless transistors», IEEE Trans.
Electron Devices, vol. 60, no. 4, pp. 1021–1030, Apr. 2012.
In the developed planar JLT model, the subthreshold [4] B. Ghosh, P. Bal, P. Mondal «A junctionless tunnel field effect
transistor with low subthreshold slope», Springer Science, pp. 487–499,
current is 4 orders of magnitude smaller – 1013 cm-3, the 2013.
saturation current is approximately the same as in the [5] S. Migita, Y. Morita, T. Matsukawa, M. Masahara «Experimental
inversion and nanowire MOSFETs – 6*10-5 cm-3, and the ratio demonstration of ultrashort-channel junctionless FETs utilizing
is significantly larger – 108 cm-3. atomically sharp V-grooves on SOI», IEEE Trans. Nanotechnol., vol.
13, no. 2, pp. 208–215, Mar. 2014.
[6] M. Jagadesh Kumar, S. Sahay, “Controlling BTBT induced parasitic
BJT action in junctionless FETs using a hybrid channel,” IEEE
Transactions on Electron Devices, vol. 63, no. 8, pp. 3350–3353, Aug.
2016
1382