Subthreshold Current Decrease in the SOI

Junctionless MOSFET

Michael A. Korolyov, N. Shelepin, A. Klyuchnikov, Daria Efimova

Integral Electronics and Microsystems
National Research University of Electronic Technology (MIET)
Russia, Moscow, Zelenograd
ef_dasha@mail.ru

Abstract — Junctionless MOSFETs (JLT) have a number of
advantages over traditional ones in terms of simplicity of design,
manufacturing technology and reducing the impact of short-
channel effects on the device characteristics. However, the known
experimental nanowire Junctionless MOSFETs have high
subthreshold currents due to the parasitic bipolar transistor
appearance in the closed state. In order to solve this problem, a
design with a low impurity concentration in the working body
and strongly doped contacts to the drain-source areas was
proposed. In the developed planar JLT model, the subthreshold
current is 4 orders of magnitude smaller – 1013 cm-3, the
saturation current is approximately the same as in the inversion
and nanowire MOSFETs – 6*10-5 cm-3, and the ratio is
significantly larger – 108 cm-3.
Keywords — junctionless MOSFET; subthreshold current;
saturation current; drain/source regions; threshold voltage
I. INTRODUCTION
Recently, a new semiconductor device – a JLT MOSFET –
has gained a lot of popularity. Such transistor is created on the
basis of silicon-on-isolation (SOI), a structure in which the
channel, drain and source regions are in a silicon film doped
with one type of impurity. In essence, such a device is a field-
controlled resistor. The current-voltage characteristics of such
transistor (output and transfer) are similar to those of a
traditional MOS transistor with an inversion channel.
The JLT MOSFET has many advantages over a
conventional MOSFET. First of all, this is the fact that the
design of such a device is much simpler and therefore the
process of its formation is simpler. In the working region of
the transistor there are no p-n junctions, and consequently,
there are no space charge regions (SCRs) associated with them.
As a result, there are no short-channel effects, for the
suppression of which it is necessary to complicate the
structure of the transistor by introducing additional regions
such as LDD, Halo and Pocket.
II. THE MAIN PROBLEM OF JLT
Unlike traditional MOSFETs that can work either in
depletion mode or in accumulation mode, a junctionless
transistor operates in an incomplete depletion mode, which
ensures a high mobility of carriers in the channel of the device,
since it is located in the volume and is isolated SCR from the
dielectric-semiconductor interface, where the surface traps of
charge carriers are located.
Despite of all the JLT advantages over the inversion MOS
transistor, such a device has one significant drawback. At the
moment there are only publications that describe MOS JLTs
based on silicon nanowires with channel sizes of only
20x10 nm. It follows that at a low concentration of the dopant
in the body of the device, the number of main charge carriers
is very small and insufficient for the operation of the transistor.
With such channel size at an impurity concentration of 10 15 cm-
3
, the number of impurity atoms is 0.002, at 10 16 – 0.02, at
1017– 0.2, at 1018– 2, at 1019 – 20. Thus, in order to there was
some conductivity, it is necessary to increase the impurity
concentration to 1019 [1].
Also, a high concentration of dopant leads to an increase in
leakage currents in the off state of the JLT because of the
interband tunneling of carriers from the valence band of the
channel to the conduction band of the drain in the channel-
drain transition region as a result of the occurrence of a high
electric field strength.
III. KNOWN SOLUTIONS OF THE PROBLEM
In the last five years, the developers of the JLT MOSFET
have been trying to find a solution to the problem of large
leakage currents in the JLT in the off state [2-5]. To date, there
are four ways to reduce the subthreshold currents in a
junctionless transistor based on a local decrease in the
magnitude of the electric field in the channel-drain transition
region.
The first method [2] proposed in 2012 is to increase the
thickness of the gate oxide on the channel boundary and
drain/source areas. Due to this design, the transverse electric
field in the channel-drain transition region decreases, the
interband tunneling effect is suppressed and the subthreshold
currents decrease.
The second method [3], developed a year later (2013), uses
a local variation of the gate electrode material in the channel-
drain transition region, leading to a change in the gate-to-
channel potential difference, which reduces the magnitude of
the electric field, and therefore suppresses the interband
tunneling.

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 The third method uses a shell alloying profile [4]. The
working region of the transistor is a nanowire of circular cross
section. The central part is doped with a small dose of the
impurity, and the surface (shell) is large (hence the name).
With this method, in the volume of nanowires with a low
impurity concentration at the channel-drain transition, the
magnitude of the electric field is small and therefore there is
no interband tunneling effect, and the heavily doped shell
provides the necessary conductivity of the channel.
The fourth method [5], proposed in early 2016, is the
development of the third - the central part is doped with an
impurity of the opposite shell type, which reduces the electric
field in the channel-drain region. As a result, interband
tunneling becomes impossible.
The presented methods greatly complicate the already
complex technology of forming a JLT based on nanowires.
IV. THE ESSENCE OF THE RESEARCH
In order to solve the problem of reducing the subthreshold
current of the JLT MOSFET, an device and technology
simulation was carried out using the TCAD program [6]. As a
research object, the planar structure of the SOI MOS JLT with
a design-technological parameters corresponding to the
conventional MOSFET manufactured at the technological
standards of 90 nm was chosen.
A schematic representation of the structure is shown in
Fig. 1.
electrode in the self-aligned technological process, must be
selected during the investigation.
V. RESEARCH RESULTS
Taking into account all the specified parameters, several
structural models are created and the characteristics of the
transistor are calculated for different spacer thicknesses. The
obtained transfer current-voltage characteristics (CVC) are
shown in Fig. 2.
Fig. 2 Transfer CVC of JLT with different spacer thicknesses. Vd=1,2 B
According to the transfer characteristic, it is seen that at
small thicknesses the subthreshold currents are very high. This
is due to the fact that when the drain/source contacts are
closely located with the gate, the characteristics of the
transistor are influenced by the n + n transition and the
threshold voltage is increasing. However, when the
drain/source area is above 250 nm, the subthreshold current
again increases. Hence, for the best characteristics of the
transistor, it is necessary to take the spacer thickness of 250
nm.
Given the clarified thickness of the spacer, several
structural models are created and the characteristics of the
transistor are calculated at different concentrations in the film.
The obtained transfer CVCs are shown in Fig. 3.

Fig. 1 Schematic representation of a planar SOI MOS JLT, with constructive-

technological parameters using 90 nm technology

The transistor uses a silicon substrate doped with a donor

impurity with a constant concentration of Nsub = 10 15 cm-3.
The upper surface of silicon is covered with an insulating
layer of SiO2, with a thickness of Wbox = 150 nm. Above
there is a working layer of n-Si 0.89 µm in length. At the
edges of the n-Si, ohmic contacts of n+Si are formed, with a
concentration of the donor impurity with N = 10 20 cm-3. On the
surface of the working n-Si layer, a gate dielectric SiO2 with a
thickness Wox = 21 Å is grown and a polysilicon gate
electrode with thickness Wg = 150 nm is formed.
The concentration of the dopant and the thickness of the
working layer, as well as the thickness of the spacers that
determine the distance between the contact areas and the gate
Fig. 3 Transfer CVC of the JLT with different impurity concentrations in the
film. Vd=1,2 B
We note that when the concentration in the film decreases
to less than 1017 cm-3, the interband tunneling effect ceases to
arise. Hence, it is necessary to set the concentration in the film
below this value.
However, for correct operation, the threshold voltage must
be in the range from 0.4 V to 0.5 V. At an impurity

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concentration in the film of 6*1016 cm-3, the threshold voltage
is 0.48 V, which is within the specified range.
As a result of the research, the optimum values of the size
of the drain/source regions were found to be 250 nm, the film
concentration was 6*1016 cm-3, and the film thickness was 70
nm. Let us compare the obtained structure with an
conventional MOS transistor and a nanowire JLT. The transfer
characteristics of these transistors are shown in Fig. 4.
Fig. 4 Transfer CVCs of the developed SOI MOS JLT, Nanowire MOSFET
and conventional MOS transistor
In the developed planar JLT model, the subthreshold
current is 4 orders of magnitude smaller – 1013 cm-3, the
saturation current is approximately the same as in the
inversion and nanowire MOSFETs – 6*10-5 cm-3, and the ratio
is significantly larger – 108 cm-3.
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VI. CONCLUSIONS
In the course of the work, a structural model of a planar
SOI JLT MOSFET was developed in accordance with the
technology standards of 90 nm, a route of mathematical
modeling was created, and the impurity concentration effect in
the silicon oxide film of SOI JLT MOSFETs on the threshold
voltage, saturation currents and subthreshold currents was
analysed using the TCAD.
The most optimal size of the spacer thickness is 250 nm, in
which the influence of n + n junctions and the consecutive
resistance of the drain/source region is minimized on the
parameters of the SOI JLT MOSFET.
It is shown that at impurity concentrations in the working
body of the device below 1017 cm-3, there is no interband
tunneling effect, subthreshold currents are reduced to 10 -13
A/µm, while maintaining saturation currents at an acceptable
level, which is significantly lower than for traditional MOS
transistors.
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