International Journal of Application or Innovation in Engineering & Management (IJAIEM)

Web Site: www.ijaiem.org Email: editor@ijaiem.org

Volume 8, Issue 1, January 2019 ISSN 2319 - 4847

Low Power Consumption and Reduced Delay

Borrow Save Adder Using Dynamic Design
Logic
K.Dinesh kumar1, Ramya jothikumar2
Department of Electronics and communication Engineering
Sri ManakulaVinayagar Engineering College, Pondicherry, India

ABSTRACT
An increase in delay fluctuation and reduction in operating frequency occurs due to low power consumption in Borrow Save
Adder (BSA). Therefore, such circuits are not upto expected benefits. A new modulo ex-or adder based on carry correction
technique and parallel prefix algorithm is proposed. The n-modulo adder can be divided into four units such as the pre-
processing unit, the prefix computation unit, the carry correction unit, and the sum computation unit. In carry correction
technique, the output carry from adder computed by prefix computation unit and the final carries is obtained by altering the
information carries twice. Also prefix computations is done parallel and carry correction technique is carried out. The
proposed modulo adder has better area delay performance and achieves faster operating frequency and it is implemented using
Xilinx ISE 9.1/14.2.
Keywords-Borrow Save Adder (BSA), Carry correction technique, Parallel prefix algorithm.

1.INTRODUCTION
The Arithmetic Logic Units (ALU) in digital computers performs various arithmetic operations. Basic arithmetic
operation is addition and subtraction of two binary digits. In processors adders are used to calculate addresses, table
indices and other similar operations. Binary Coded Decimal (BCD) and excess-3 are the most common adders used in
arithmetic operations. Ripple carry adder is a type of adder that create a logical circuit using multiple full adders to add
n-bit numbers. Each full adder has an input Cin, which is the Cout of previous adder. Therefore, it performs a simple
adder circuit where the carry bit ripples to the next full adder. Under nominal process and environmental conditions, its
maximum critical path delay is defined by the path along its carry chain until the sum output of the Most Significant
Bit position. Borrow save adder is other type of adder where the propagation of carry is skipped using skip logic.

2.LITRATURE SURVEY
The carry bit is added at the end in borrow save adder to increase the speed of addition operation. With the challenge of
increased threshold voltage variation, low power addition is done. Borrow save adder achieves lower standard deviation
with maximum delay than ripple carry adder (1). A novel 1-bit full adder is designed using carbon nanotube field
effect transistor with input XOR/XNOR circuit. The circuit has its own merits with power, speed and noise (2). The
variation of delay of gate within die variation (3). The analysis of delay variation depends on fluctuation of supply
voltage will have a limitation of speed in circuits (4). Depends on the structure, variations, values the analysis is done
(5). The total delay, power variations and other parameters are analysed depends on the model and die variations (6-
15).

3.Proposed System Methodology

3.1. Parallel Prefix Algorithm
A modulo adder is proposed with parallel prefix algorithm. The prefix sum of parallel algorithm can be concluded for
characterized binary operations. Parallel implementations follow a two pass steps where partial prefix sums are
calculated in the first pass on each processing unit; the prefix sum of these partial sums is then calculated and given
back to the processing units for a second pass using the calculated prefix as the initial value. An algorithm which can
be performed a piece at a time on many different processing devices, and then combined together again at the end to

Volume 8, Issue 1, January 2019 Page 8

International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 8, Issue 1, January 2019 ISSN 2319 - 4847

get the correct result. The multiple processors are performed to use same memory at the same time. The processes are
sorted in order in memory cell and accessed depends on the requested cells and the results are distributed from memory
read operations.
For the sequence of binary values, the number n can be converted into gray code in n position. The decoding of gray
code is more complicated, therefore bitwise Boolean expression is used. An early application of parallel prefix sum
algorithms was in the design of binary adders, Boolean circuits that can add two n-bit binary numbers. Thus parallel
prefix algorithm is implemented in borrow save adder to reduce power consumption and delay.

3.2. Carry Correction Technique

A circuit having a carry correcting technique which set all bits of a circuit subjected to sign extension to a certain
specific value.Both the least significant invalid bit and the most significant effective bit of the circuit are given
according to a value of a sign extension control signal. A sign bit is the bit of effective data to be multiplied, is carried,
a specific value signal is input to a bit input portion of a Booth decoder, receiving both the least significant invalid bit
and the most significant effective bit of the multiplier, according to a value of a sign extension control signal. The input
of intermediate circuit is set to value of predetermined bit of multiplier according to multiple generating circuits.

4.Architecture of the Proposed System

A sign extension function or the number of adding circuits to be added in the case of producing a remainder in the
number of partial products, at the time of dividing the multiplication into a plurality of operation cycles, are reduced to
suppress a circuit scale from becoming larger.

Fig.1 The block diagram of the proposed system

5.Performancesand Analysis
This section gives an impact of delay variation and power reduction on Borrow save adder. The latency and power
consumption of the circuit is reduced in the adder using dynamic design logic circuit when compared to the existing

Volume 8, Issue 1, January 2019 Page 9

International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 8, Issue 1, January 2019 ISSN 2319 - 4847

system. When carry is not propagated in the proposed system, the switching technique will reduce the amount of power
consumed by the circuit and delay is also reduced by implementing modulo adder. The comparison for parameters like
power, delay are listed in the Table 1.These parameters analysis are obtained by implementing the architecture in the
Xilinx vivado software. From the below tabulation it shows that proposed low power consumption and reduced delay
borrow save adder using dynamic design logic circuit is more efficient in power when compared to the existing system.

Fig.2Simulation result of Borrow save adder with reduced delay and low power reduction.
5.1. Table
Table.1. Design summary
Existing system Proposed system
(carrypropagated) (without carry propagated)

DELAY 12.97ns 8.920ns

POWER 0.034W 0.014W

The design summary of a system with carry propagation and without carry propagation is compared in Table.1.

6. Conclusion
Low power consumption and reduced delay borrow save adder using dynamic design logic circuit is proposed to
achieve better area delay performance with faster operating frequency. The design of this architecture was implemented
successfully on the Xilinx virtex-5 FPGA. The sample design has been synthesized using Xilinx synthesizer and
functionality of the design has been verified extensively by using ModelSim verification tool over a large set of test
cases. This architecture works better than the existing system in terms of speed, power consumption and delay. Parallel
prefix algorithm and Carry correction technique algorithm are the proposed algorithm used in this architecture.

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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 8, Issue 1, January 2019 ISSN 2319 - 4847

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