IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO.

3, MARCH 2015 1403

Techniques of Dual-Path Error Amplifier

and Capacitor Multiplier for On-Chip
Compensation and Soft-Start Function
Pang-Jung Liu, Member, IEEE, Chih-Yao Hsu, and Yi-Hsiang Chang

Abstract—Techniques of a dual-path error amplifier and two

capacitor multipliers for providing on-chip frequency compensa-
tion and soft-start function are proposed in this paper. The concept
of the dual-path error amplifier is to use two currents to charge
and discharge a compensation capacitor simultaneously. As a re-
sult, the equivalent capacitance is enlarged significantly with little
additional power and silicon area. The dc–dc converter with the
dual-path architecture also has great performance in transient re-
sponse because the compensation capacitor is reduced significantly.
For the soft-start function, the subtractive-type and time-average
capacitor multipliers are used to relax the restriction of the capac-
itance and the charging current. Consequently, it is easy to inte-
grate the soft-start capacitance into a chip and the output overshoot
voltage can be suppressed. A prototype converter fabricated with
TSMC 0.35-μm 2P4M CMOS process verifies the effectiveness of
the techniques of a dual-path error amplifier and two capacitor
multipliers. Experimental results demonstrate the converter sta-
bility, transient response, and soft-start function. The transient
recovery time and transient ripple are less than 20 μs and 25 mV, Fig. 1. Capacitor multiplier techniques in (a) voltage mode and (b) current
respectively, for the load current swing from 50 to 500 mA. More- mode.
over, the soft-start time is up to 8 ms. With the proposed techniques,
the external pins of the dc–dc converters are minimized and their
high integration is imperative for achieving small area and high
performance is improved significantly.
performance in portable electronic devices [2], [3].
Index Terms—Capacitor multiplier, dc–dc converter, frequency Switched-mode power supplies provide efficient power con-
compensation, soft-start function, transient response.
version and reliable output voltages under changing supply volt-
age and load current, so those power supplies are widely used
in portable electronic devices. For dc–dc converters, it is urgent
I. INTRODUCTION
to integrate off-chip components into a chip for minimizing ex-
ORTABLE electronic devices such as smart phones, tablet
P personal computer, digital cameras, and other multimedia
entertainment devices have a high demand for low cost and
ternal pins and PCB area. Due to stability consideration, the
controller of the dc–dc converters always needs to perform fre-
quency compensation. However, the compensation capacitor is
low power. To facilitate portability, the efforts for making the usually large and hard to integrate into a chip; therefore, the
electronic gadgets smaller and lighter are never enough. Unfor- capacitor should be dealt with off-chip.
tunately, off-chip components add production cost and occupy Several research works have proposed capacitor multiplier
areas of significant sizes on the printed circuit board (PCB) [1]. circuits [4]–[10]. Generally speaking, there are two types of
Moreover, the parasitic elements of pads, bonding wires, and capacitor multiplier techniques, which are used to obtain a large
package degrade the performance of electronic devices. Hence, equivalent capacitance. One type is voltage mode and the other is
current mode. The voltage-mode capacitor multiplier is shown
in Fig. 1(a). According to the Miller theorem, the equivalent
capacitance at node n1 to ground can be expressed as
Manuscript received December 21, 2013; revised March 27, 2014; accepted
April 15, 2014. Date of publication April 25, 2014; date of current version
October 15, 2014. This work was supported in part by National Science Coun- Ceq,VM = (1 + Av ) Cc (1)
cil, Taiwan, under Grants NSC 101-2221-E-027-145 and 102-2221-E-027-030.
Recommended for publication by Associate Editor J. A. Cobos.
P.-J. Liu is with the Department of Electrical Engineering, National Taipei where Av is the absolute voltage gain of V2 to V1 . The current-
University of Technology, Taipei 10608, Taiwan (e-mail: pjliu@ntut.edu.tw).
C.-Y. Hsu and Y.-H. Chang are with the Department of Electronics Engi- mode capacitor multiplier is shown in Fig. 1(b). The concept
neering, National Taiwan University of Science and Technology, Taipei 10617, of the current-mode technique is to sense the current flowing
Taiwan (e-mail: m9902255@mail.ntust.edu.tw; b9602112@mail.ntust.edu.tw). through the capacitor Cc , amplify the sensed current by a factor
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. of Kx , and bypass the amplified current across the capacitor
Digital Object Identifier 10.1109/TPEL.2014.2320282 Cc . Hence, the equivalent capacitance at node n1 to ground is

0885-8993 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
1404
derived as
Ieq (1 + Kx )Ic
V1 = =
sCeq,CM sCeq,CM
(1 + Kx )Ic
⇒ Ceq,CM = = (1 + Kx ) Cc . (2)
sV1
From (1), we know that using a voltage amplifier with high
gain can achieve high multiplication factor. However, its fre-
quency operation is limited because the high voltage gain im-
plicated a relatively low-frequency pole [5]. Moreover, high
multiplication factor may be compressed because any node volt-
age of the voltage amplifier is limited by power rails when large
swings occur in its input. In such a case, the effective Miller
capacitance is reduced. The current-mode capacitor multiplier
could be realized by a current mirror that provides better fre-
quency performance due to its simplicity. Based on (2), the mul-
tiplication factor of the current-mode method is proportional
to the amplified current Kx Ic shown in Fig. 1(b). Therefore,
for the same multiplication factor, the current-mode capacitor
multiplier leads to higher power dissipation compared to the
voltage-mode method [4]–[7].
During the start-up period, the output voltage of dc–dc con-
verters starts from zero value. Since there exists a large dif-
ference between the output feedback voltage and the reference
voltage of the error amplifier, the duty cycle of the PWM driv-
ing signal tends to be maximized. Therefore, it is easy for the
dc–dc converters to induce inrush current and output voltage
overshoot, which damage circuit components, affect following
circuit operation, and even shorten battery lifetime [11]. In order
to prevent this issue, one of the common methods is applying
a soft-start circuit. The conventional soft-start method requires
an additional pin and discrete capacitor, but it will obstruct high
integration and increase board area [12], [13].
Soft-start circuits are used to control the ramp up speed of
the output voltage of the dc–dc converter from zero to the target
value [12]–[18]. By controlling the rising time of the reference
voltage of the error amplifier, the soft-start time could be de-
termined easily. The reference voltage is usually accomplished
with a current source charging a capacitor [14], and the soft-start
time can be calculated as
tss = (Vref Css )/Iss (3)
where Vref is the reference voltage of the error amplifier, Css is
the soft-start capacitor, and Iss is the charging current. The soft-
start time is proportional to the soft-start capacitor and inversely
proportional to the charging current. For example, if Vref equals
1 V and a soft-start time of 1 ms with a charging current of 1 μA
is required, a soft-start capacitor of 1 nF is needed. To avoid
using such a large capacitor, a small charging current should be
used; therefore, the on-chip soft-start capacitor can be realized.
A nanoampere current can be used to shrink the capacitor, but
the tiny current is difficult to precisely control and is easily
affected by the fabrication process [15]. For a clock-based soft-
start circuit, the small average current is achieved by increasing
the bit-length of the counter to shorten the charging time, but
this method increases silicon area [18].
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 3, MARCH 2015
Fig. 2. Block diagram of the proposed buck converter.
Techniques of a dual-path error amplifier (DPEA) and two
capacitor multipliers containing the function of on-chip fre-
quency compensation and soft-start function are presented in
this paper. The concept, circuit analysis, and implementation
are described in Section II. The DPEA uses two current sources
to effectively amplify a compensation capacitor with little power
consumption and small silicon area. Moreover, due to the small
compensation capacitor, the transient response of the dc–dc con-
verter with the dual-path architecture is also improved signif-
icantly. Subtractive-type and time-average capacitor multiplier
techniques are used to create an accurate tiny charging cur-
rent and shorten the charging period. Hence, the proposed soft-
start strategy with the two capacitor multipliers significantly re-
laxes the restriction of the capacitance and the charging current.
The laboratory prototype of a buck converter was fabricated by
TSMC 0.35-μm process and experimental results are shown in
Section III. Finally, conclusions are summarized in Section IV.
II. DESIGN OF THE PROPOSED BUCK CONVERTER
Techniques of the DPEA and subtractive-type and time-
average capacitor multipliers are concurrently adopted in de-
signing a synchronous CMOS buck converter. The block
diagram of the buck converter is shown in Fig. 2. The DPEA
has two inputs: one of which is the output feedback voltage Vfb
and the other is the output of the proposed soft-start circuit. The
outputs of the error amplifier are connected to the frequency
compensation components Rc and Cc . The reference voltage
Vref passes through the soft-start circuit, and then, the slow ris-
ing signal Vref ss is generated to control the rising time of the
output voltage Vout during start-up period. Thanks to the DPEA
and the two capacitor multipliers, the frequency compensation
and soft-start capacitance can be implemented into a chip, so
the external pins can be minimized. Thus, a low-cost dc–dc con-
verter with small PCB size is achieved. The concept and detailed
circuit-level implementation of the DPEA and subtractive-type
and time-average capacitor multipliers are described in the fol-
lowing sections.
LIU et al.: TECHNIQUES OF DUAL-PATH ERROR AMPLIFIER AND CAPACITOR MULTIPLIER FOR ON-CHIP COMPENSATION 1405

Fig. 3. Conventional compensated error amplifier.

Fig. 4. (a) Concept and (b) equivalent impedance of the DPEA.

A. Analysis of the DPEA for Frequency Compensation

Since dc–dc converters are necessary for providing an ac-
curate output voltage in various operation conditions, negative
feedback control is always required. To prevent dc–dc converters
with negative feedback control from being unstable, frequency
compensation should be done well [19]. Lag compensation is
widely used in many types of feedback system, and an example
of a lag compensation circuit is shown in Fig. 3 [20]–[22]. For
this implementation, the equation of the zero is expressed as
1
z1 = . (4)
Rc Cc
Fig. 5. (a) Simple circuit diagram of the soft-start function and (b) waveforms.
To stabilize the dc–dc converter, the compensation capacitor
Cc should be large to create the low-frequency zero z1 . More-
over, since the large compensation capacitor Cc is connected to To compare (4) and (7), the zero is multiplied by (1 − α).
the output of the operation transconductance amplifier (OTA), In other words, the value of the capacitor Cc is multiplied by
the OTA slewing rate is degraded, and then, the response time (1 − α)−1 . For example, if α is 0.95, then Cc is multiplied by
of the dc–dc converter is also seriously limited. 20, leading to substantial saving on area.
The concept of the DPEA is shown in Fig. 4(a). Two cur- The multiplication factor of the conventional current-mode
rent sources I1 and I2 are used to simultaneously charge the capacitor multiplier in (2) is (1 + Kx ), but its total power con-
compensation capacitor Cc . The Vc equation can be derived as sumption is also (1 + Kx ) times that of the capacitor Cc with-
  out the capacitor multiplier technique. The multiplication fac-
Vc (s) = I1 Rc +
(I1 + I2 )
. (5) tor of the DPEA technique is (1 − α)−1 , and the total power
sCc I1 consumption is only increased by (1 + α), where α is less than
1. When the values of the two currents I1 and I2 are closer, the
Assuming that current I2 is equal to −αI1 and α is less than effective capacitance multiplication is larger. Hence, the dual-
1, the Vc equation can be rewritten as path architecture technique is more area- and power-efficient
  than the conventional current-mode capacitor multiplier.
1
Vc (s) = I1 Rc + . (6)
s (1 − α)−1 Cc
B. Subtractive-Type and Time-Average Capacitor Multiplier
Based on (6), the equivalent impedance of Vc to I1 of Fig. 4(a) Techniques for the Soft-Start Function
becomes a series connection of the original resistor and the
amplified capacitor as shown in Fig. 4(b). Hence, the zero z1 of Large inrush current and large output overshoot voltage usu-
Fig. 4(b) can be given as ally occur due to the large difference between the output feed-
back voltage and the reference voltage of the error amplifier
1
z1 = . (7) during the start-up period. To solve the above two issues and re-
(1 − α)−1 Rc Cc duce capacitance area, the proposed simplified soft-start circuit
1406 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 3, MARCH 2015

is presented in Fig. 5(a). The soft-start methodology uses the

subtractive-type and time-average capacitor multipliers to pro-
long the start-up time with on-chip capacitors. The subtractive-
type capacitor multiplier adopts two current sources I1 and I2 to
realize a tiny controllable charging current Ic1 . The time-average
capacitor multiplier shortens the charging time of current I3 to
make voltage Vref ss increase slowly.
The operation of the proposed soft-start circuit is described in
the following. Current Ic1 is tiny when current I2 is close to but
less than current I1 , and in this case, voltage Vram p increases
Fig. 6. Block diagram of the soft-start cascade architecture.
gradually. Hence, this study adopts the subtraction concept to
realize a tiny current without complex circuitry. When volt-
age Vram p is over Vref , voltage Vcm p changes to the low-level
state. Consequently, switch S2 is turned ON, so capacitor Cs2 is
charged with current I3 , and then, voltage Vref ss is increased.
In the meantime, voltage Vs1 is forced to the high level through
a delay circuit and an inverter. Hence, switch S1 is turned ON to
discharge Vram p quickly during the period when Vcm p is at the
low level. When Vram p drops lower than Vref , Vcm p transforms
to the high-level state to switch S1 and S2 OFF to stop discharg-
ing Vram p and charging Vref ss , respectively. In order to mini-
mize the low-level state of voltage Vcm p , the propagation time
of the delay circuit and the discharging current Is1 should be Fig. 7. Schematic diagram of the DPEA.
short and large, respectively. Compared to clock-based soft-start
circuits, the time-average capacitor multiplier realizes a “short-
function can be enlarged significantly. To further amplify the
pulse-turn-on” period with simple circuitry. Since switch S2 is
multiplication factor, the cascade architecture can be adopted
controlled by Vcm p , Vref ss increases slowly. Consequently, the
as shown in Fig. 6. The comparator used in the time-average
soft-start function is achieved.
capacitor multiplier can be replaced with an inverter for saving
The waveforms of the simplified soft-start circuit are sketched
power. Since Vss2 is connected to another time-average capac-
in Fig. 5(b). Voltage Vram p is charged and discharged continu-
itor multiplier, Vss2 will be discharged when its value exceeds
ously, so its waveform is like a sawtooth. Since voltage Vref ss is
Vref . Therefore, the rising time of voltage Vref ss can be pro-
charged discretely, its amplitude increases slowly as a staircase
longed by cascading another time-average capacitor multiplier.
waveform. Based on the equation Q = CV = It, the period t1
The multiplication factor N2 contributed by time-average ca-
and (t2 − t1 ) can be expressed, respectively, as
pacitor multiplier 2 and the total soft-start time of Fig. 6 can be
Cs1 × Vref approximately given, respectively, as
t1 ≈ + delay (8)
I1 − I2 Cs3 Vref
N2 ≈ (11)
(I1 − I2 ) delay I4 × delay
t2 − t1 = + delay ≈ delay (9)
Cs1 Is1 3
Cs1 Cs2 Cs3 Vref
tss ≈ . (12)
where the delay represents the propagation time of the delay (1 − β) I1 I3 I4 × delay2
circuit and inverter. Assuming Vref /V1 = N1 and I2 = βI1 , the
total soft-start time can be derived as Hence, the soft-start time can easily be prolonged dramati-
Cs2 Vref cally with the cascade architecture.
N1 ≈
I3 × delay
C. Implementation of the DPEA
2
Cs1 Cs2 Vref 2Cs2 Vref
tss ≈ + . (10) The implementation of the DPEA is shown in Fig. 7. The two
(1 − β) I1 I3 × delay I3
OTAs, OT A1 and OT A2 , are used as the two current sources I1
The first term in (10) becomes large when I2 is close to I1 and I2 in Fig. 4(a). OT A1 is composed of two OTAs, OT A11
and when delay approaches zero. Hence, the total soft-start time and OT A12 , which are used to improve load regulation. Two
is dramatically long even with the two small capacitors. As input signals of the DPEA are the output feedback voltage Vfb
a result, the restriction of the charging current can be relaxed and the output Vref ss of the proposed soft-start circuit. To make
significantly and the soft-start capacitance can be integrated into the direction of currents I1 and I2 opposite, signal Vref ss is
a chip. connected to the noninverting input of OT A11 and the inverting
With a comparator CMP, switch S1 , and delay line in Fig. 5(a) input of OT A2 , and signal Vfb is connected to the inverting
to combine the subtractive-type and time-average capacitor mul- input of OT A11 and the noninverting input of OT A2 . OT A11
tipliers, the capacitance multiplication factor of the soft-start and OT A2 adopt conventional current mirror OTA shown in
LIU et al.: TECHNIQUES OF DUAL-PATH ERROR AMPLIFIER AND CAPACITOR MULTIPLIER FOR ON-CHIP COMPENSATION 1407

Fig. 9. Schematic diagram of the on-chip soft-start function.

The two poles p1 and p2 are at high frequency because Co1

and Ro1 are small. The dc gain of the DPEA can be found
approximately as
(1 − α) Ro2 + Rc
dc gain of DPEA ≈ Av ,ota11 (16)
Ro12 + Ro2 + Rc
where Av ,ota11 is the voltage gain of OTA11 . When OTA12 is re-
moved, the dc gain of the DPEA can be rewritten approximately
as
dc gain of DPEA without OTA12
Gm 11 Ro11 [(1 − α) Ro2 + Rc ]
≈ (17)
Ro11 + Ro2 + Rc
where Gm 11 and Ro11 are the transconductance and output
Fig. 8. Schematic of OTA for (a) OTA11 and OTA2 and (b) OTA12. resistor of OTA11 , respectively. The dc gain of the DPEA is
enhanced by adding OTA12 because the Ro11 is larger than
Ro12 . Therefore, the load regulation of the dc–dc converter with
Fig. 8(a). To obtain high dc gain, OT A12 uses the cascade
the DPEA can be improved.
OTA architecture shown in Fig. 8(b). The cascade OTA and its
When the load current changes from light load to heavy load,
bias circuit are composed of transistors M1 –M16 and transistors
the output feedback voltage Vfb drops down. Then, the values of
Mb 1 –Mb 9 , respectively.
currents I1 and I2 of Fig. 7 become larger and smaller, respec-
Assuming that current I2 is equal to αI1 , the transfer function
tively. Since the variation of I1 is larger than that of I2 and the
of the DPEA can be formulated as (13), shown at the bottom of
compensation capacitor Cc is small, the output voltage Vc of the
the page where Co12 and Co2 represent the output capacitance of
DPEA increases immediately and significantly. Consequently,
the OT A12 and OT A2 , respectively. Ro12 and Ro2 represent the
the transient response of the dc–dc converter is improved dra-
output resistor of OT A12 and OT A2 , respectively. Assuming
matically. Similarly, when the load current changes from heavy
Ro2 is large, the left-half-plane zero z1 is given by
load to light load, voltage Vc decreases immediately and sig-
1 nificantly. Therefore, the response time of the buck converter is
z1 ≈ . (14) also shortened significantly.
(1 − α)−1 Rc (Cc + Co2 )
D. Implementation of the On-Chip Soft-Start Circuit
The zero z1 is at low frequency when α approaches 1. For the
second-order polynomial in the denominator of (13), two poles The implementation of the on-chip soft-start circuit is shown
can be approximately calculated as in Fig. 9. The circuit of the subtractive-type capacitor multiplier
is composed of transistors M1 –M5 , inverters inv1 –inv3 , and
1 1 capacitor Cs1 . Before the buck converter operates, the reference
p1 = +
Co 1 2 [Ro 1 2 || (Ro 2 + Rc )] (Cc + Co 2 ) [Ro 2 || (Ro 1 2 + Rc )] voltage Vref should be around zero value, so transistors M5
1 and M9 are turned ON to discharge capacitors Cs1 and Cs2 ,
p2 ≈ . (15) respectively. This action makes sure the output voltage Vref ss
Co 1 2 (Ro 1 2 ||Rc )

Vc (s) Ro12 [(1 − α) Ro2 + Rc ] (1 + s/sz1 ).

= (13)
I1 (s) Ro12 + Ro2 + Rc + s [Ro12 Co12 (Ro2 + Rc ) + Ro2 (Cc + Co2 ) (Ro12 + Rc )] + s2 Ro12 Ro2 Rc Co12 (Cc + Co2 )
1408
Fig. 10. Chip microphotograph.
TABLE I
DESIGN PARAMETERS OF THE BUCK CONVERTER
of the soft-start circuit is reset from zero value before the start-up
phase. After the buck converter is powered-on, Vref is changed
to the predefined value. Then, signals SEL and SELB transform
to high-level and low-level states, respectively, so the currents
of transistors M1 , M3 , and M7 are set. By setting the aspect
ratio of transistors M2 to M4 , the current ratio of the drain
currents of M4 to M3 is set to β. A nanoampere-order current
Ics1 is released when β approaches 1, and then, Vram p increases
slowly.
When Vram p rises higher than Vref , Vcm p transfers to the low-
level state, so transistor M8 is turned ON to charge capacitor
Cs2 . In the meantime, transistor M6 is converted to the ON
state when Vcm p passes through inverter inv3 , and then, Vram p
is discharged quickly through M6 . When Vram p drops lower
than Vref , transistor M8 is OFF to stop charging Cs2 . Since the
inv3 propagation delay is short and the M6 discharging capa-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 3, MARCH 2015
Fig. 11. Simulated transient response of the buck converter with the DPEA
for (a) step-up and (b) step-down loads.
bility is large, voltage Vref ss increases slowly because of the
short charging period. The tiny current Ics1 continues charging
Cs1 again when M6 is turned OFF. When Vref ss exceeds the
value of Vref , the control signals SEL and SELB change to low-
level and high-level states, respectively, to turn transistors M1 ,
M3 , and M7 OFF for power saving. Combining the subtractive-
type and time-average capacitor multiplier techniques, the start-
up time is prolonged dramatically with small capacitance and
simple circuitry.
III. VERIFICATION AND EXPERIMENTAL RESULTS
The proposed buck converter is fabricated with a standard
0.35-μm 2-poly-4-metal (2P4M) CMOS technology. The mi-
crophotograph of the chip is shown in Fig. 10, and the active
area and chip area including testing pads are 800 × 730 and
1146 × 1173 μm2 , respectively. The specification of the buck
dc–dc converter, the compensation components, and soft-start
capacitors are listed in Table I. Since the values of the capacitors
used in frequency compensation and soft-start function are 0.5
and 1 pF, respectively, it is easy to integrate them into a chip.
Fig. 11 shows the simulated transient response of the buck
converter with the DPEA when the load current changes from
LIU et al.: TECHNIQUES OF DUAL-PATH ERROR AMPLIFIER AND CAPACITOR MULTIPLIER FOR ON-CHIP COMPENSATION
Fig. 12. Simulated transient response of the buck converter without OTA12
for (a) step-up and (b) step-down loads.
light load to heavy load and then back to light load. The
signals of Fig. 11 from top to down are the output voltage Vo ,
load current Io , inductor current IL , and PWM driving signal
VPW M , respectively. For step-up load as shown in Fig. 11(a),
the output voltage Vo drops down, and then, the Vc of Fig. 7 is
charged quickly. Since the compensation capacitor Cc is small,
the slewing of the DPEA is enhanced. Hence, the duty ratio of
VPW M is minimized, and then, the inductor current increases
with maximum changing rate. Consequently, the recovery time
and transient ripple of the buck converter is enhanced dramati-
cally. Similarly, for step-down load as shown in Fig. 11(b), the
buck converter has great transient response performance.
Fig. 12 shows the simulated transient response of the buck
converter with the DPEA, but OTA12 in Fig. 7 is removed. When
the load current changes from 50 to 500 mA, the output voltage
difference between the two currents is about 50 mV without
OTA12 . It resulted from the smaller dc gain of the DPEA, which
is shown in (17), because of large Ro11 . For Fig. 11, the output
voltage difference is less than 5 mV.
The input and output voltages for all measurement are 5 and
3.3 V, respectively. Fig. 13(a) shows the transient response of the
buck converter for the step-up load from 50 to 500 mA. With the
DPEA, it takes 20 μs for the output voltage to resume its steady-
state value with a transient ripple of 25 mV. Fig. 13(b) shows the
1409
Fig. 13. Measured transient responses of the buck converter with the DPEA
for (a) step-up and (b) step-down loads.
Fig. 14. Output waveforms of the buck converter with the on-chip soft-start
mechanism.
transient response of the buck converter with the DPEA for the
step-down load from 500 to 50 mA. It takes 15 μs for the output
voltage to resume its steady-state value with a transient ripple
of 15 mV. The waveforms of Fig. 13(a) and (b) demonstrate that
the DPEA not only amplifies the small compensation capacitor
to keep the output voltage stable, but also significantly improves
the transient response of the dc–dc converter.
Fig. 14 shows the measured start-up results of the buck con-
verter with the on-chip soft-start circuit. The first and second
trails are the output voltage and inductor current waveforms.
Since Vref ss is controlled by the soft-start circuit, the output
voltage and inductor current increase slowly without overshoot
and inrush current during the start-up period. Two capacitor
1410
multipliers are combined together, resulting in a soft-start time
of up to 8 ms with 6.6-Ω load.
IV. CONCLUSION
This paper proposes the dual-path capacitor multiplier for
providing frequency compensation. This paper proposes tech-
niques of the DPEA, subtractive-type capacitor multiplier, and
time-average capacitor multiplier for frequency compensation
and soft-start mechanism. The DPEA uses two currents to pro-
vide on-chip compensation while sacrificing little additional
power and keeping silicon area small. The slewing of the DPEA
is improved because of the small compensation capacitor, so
the transient response of the buck converter is also enhanced
dramatically. Since the proposed soft-start function combines
subtractive-type and time-average capacitor multipliers, the re-
striction of the capacitance and the charging current can be
relaxed significantly. The experimental results demonstrate that
the transient recovery time and transient ripple are less than
20 μs and 25 mV, respectively, when load current changes be-
tween 50 and 500 mA. Thanks to the two capacitor-multiplier
techniques, the soft-start time can be prolonged up to 8 ms.
With the proposed dual-path architecture and capacitor multi-
plier techniques, the external pins of the dc–dc converters are
minimized and their performance is improved dramatically.
ACKNOWLEDGMENT
The authors would like to thank National Chip Implementa-
tion Center, Taiwan, for chip fabrication.
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Pang-Jung Liu (S’08–M’10) received the B. S. and
M.S. degrees from the National Taiwan University of
Science and Technology, Taipei, Taiwan, in 1998 and
2000, respectively, and the Ph.D. degree from the
Graduate Institute of Electronics Engineering, Na-
tional Taiwan University, Taipei, in 2010.
From 2000 to 2003, he was an Engineer at Taiwan
Semiconductor Manufacturing Company. From 2003
to 2005, he was working on digital IC design with
ELAN Microelectronics Corporation. From August
2010 to January 2012, he was with the Department
of Electrical Engineering, National Ilan University, I-Lan, Taiwan. Since 2012,
he has been with the Department of Electrical Engineering, Taipei University of
Technology, Taipei, where he is currently an Assistant Professor. His research
interests include power management IC, LCD/LED driver, and mixed-mode IC
design.
Chih-Yao Hsu was born in Taichung, Taiwan, in
1987. He received the B.S. degree in electronic en-
gineering from National Taiwan Ocean University,
Keelung, Taiwan, in 2010, and the M.S. degree in
electrical engineering from the National Taiwan Uni-
versity of Science and Technology, Taipei, Taiwan,
in 2012.
His research interests include integrated power
management system designs and analog integrated
circuits.
Yi-Hsiang Chang was born in Taipei, Taiwan, in
1988. He received the B.S. degree in electronic engi-
neering and the M.S. degree in electrical engineering
from the National Taiwan University of Science and
Technology, Taipei, in 2011 and 2013, respectively.
His research interests include integrated power
management system designs and analog integrated
circuits.