Vous êtes sur la page 1sur 21

Contents

FET Small-Signal Analysis


FET SSAC Analysis Steps
FET Small-Signal Model
Common-Source Fixed-Bias Conguration
Input Resistance
Voltage Gain
Output Resistance
Common-Source Self-Bias Conguration
Input Resistance
Voltage Gain
Output Resistance
Common-Source Voltage-Divider Bias Conguration
Input Resistance
Voltage Gain
Output Resistance
Common-Source Unbypassed Self-Bias Conguration
Input Resistance
Voltage Gain
Output Resistance
Source-Follower Conguration
Input Resistance
Voltage Gain
Output Resistance
Common-Source Drain Feedback Conguration
Input Resistance
Voltage Gain
Output Resistance
Common-Gate Conguration
Input Resistance
Voltage Gain
Output Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 1 / 42

FET Small-Signal Analysis

FET SSAC Analysis Steps


1. Draw the SSAC equivalent circuit
a) Draw the AC equivalent circuit (signal frequency is innity, i.e., f = ∞)
i. Capacitors are short circuit, i.e., XC → 0.
ii. Kill the DC power sources (i.e., AC value of DC sources is zero).
b) Replace FET with its small-signal equivalent model.

2. Calculate the three amplier parameters: Ri , Ro and Av



a) Calculate no-load input resistance, Ri = vi
ii R =∞
.
L
b) Calculate output resistance, Ro .
c) Calculate no-load voltage gain, Av = vo
vi R =∞
.
L

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 2 / 42
FET Small-Signal Analysis FET Small-Signal Model

FET Small-Signal Model


Small-signal equivalent model for a FET transistor is provided below. This model and its analysis
is the same for all FET types, i.e., JFET, DMOSFET, EMOSFET, n-channel and p-channel.

Here,

∂ID
g m = g f s = yf s = is the forward transfer conductance,
∂VGS Q-point

1 1 ∂VDS
rds = = = is the output resistance.
gos yos ∂ID Q-point

Forward transfer conductance gm is mostly called as the transconductance parameter.

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 3 / 42

FET Small-Signal Analysis FET Small-Signal Model


When rds 6= ∞, we can also use the voltage-controlled voltage source model (via
Norton-to-Thévenin transformation) as shown below. We mostly use this model for the
common-gate and unbypassed self-bias congurations.

Here µ = gm rds is the forward transfer-voltage gain.

Typical values of gm run from 1 mS to 5 mS,


Typical values of rds run from 20 kΩ to 100 kΩ,
Consequently, typical values of µ run from 20 to 500.

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 4 / 42
FET Small-Signal Analysis FET Small-Signal Model

Transconductance Parameter (gm)


Transconductance parameter gm is given by

∂ID ∼ ∆ID
gm = =
∂VGS Q-point ∆VGS Q-point

In other words, gm is the slope of the characteristics at the point of operation as shown below.

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 5 / 42

FET Small-Signal Analysis FET Small-Signal Model

 2
I Let us derive gm for the JFET equation, ID = IDSS 1 − VGS
VP

 
∂ID 2IDSS VGS
gm = = 1−
∂VGS Q-point |VP | VP Q-point
 
2IDSS VGSQ
= 1−
|VP | VP
s
VGSQ 2
 
2IDSS IDQ
= . . . IDQ = IDSS 1 −
|VP | IDSS VP
s
IDQ 2IDSS
= gm0 . . . gm0 =
IDSS |VP |

I Let us derive gm for the MOSFET equation, ID = k VGS − VGS(T h)


2


∂ID 
gm = = 2k VGS − VGS(T h) Q-point
∂VGS Q-point


= 2k VGSQ − VGS(T h)
√ p 2
= 2 k IDQ . . . IDQ = k VGS − VGS(T h)

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 6 / 42
FET Small-Signal Analysis FET Small-Signal Model

Phase Relationship
The phase relationship between input and output depends on the amplier conguration circuit
as listed below.

Common-Source: 180 degrees


Common-Gate: 0 degrees
Common-Drain: 0 degrees (Source-Follower)

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 7 / 42

FET Small-Signal Analysis Common-Source Fixed-Bias Conguration

Common-Source Fixed-Bias Conguration


Common-source xed-bias conguration is given below

Corresponding SSAC equivalent circuit is shown below

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 8 / 42
FET Small-Signal Analysis Common-Source Fixed-Bias Conguration

Input Resistance

Input resistance Ri is given as



vi
Ri = = RG
ii RL =∞

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 9 / 42

FET Small-Signal Analysis Common-Source Fixed-Bias Conguration

Voltage Gain

No-load voltage gain Av is given by


   
vo vo gm vgs vgs
Av = =
vi RL =∞ gm vgs vgs vi
= (−RD ||rds ) (gm ) (1)
= −gm (RD ||rds )

If rds ≥ 10RD , voltage gain Av reduces to


Av = −gm RD

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 10 / 42
FET Small-Signal Analysis Common-Source Fixed-Bias Conguration

For the circuit above, we can obtain the current gain Ai as follows

io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD

If rds ≥ 10RD , current gain Ai reduces to


Ai = −gm RG

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 11 / 42

FET Small-Signal Analysis Common-Source Fixed-Bias Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.

vtest
Ro = = RD ||rds
itest vs =0,RL =vtest

If rds ≥ 10RD , then Ro simplies to Ro = RD .

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 12 / 42
FET Small-Signal Analysis Common-Source Self-Bias Conguration

CS Self-Bias Conguration
Common-source self-bias conguration is given below

Corresponding SSAC equivalent circuit is shown below

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 13 / 42

FET Small-Signal Analysis Common-Source Self-Bias Conguration

Input Resistance

Input resistance Ri is given as



vi
Ri = = RG
ii RL =∞

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 14 / 42
FET Small-Signal Analysis Common-Source Self-Bias Conguration

Voltage Gain

No-load voltage gain Av is given by


   
vo vo gm vgs vgs
Av = =
vi RL =∞ gm vgs vgs vi
= (−RD ||rds ) (gm ) (1)
= −gm (RD ||rds )

If rds ≥ 10RD , no-load voltage gain Av reduces to


Av = −gm RD

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 15 / 42

FET Small-Signal Analysis Common-Source Self-Bias Conguration

For the circuit above, we can obtain the current gain Ai as follows

io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD

If rds ≥ 10RD , current gain Ai reduces to


Ai = −gm RG

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 16 / 42
FET Small-Signal Analysis Common-Source Self-Bias Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.

vtest
Ro = = RD ||rds
itest vs =0,RL =vtest

If rds ≥ 10RD , then Ro simplies to Ro = RD .

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 17 / 42

FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration

CS Voltage-Divider Bias Conguration


Common-source voltage-divider bias conguration is given below

Corresponding SSAC equivalent circuit is shown below

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 18 / 42
FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration

Input Resistance

Input resistance Ri is given as



vi
Ri = = R1 ||R2
ii RL =∞

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 19 / 42

FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration

Voltage Gain

No-load voltage gain Av is given by


   
vo vo gm vgs vgs
Av = =
vi RL =∞ gm vgs vgs vi
= (−RD ||rds ) (gm ) (1)
= −gm (RD ||rds )

If rds ≥ 10RD , no-load voltage gain Av reduces to


Av = −gm RD

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 20 / 42
FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration

For the circuit above, we can obtain the current gain Ai as follows

io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD

If rds ≥ 10RD , current gain Ai reduces to


Ai = −gm (R1 ||R2 )

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 21 / 42

FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.

vtest
Ro = = RD ||rds
itest vs =0,RL =vtest

If rds ≥ 10RD , then Ro simplies to Ro = RD .

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 22 / 42
FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration

CS Unbypassed Self-Bias Conguration


Common-source unbypassed self-bias conguration and its SSAC equivalent circuit are
given on the left and right gures below, respectively.

When RS is not bypassed, we normally use the voltage-controlled voltage source model in
the small-signal equivalent circuit as shown above.

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 23 / 42

FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration

Input Resistance

Input resistance Ri is given as



vi
Ri = = RG
ii RL =∞

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 24 / 42
FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration

Voltage Gain

No-load voltage gain Av is given by


   
vo vo id vgs
Av = =
vi R id vgs vi
L =∞
  
µ vgs µvgs
= (−RD ) . . . id =
RS + RD + rds vgs + id RS RS + RD + rds
 
 
µ 1
= (−RD ) 
µRS

RS + RD + rds 1+ RS +RD +rds

µRD
=− . . . µ = gm rds
(µ + 1) RS + RD + rds
gm RD
=− RS +RD
1 + g m RS + rds

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 25 / 42

FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration

If rds ≥ 10 (RD + RS ), no-load voltage gain Av reduces to


gm RD
Av = −
1 + gm RS

If rds ≥ 10 (RD + RS ) and gm RS  1, no-load voltage gain Av reduces to


RD
Av ≈ −
RS
For the circuit above, we can obtain the current gain Ai as follows
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 26 / 42
FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above.

vtest vtest
Ro = = + id
itest vs =0,RL =vtest
RD
vtest vgs −vgs
= − . . . vs = −vgs , id =
RD RS RS
vtest vtest vtest
= + . . . vgs = −
RD (µ + 1) RS + rds (µ + 1) + rds /RS
= RD || [(µ + 1) RS + rds ] . . . µ = gm rds
= RD || [(gm RS + 1) rds + RS ]

= RD

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 27 / 42

FET Small-Signal Analysis Source-Follower Conguration

Source-Follower Conguration
Source-follower (common-drain) conguration is given below

Corresponding SSAC equivalent circuit is shown below

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 28 / 42
FET Small-Signal Analysis Source-Follower Conguration

Input Resistance

Input resistance Ri is given as



vi
Ri = = RG
ii RL =∞

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 29 / 42

FET Small-Signal Analysis Source-Follower Conguration

Voltage Gain

No-load voltage gain Av is given by


  
vo vo vgs
Av = =
vi RL =∞ vgs vi
 
1
= [gm (RS ||rds )] . . . vi = vgs + vo
1 + gm (RS ||rds )
gm (RS ||rds )
=
1 + gm (RS ||rds )

=1

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 30 / 42
FET Small-Signal Analysis Source-Follower Conguration

For the circuit above, we can obtain the current-gain Ai as follows


io vo /RS Ri vo
Ai = = =
ii vi /Ri RS vi
Ri
= Av
RS

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 31 / 42

FET Small-Signal Analysis Source-Follower Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test voltage
circuit above.

vtest vtest
Ro = = − gm vgs
itest vs =0,R RS ||rds
L =vtest
vtest
= + gm vtest . . . vtest = −vgs
RS ||rds
vtest vtest
= +
RS ||rds 1/gm
1
= RS ||rds ||
gm
If (RS ||rds ) ≥ 10/gm , output resistance Ro reduces to

1
Ro ∼
=
gm

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 32 / 42
FET Small-Signal Analysis Common-Source Drain Feedback Conguration

CS Drain Feedback Conguration


Common-source drain feedback bias conguration is given below

Corresponding SSAC equivalent circuit is shown below

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 33 / 42

FET Small-Signal Analysis Common-Source Drain Feedback Conguration

Input Resistance

Input resistance Ri is given as



vi vgs
Ri = = . . . vi = vgs
ii RL =∞
gm vgs + vo / (RD ||rds )
RF + RD ||rds (1 − gm RF ) (RD ||rds ) vgs
= . . . vo =
1 + gm (RD ||rds ) RF + RD ||rds
∼ RF
= . . . RF  RD ||rds
1 + gm (RD ||rds )

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 34 / 42
FET Small-Signal Analysis Common-Source Drain Feedback Conguration

Voltage Gain

No-load voltage gain Av is given by



vo (1 − gm RF ) (RD ||rds )
Av = = . . . vi = vgs
vi RL =∞
RF + RD ||rds

= −gm (RD ||rds ||RF ) . . . g m RF  1

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 35 / 42

FET Small-Signal Analysis Common-Source Drain Feedback Conguration

For the circuit above, we can obtain the current-gain Ai as follows

io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 36 / 42
FET Small-Signal Analysis Common-Source Drain Feedback Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.

vtest
Ro = = RD ||rds ||RF
itest vs =0,RL =vtest

If a voltage source with source resistance Rs is connected to the input, replace RF with
[(RF + Rs ) / (1 + gm Rs )] in Ro calculations.

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 37 / 42

FET Small-Signal Analysis Common-Gate Conguration

Common-Gate Conguration
Common-gate conguration is given below

Corresponding SSAC equivalent circuit is shown below

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 38 / 42
FET Small-Signal Analysis Common-Gate Conguration

Input Resistance

Input resistance Ri is given as



vi vi
Ri = = . . . vi = −vgs
ii RL =∞
vi /RS − id
vi (µ + 1) vgs
=   . . . id =
RD +rds RD + rds
vi /RS + vi / µ+1
RD + rds
= RS || . . . µ = gm rds
1 + gm rds
1

= RS || . . . rds ≥ 10RD and gm rds  1
gm

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 39 / 42

FET Small-Signal Analysis Common-Gate Conguration

Voltage Gain

No-load voltage gain Av is given by



vo −id RD
Av = = . . . vi = −vgs
vi RL =∞
−vgs
(µ + 1) RD (µ + 1) vgs
= . . . id =
RD + rds RD + rds
(gm rds + 1) RD
= . . . µ = gm rds
RD + rds

= gm RD . . . rds ≥ 10RD and gm rds  1

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 40 / 42
FET Small-Signal Analysis Common-Gate Conguration

For the circuit above, we can obtain the current-gain Ai as follows

io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD

If rds ≥ 10RD and gm rds  1, current-gain Ai reduces to


 
1
Ai = gm RS || ≈1
gm

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 41 / 42

FET Small-Signal Analysis Common-Gate Conguration

Output Resistance

Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.

vtest
Ro = = RD ||rds
itest vs =0,RL =vtest

If rds ≥ 10RD , then Ro simplies to Ro = RD .


If a voltage source with source resistance Rs is connected to the input, replace rds with
([1 + gm (Rs ||RG )] rds + Rs ||RG ) in Ro calculations. We can say that Ro ≈ RD in
most cases.

Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 42 / 42

Vous aimerez peut-être aussi