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Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 2 / 42
FET Small-Signal Analysis FET Small-Signal Model
Here,
∂ID
g m = g f s = yf s = is the forward transfer conductance,
∂VGS Q-point
1 1 ∂VDS
rds = = = is the output resistance.
gos yos ∂ID Q-point
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 3 / 42
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 4 / 42
FET Small-Signal Analysis FET Small-Signal Model
In other words, gm is the slope of the characteristics at the point of operation as shown below.
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 5 / 42
2
I Let us derive gm for the JFET equation, ID = IDSS 1 − VGS
VP
∂ID 2IDSS VGS
gm = = 1−
∂VGS Q-point |VP | VP Q-point
2IDSS VGSQ
= 1−
|VP | VP
s
VGSQ 2
2IDSS IDQ
= . . . IDQ = IDSS 1 −
|VP | IDSS VP
s
IDQ 2IDSS
= gm0 . . . gm0 =
IDSS |VP |
∂ID
gm = = 2k VGS − VGS(T h) Q-point
∂VGS Q-point
= 2k VGSQ − VGS(T h)
√ p 2
= 2 k IDQ . . . IDQ = k VGS − VGS(T h)
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 6 / 42
FET Small-Signal Analysis FET Small-Signal Model
Phase Relationship
The phase relationship between input and output depends on the amplier conguration circuit
as listed below.
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 7 / 42
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 8 / 42
FET Small-Signal Analysis Common-Source Fixed-Bias Conguration
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 9 / 42
Voltage Gain
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 10 / 42
FET Small-Signal Analysis Common-Source Fixed-Bias Conguration
For the circuit above, we can obtain the current gain Ai as follows
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 11 / 42
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.
vtest
Ro = = RD ||rds
itest vs =0,RL =vtest
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 12 / 42
FET Small-Signal Analysis Common-Source Self-Bias Conguration
CS Self-Bias Conguration
Common-source self-bias conguration is given below
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 13 / 42
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 14 / 42
FET Small-Signal Analysis Common-Source Self-Bias Conguration
Voltage Gain
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 15 / 42
For the circuit above, we can obtain the current gain Ai as follows
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 16 / 42
FET Small-Signal Analysis Common-Source Self-Bias Conguration
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.
vtest
Ro = = RD ||rds
itest vs =0,RL =vtest
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 17 / 42
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 18 / 42
FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 19 / 42
Voltage Gain
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 20 / 42
FET Small-Signal Analysis Common-Source Voltage-Divider Bias Conguration
For the circuit above, we can obtain the current gain Ai as follows
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 21 / 42
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.
vtest
Ro = = RD ||rds
itest vs =0,RL =vtest
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 22 / 42
FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration
When RS is not bypassed, we normally use the voltage-controlled voltage source model in
the small-signal equivalent circuit as shown above.
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 23 / 42
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 24 / 42
FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration
Voltage Gain
µRD
=− . . . µ = gm rds
(µ + 1) RS + RD + rds
gm RD
=− RS +RD
1 + g m RS + rds
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 25 / 42
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 26 / 42
FET Small-Signal Analysis Common-Source Unbypassed Self-Bias Conguration
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above.
vtest vtest
Ro = = + id
itest vs =0,RL =vtest
RD
vtest vgs −vgs
= − . . . vs = −vgs , id =
RD RS RS
vtest vtest vtest
= + . . . vgs = −
RD (µ + 1) RS + rds (µ + 1) + rds /RS
= RD || [(µ + 1) RS + rds ] . . . µ = gm rds
= RD || [(gm RS + 1) rds + RS ]
∼
= RD
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 27 / 42
Source-Follower Conguration
Source-follower (common-drain) conguration is given below
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 28 / 42
FET Small-Signal Analysis Source-Follower Conguration
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 29 / 42
Voltage Gain
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 30 / 42
FET Small-Signal Analysis Source-Follower Conguration
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 31 / 42
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test voltage
circuit above.
vtest vtest
Ro = = − gm vgs
itest vs =0,R RS ||rds
L =vtest
vtest
= + gm vtest . . . vtest = −vgs
RS ||rds
vtest vtest
= +
RS ||rds 1/gm
1
= RS ||rds ||
gm
If (RS ||rds ) ≥ 10/gm , output resistance Ro reduces to
1
Ro ∼
=
gm
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 32 / 42
FET Small-Signal Analysis Common-Source Drain Feedback Conguration
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 33 / 42
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 34 / 42
FET Small-Signal Analysis Common-Source Drain Feedback Conguration
Voltage Gain
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 35 / 42
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 36 / 42
FET Small-Signal Analysis Common-Source Drain Feedback Conguration
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.
vtest
Ro = = RD ||rds ||RF
itest vs =0,RL =vtest
If a voltage source with source resistance Rs is connected to the input, replace RF with
[(RF + Rs ) / (1 + gm Rs )] in Ro calculations.
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 37 / 42
Common-Gate Conguration
Common-gate conguration is given below
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 38 / 42
FET Small-Signal Analysis Common-Gate Conguration
Input Resistance
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 39 / 42
Voltage Gain
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 40 / 42
FET Small-Signal Analysis Common-Gate Conguration
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av
RD
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 41 / 42
Output Resistance
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test
voltage circuit above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.
vtest
Ro = = RD ||rds
itest vs =0,RL =vtest
Dr. U. Sezen & Dr. D. Gökcen (Hacettepe Uni.) ELE230 Electronics I 21-Apr-2018 42 / 42