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• We have four common types of memory:
• Read only memory ( ROM )
• Flash memory ( EEPROM )
• Static Random access memory ( SARAM )
• Dynamic Random access memory ( DRAM ).
• Pin connections common to all memory devices are: The
address input, data output or input/outputs, selection input
and control input used to select a read or write operation.
A1 O1 OUTPUT OR
ADDRESS INPUT/OUTPUT
CONNECTION A2 O2 CONNECTION
AN ON
WE WRITE
CS OE
SELECT READ
MEMORY COMPONENT ILLUSTRATING THE ADDRESS, DATA AND
,
CONTROL CONNECTIONS
M. Krishna Kumar MM/M3/LU8/V1/2004
Interface (cont..)
A0 –A10 ADDRESSES
CS CHIP SELECT
CHIP SELECT
CS POWER DOWN
AND PROGRAM OUTPUT
PD / PGM
LOGIC BUFFERS
Y Y-GATING
A0 - A10 DECODER
ADDRESS
INPUTS
16,386 BIT
X CELL
DECODER MATRIX
BLOCK DIAGRAM
M. Krishna Kumar MM/M3/LU8/V1/2004
Interface (cont..)
• Static RAM memory device retain data for as long as DC
power is applied. Because no special action is required to
retain stored data, these devices are called as static
memory. They are also called volatile memory because
they will not retain data without power.
• The main difference between a ROM and RAM is that a
RAM is written under normal operation, while ROM is
programmed outside the computer and is only normally
read.
• The SRAM stores temporary data and is used when the
size of read/write memory is relatively small.
S CHIP SELECT
DATA IN /
DQ _ DQ
0 8 DATA OUT
OUT PUT
G ENABLE
Vss GROUND
Vcc + 5 V
SUPPLY
PIN NAMES
CE1
A7 – A13
A7 – A13
16K*1 16K*1 16K*1 16K*1 16K*1 16K*1 16K*1 16K*1
A6 – A0
OE CE OE CE OE CE OE CE OE CE OE CE OE CE OE CE
CE2
7 bit
A0-A6 bus
MUX
Ar0
–
Ar6 CE1 CE2
Address
Refresh Deciding logic
Ref. Add Refresh
timer
Counter A15 A14
To transreceivers
Dynamic RAM Refreshing Logic
M. Krishna Kumar MM/M3/LU8/V1/2004
+12 V CLK
X0/OP2 X1/CLK
Bank Select B0 Vcc
16K/64K
AH0 -AH7
OUT7 – OUT0
ADDRESS Address O/P
AL0 -AL7
CAS
Dout
WE
8267
XACK XCIEVER
XACK CS
WR