PmodALS

Features
 Simple ambient light sensor
 Convert light to digital data with 8-bit resolution
 6-pin Pmod port with SPI interface

Functional Description
The PmodALS utilizes a single ambient light sensor (ALS) for user input. The amount of light the ALS is exposed
to determines the voltage level passed into the ADC, which converts it to 8-bits of data. A value of 0 indicates a
low light level and a value of 255 indicates a high light level.

Interfacing with the Pmod

The PmodALS communicates with the host board via the SPI protocol. Since the on-board analog-to-digital
converter is a read-only module, the only wires in the SPI protocol that are required are the Chip Select, Master-
In-Slave-Out, and Serial Clock lines. The location of each of these lines on the Pmod header are shown in the
table below.

Pinout Description Table

Pin Signal Description
1 ~CS Chip Select
2 NC Not Connected
3 SDO Master-In-Slave-Out
4 SCK Serial Clock
5 GND Power Supply Ground
6 VCC Power Supply (3.3V/5V)
Table 1 Connector J1- Pin Descriptions as labeled on the Pmod

The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin
low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK
to be between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on
the subsequent rising edge of SCLK, consist of three leading zeroes, the eight bits of information with the MSB
first, and four trailing zeroes.

Any external power applied to the PmodALS must be within 2.7V and 5.25V; however, it is recommended that
Pmod is operated at 3.3V.

Physical Dimensions
The pins on the pin header are spaced 100 mil apart. The PCB is 0.8 inches long on the sides parallel to the pins
on the pin header and 0.8 inches long on the sides perpendicular to the pin header.
Additional Information
The schematics of the PmodALS are available here. Additional information about the ADC including
communication modes and specific timings of the chip can be found by checking out its datasheet here. Similarly,
the datasheet for the ambient light sensor can be found here.

More specific information about how to use the PmodALS can be found by checking out our user guide. Example
code demonstrating how to get information from the PmodALS can be found here.

If you have any questions or comments about the PmodALS, feel free to post them under the appropriate section
(“Add-on Boards”) of the Digilent Forum.

The ADC081S021 operates with a single supply that can range from 2.7 V to 5.25 V. Normal power
consumption using a 3.6-V or 5.25-V supply is 1.3 mW and 7.7 mW, respectively. The power-down
feature reduces the power consumption to as low as 2.6 µW using a 5.25-V supply.

Electrical Characteristics (continued)

Typical values correspond to TA = 25°C, and minimum and maximum limits apply over –40°C to 85°C operating
temperature range (unless otherwise noted). VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50
ksps to 200 ksps, and CL = 15 pF (unless otherwise noted).(1)

Feature Description
The serial interface timing diagram for the ADC is shown in Timing Requirements. CS is chip select, which
initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the
conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is
found as a serial data stream.
Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK are labelled with reference to the falling edge of CS; for example,
the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low. At the fall of CS,
the SDATA pin comes out of TRI-STATE and the converter moves from track mode to hold mode. The input
signal is sampled and held for conversion on the falling edge of CS. The converter moves from hold mode to
track mode on the 13th rising edge of SCLK (see Timing Requirements). It is at this point that the interval for the
TACQ specification begins. At least 350 ns must pass between the 13th rising edge of SCLK and the next falling
edge of CS. The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising
edge of CS, whichever occurs first. After a conversion is completed, the quiet time (tQUIET) must
be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read
a complete sample from the ADC. The sample bits (including leading or trailing zeroes) are clocked out on falling
edges of SCLK, and are intended to be clocked in by a receiver on subsequent rising edges of SCLK. The ADC
produces three leading zero bits on SDATA, followed by eight data bits, most significant first. After the data bits,
the ADC clocks out four trailing zeros. If CS goes low before the rising edge of SCLK, an additional (fourth) zero
bit may be captured by the next falling edge of SCLK.

Determining Throughput
Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one
conversion and the start of another. At the maximum specified SCLK frequency, the maximum ensured
throughput is obtained by using a 20 SCLK frame. As shown in Timing Requirements, the minimum allowed
time between CS falling edges is determined by:
1. 12.5 SCLKs for Hold mode.
2. The larger of two quantities: either the minimum required time for Track mode (tACQ) or 2.5 SCLKs to finish
reading the result.

Código VHDL
------------------------------------------------------------------------------------------
-- PmodALS (Ambient Light Sensor)
-- SPI CONTROLLER

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SPI_ctrl_ALS is

generic(
N : integer := 8; -- number of bit to serialize
MAX : integer := 333_333 -- number of us to sample
);
port (
--FPGA clock and button
clk : in std_logic; -- 50MHz
rst : in std_logic; -- reset
--PmodALS
CS : out std_logic; -- Pmod chip selec
SDO : in std_logic; -- Pmod Serial Data Output
SCK : out std_logic; -- Pmod Serial Clock
-- led output
data : out std_logic_vector(N-1 downto 0):=x"00"; -- received data
-- Display "abcdefgP"
DISPLAY: out STD_LOGIC_VECTOR(7 DOWNTO 0); -- segments
AN: out STD_LOGIC_VECTOR(3 DOWNTO 0):="0111" -- ánodes
);

end SPI_ctrl_ALS;

architecture behav of SPI_ctrl_ALS is

--Declaración de señales para SPI

signal clkdiv : std_logic; -- divisor
signal counter : integer range 0 to MAX:=0; -- control counter
signal cnt : std_logic_vector(4 downto 0); -- divisor counter
signal tempo : std_logic_vector(0 to 15):=x"0000"; -- save data

--Declaración de señales de la asignación de U-D-C

signal P: std_logic_vector (9 DOWNTO 0); -- asign UNI,DEC,CEN
signal UNI,DEC,CEN: std_logic_vector (3 DOWNTO 0); -- digits

-- Declaración de señales de la multiplexación y asignación de U-D-C-UM al display

signal SEL: std_logic_vector (1 downto 0):="00"; -- selector de barrido
signal D: std_logic_vector (3 downto 0); -- sirve para almacenar los valores del display

-- Declaración de señales de los divisores

signal contadors: integer range 1 to 6250:=1; -- pulso1 de 0.25ms (pro. divisor ánodos)
-- para la nexys 2 6250, si se usa la nexys 3 cambiar a 12500
signal SAL_250us: std_logic; --

begin

-----------------------------------------------------
div : process(rst,clk,clkdiv,counter)
begin
-- divisor 1MHz (1us)
if(rst='1') then clkdiv <= '0';
elsif(rising_edge(clk)) then
if cnt = "11000" then cnt <= "00000"; --24
clkdiv <= not clkdiv;
else cnt <= cnt + '1';
end if;
end if;
SCK <= clkdiv;
end process div;

-----------------------------------------------------
cnter : process(rst,counter,clkdiv)
begin
-- divisor 1MHz (1us)
if(rst='1' or counter = MAX) then counter <= 0;
elsif(rising_edge(clkdiv)) then counter <= counter + 1 ;
end if;
end process cnter;

-----------------------------------------------------
receive : process(clkdiv,counter,tempo,SDO,rst)
begin
--
if(rst='1') then tempo <= (others => '0');
elsif(rising_edge(clkdiv)) then
case counter is
when 0 => CS <= '1';
when 1 => CS <= '1';
when 2 => CS <= '0';
when 3 => tempo(0) <= SDO; --0
when 4 => tempo(1) <= SDO; --0
when 5 => tempo(2) <= SDO; --0
when 6 => tempo(3) <= SDO; --DB7
when 7 => tempo(4) <= SDO; --DB6
when 8 => tempo(5) <= SDO; --DB5
when 9 => tempo(6) <= SDO; --DB4
when 10 => tempo(7) <= SDO; --DB3
when 11 => tempo(8) <= SDO; --DB2
when 12 => tempo(9) <= SDO; --DB1
when 13 => tempo(10) <= SDO; --DB0
when 14 => tempo(11) <= SDO; --0
when 15 => tempo(12) <= SDO; --0
when 16 => tempo(13) <= SDO; --0
when 17 => tempo(14) <= SDO; --0
when 18 => tempo(15) <= SDO; --tri state
when 19 => CS <= '1'; --
when others => CS <= '1'; --
end case;
end if;
data <= tempo (3 to 10);
end process receive;

-----------CONVERTIR DE BIN A BCD------------------

-- Este proceso contiene un algoritmo recorre y suma 3 para convertir el número binario tempo (3 to 10)
-- a bcd, que se manda a los displays.
-- El algoritmo consiste en desplazar (shift) el vector inicial (en binario) el número de veces
-- según sea el número de bits, y cuando alguno de los bloques de U-D-C sea igual o mayor a 5
-- (por eso el >4) se le debe sumar 3 a ese bloque, después se continúa desplazando hasta
-- que otro (o el mismo) bloque cumpla con esa condición y se le sumen 3.
-- Inicialmente se rota 3 veces porque es el número mínimo de bits que debe tener para que
-- sea igual o mayor a 5.
-- Finalmente se asigna a otro vector, el vector ya convertido, que cuenta con 4 bloques para
-- las 4 cifras de 4 bits cada una.
PROCESS(tempo(3 to 10))
VARIABLE C_D_U:STD_LOGIC_VECTOR(17 DOWNTO 0);
--18 bits para separar las Centenas-Decenas-Unidades
BEGIN
--ciclo de inicialización
FOR I IN 0 TO 17 LOOP --
C_D_U(I):='0'; -- se inicializa con 0
END LOOP;

C_D_U(7 DOWNTO 0):=tempo (3 to 10); --tempo de 8 bits

-- C_D_U(10 DOWNTO 3):=CONT(7 downto 0); --contador de 8 bits, carga desde el shift3

--ciclo de asignación UM-C-D-U

FOR I IN 0 TO 7 LOOP
-- FOR I IN 0 TO 4 LOOP -- si carga desde shift3 solo hace 5 veces el ciclo shift add

-- los siguientes condicionantes comparan (>=5) y suman 3

IF C_D_U(11 DOWNTO 8) > 4 THEN -- U

C_D_U(11 DOWNTO 8):= C_D_U(11 DOWNTO 8)+3;
END IF;

IF C_D_U(15 DOWNTO 12) > 4 THEN -- D

C_D_U(15 DOWNTO 12):= C_D_U(15 DOWNTO 12)+3;
END IF;

IF C_D_U(17 DOWNTO 16) > 4 THEN -- C

C_D_U(17 DOWNTO 16):= C_D_U(17 DOWNTO 16)+3;
END IF;

-- realiza el corrimiento
C_D_U(17 DOWNTO 1):= C_D_U(16 DOWNTO 0);
END LOOP;

P<=C_D_U(17 DOWNTO 8); -- guarda en P y en seguida se separan UM-C-D-U

END PROCESS;

--UNIDADES
UNI<=P(3 DOWNTO 0);
--DECENAS
DEC<=P(7 DOWNTO 4);
--CENTENAS
CEN<="00"&P(9 DOWNTO 8);

-------------------DIVISOR ÁNODOS-------------------
process (CLK) begin
if rising_edge(CLK) then
if (contadors = 6250) then --cuenta 0.125ms (50MHz=6250)
-- if (contadors = 12500) then --cuenta 0.125ms (100MHz=12500)
SAL_250us <= NOT(SAL_250us); --genera un barrido de 0.25ms
contadors <= 1;
else
contadors <= contadors+1;
end if;
end if;
end process; -- fin del proceso Divisor Ánodos

--------------------MULTIPLEXOR---------------------
PROCESS(SAL_250us, sel, UNI, DEC,CEN)
BEGIN
IF SAL_250us'EVENT and SAL_250us='1' THEN SEL <= SEL+'1';
CASE(SEL) IS
when "00" => AN <="0111"; D <= UNI; -- UNIDADES
when "01" => AN <="1011"; D <= DEC; -- DECENAS
when "10" => AN <="1101"; D <= CEN; -- CENTENAS
-- when "11" => AN <="1111"; --D <= MIL; -- UNIDAD DE MILLAR
when OTHERS=>AN <="1111"; --D <= MIL; -- UNIDAD DE MILLAR
END CASE;
end if;
END PROCESS; -- fin del proceso Multiplexor

--------------------DISPLAY---------------------
PROCESS(D)
Begin
case(D) is -- abcdefgP
WHEN "0000" => DISPLAY <= "00000011"; --0
WHEN "0001" => DISPLAY <= "10011111"; --1
WHEN "0010" => DISPLAY <= "00100101"; --2
WHEN "0011" => DISPLAY <= "00001101"; --3
WHEN "0100" => DISPLAY <= "10011001"; --4
WHEN "0101" => DISPLAY <= "01001001"; --5
WHEN "0110" => DISPLAY <= "01000001"; --6
WHEN "0111" => DISPLAY <= "00011111"; --7
WHEN "1000" => DISPLAY <= "00000001"; --8
WHEN "1001" => DISPLAY <= "00001001"; --9
WHEN OTHERS => DISPLAY <= "11111111"; --apagado
END CASE;
END PROCESS; -- fin del proceso Display

------------------------------------------------

end Behavioral; -- fin de la arquitectura

Código UCF
// Archivo de restricciones de usuario (UCF) Nexys 2//

//CLK reloj 50MHz

NET "CLK" LOC = "B8";

//reset
NET "RST" LOC = "H13"; // btn3 RST

#//la nexys 2 habilita LD7 y LD6 pero al invertir el orden se corrige

NET "DATA<7>" LOC = "J14"; // LD0
NET "DATA<6>" LOC = "J15"; // LD1
NET "DATA<5>" LOC = "K15"; // LD2
NET "DATA<4>" LOC = "K14"; // LD3
NET "DATA<3>" LOC = "E17"; // LD4
NET "DATA<2>" LOC = "P15"; // LD5
NET "DATA<1>" LOC = "F4"; // LD6
NET "DATA<0>" LOC = "R4"; // LD7

// Pmod ALS en JA
NET "CS" LOC = "L15"; // JA1
#NET "NC" LOC = "K12"; // JA2
NET "SDO" LOC = "L17"; // JA3
NET "SCK" LOC = "M15"; // JA4

#JA1: L15 JB1: M13 JC1: G15 JD1: J13

#JA2: K12 JB2: R18 JC2: J16 JD2: M18
#JA3: L17 JB3: R15 JC3: G13 JD3: N18
#JA4: M15 JB4: T17 JC4: H16 JD4: P18
#JA7: K13 JB7: P17 JC7: H15 JD7: K14 = LD3
#JA8: L16 JB8: R16 JC8: F14 JD8: K15 = LD3
#JA9: M14 JB9: T18 JC9: G16 JD9: J15 = LD3
#JA10: M16 JB10: U18 JC10: J12 JD10: J14 = LD3

//DISPLAYS
NET "DISPLAY(7)" LOC = "L18"; // a
NET "DISPLAY(6)" LOC = "F18"; // b
NET "DISPLAY(5)" LOC = "D17"; // c
NET "DISPLAY(4)" LOC = "D16"; // d
NET "DISPLAY(3)" LOC = "G14"; // e
NET "DISPLAY(2)" LOC = "J17"; // f
NET "DISPLAY(1)" LOC = "H14"; // g
NET "DISPLAY(0)" LOC = "C17"; // P
//ANODOS
NET "AN(3)" LOC = "F17"; // AN0
NET "AN(2)" LOC = "H17"; // AN1
NET "AN(1)" LOC = "C18"; // AN2
NET "AN(0)" LOC = "F15"; // AN3

References.

PmodALS, consultado en febrero-2018, disponible en:

https://reference.digilentinc.com/reference/pmod/pmodals/reference-manual
https://store.digilentinc.com/pmod-als-ambient-light-sensor/

ADC081S021 Single-Channel, 50-ksps to 200-ksps, 8-Bit A/D Converter, consultado en febrero-2018, disponible
en: http://www.ti.com/lit/ds/symlink/adc081s021.pdf

Design and implementation (in VHDL) of a VGA Display and Light Sensor to run on the Nexys4DDR board
Report and Signoff due Week 6 (October 4), ECE 574: Modeling and synthesis of digital systems using Verilog
and VHDL Fall Semester 2017, consultado en febrero-2018, disponible en:
http://artsdocbox.com/Television/70952295-Design-and-implementation-in-vhdl-of-a-vga-display-and-light-
sensor-to-run-on-the-nexys4ddr-board-report-and-signoff-due-week-6-october-4.html