Winter Semester 2019

ECE 6025 Low Power IC Design

Digital Assignment 1

PROBLEM I:

a) Inverter Design:

Determine the appropriate PMOS to NMOS width ratio of a CMOS inverter by simulating it
with CMOS 90 nm technology node with a minimum width and gate length of NMOS FET such
that its switching threshold is half of the input voltage. (Use a supply voltage of 1.5V)

b) Short circuit power Vs gate loading:

Load the inverter with the following capacitors

i)10fF

ii)100fF

iii)200ff

iv)400ff

v)500fF

and plot output voltage and power in each case.

c) Conclusion

Compute the average power and peak power in each case and analyze the relation between

Load capacitance, dynamic power and short circuit power.

PROBLEM II:

a) AOI gate:

Draw a two level static CMOS gate which implements the AOI function 𝑌 = 𝐴(𝐵 + 𝐶 + 𝐷)

b)Transition probability of AOI gate: Write down the truth table for the AOI gate for Y .
Determine the 0 – 1 transition probabilities of the output, by assuming the inputs are
independent and equally distributed.

c)AOI gates Vs basic gates:

Draw the simplest possible implementation of the logic function Y using 2-input basic gates
(NOR,OR, NAND, AND, XOR).

Assuming the inputs are independent and their probabilities are 0.5, derive the transition
probability for the outputs and any internal nodes of the 2-input gate implementation of function
Y.

d) Conclusion:

Which implementation of function Y is more efficient?

Support your answer by simulating both in CMOS 90nm technology node. (Use a supply voltage
of 1.5V).
Rubrics for Evaluation of Digital Assignment 1:

Indicator Max. Fair Better Good Excellent

Marks 0 – 40% 41 – 60% 61 – 80% 81 – 100%
Inverter design and Only one of Two of the All three Satisfied all the
power ananlysis the indicators indicators indicators indicators and
[1] Symmetric inverter is mentioned is completed completed demonstrated
designed and DC analysis 5 completed satisfactorily satisfactorily the effect of
is done and VI satisfactorily capacitance on
characteristics are short circuit
plotted power
[2] Transient analysis is
done with given
capacitor values and
time vs power curves are
plotted
[3] Inference of
capacitance effect on
power consumption

Design of an efficient Only one of Two of the All three All four
AOI gate the indicators indicators indicators indicators
[1] Design of AOI gate in is completed completed completed described
two level CMOS logic. 5 satisfactorily satisfactorily satisfactorily satisfactorily
Calculating its transition
probability
[2]Development of AOI
gate with basic gates
[3] calculation of
transition probability of
developed structure with
probability propagation
algorithm
[4] Identifying which
deign is power efficient
and mention the factors
responsible for it.