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Contents
I Introduction 2
V Conclusion 11
References 11
Biographies 11
Eng. Bruno Taranto Alvim . . . . . . . . . . . . . . 11
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RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 2
Fig. 1. Standard Negative Feedback Control System Model. A. Phase-Locked Loop (PLL) Operation
Delving much further within the circuit of Figure 3, which
The usual equations for a negative-feedback system apply: comprises a common single-loop PLL synthesizer: A low-
frequency crystal oscillator, the reference oscillator, feeds the
highly stable frequency of fosc into the R − divider, which
This paper is a final project of RF PLL Synthesizer course of the RF decreases fosc to the same frequency as the fCOM that is
Engineering Certification of UCSD - University of California San Diego
(Extension). Is given by Mr. Moazzam, Reza, RF Systems Architect, Mixed coming out of the adjustable N − divider. This new fREF
Signal. Bruno have Bachelor’s Degree in Electrical Engineering. frequency out of the R−divider is then inserted into the P F D
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 3
(phase-frequency detector), which compares the phase of the The fundamental frequency of oscillation, fosc , is easy to
R−divider0 s fREF signal to that of the N −divider0 s fCOM calculate once the delay, τ is know.
signal. The N −divider receives its own input frequency from
the V CO0 s output as fout , and then lowers fout’s frequency
to a value of fCOM , which must be exactly equal to the 1
fosc = . (4)
R − divider0 s fREF output. As the P F D is comparing the τ
two frequencies of fCOM and fREF at its input from the N −
and R − dividers to see if they are of the same phase, it will
produce a rectified DC correction voltage, Verror , at its output
port, which is then placed into the PLL loop filter if these two
fCOM and fREF frequencies differ. This lowpass filter almost
completely eliminates any AC variations and noise products
emanating from the PFD’s output port, and places the now
nearly pure DC correction voltage (VCN T RL ) directly into
the VCO’s frequency control input. The VCO immediately
generates a variable and controllable output frequency that is
as stable as the reference oscillator’s fosc . Fig. 5. A Typical Crystal Oscillator Diagram.
Fig. 9. XOR Gate as a PFD. The filter then converts this charge-pump current output
into a DC control voltage for the VCO’s input control port,
The PLL’s phase-frequency detector detects a change in VCN T RL .
phase between fCOM and fREF . It does this by lining up A charge-pump’s output is connected to the simple loop-
the rising edges of fCOM and fREF , and then outputs control filter of Figure 11 to demonstrate charge-pump/loop-filter
signals to the charge pump to tell it to sink or source current action: As soon as the PFD senses that fREF and fCOM are
in or out of the low-pass loop filter to keep the PLL locked. not perfectly equal, a phase error is detected and the PFD
The charge pump outputs a single amplitude, but changeable sends a voltage command to the charge-pump circuit to turn
duty cycle, current pulse which the loop filter converts into on Iup , which begins to charge C1 through R1. This causes
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 5
Fig. 12. The Waveform from the Charge-Pump, and the Output Waveform
from Loop-Filter.
In general, it is ideal to implement the loop-filter with just designing oscillators. JFETS have low i/f noise but are used
resistors and capacitors for the reasons of cost and noise. at lower frequency range.
However, in some situations, there may be reasons to use an
active device such as an op-amp. The most common reason III. E FFECTS OF L OOP BANDWIDTH
for this is when the charge pump cannot put out a high enough Based on the VCO noise characteristics and incoming ref-
voltage. erence phase-noise the PLL loop bandwidth can be optimized
The loop-filter is a key performance of the PLL system to produce lower phase noise at the output clocks. The closed-
and has a lot of degrees of flexibility for one to design. The loop transfer function from the input of the phase detector to
loop-filter can have different orders; this book assumes that it the VCO output is determined by the N-divider, VCO gain,
can be of order two, three or four. There is no one loop-filter charge-pump gain and the loop-filter. This is a low-pass func-
that is right for every application as it involves performance tion with a cutoff frequency called the loopbandwidth(BW ).
trade-offs. Later chapters will cover the characteristics of the The choice of a loop bandwidth is the most critical design
loop-filter in much greater depth. parameter and has a significant impact on phase-noise, spurs,
4) Voltage-Controlled Oscillator (VCO): In many wireless lock time, jitter, magnitude and the switching speed of a
applications it is necessary to vary the frequency of the local PLL. In fact, it is practically nonsense to talk about spurs
oscillator. This requirement occurs in AM and FM broadcast or lock time without knowing the loop bandwidth. Wider
receivers, and multichannel telecommunications systems such loop bandwidths give better lock times, but spurs that are
as cellular telephones and wireless local area networks. Be- not crosstalk dominated will be increased. Inside the loop
cause the resonant frequency of an oscillator is controlled bandwidth, the PLL phase-noise is passed, but the VCO
by an LC network, changing the frequency os an oscillator phase-noise is attenuated. At the offset frequency where the
requires changing either the inductance or capacitance, and it PLL and VCO phase noise cross is a good starting point
is usually easer and cheaper to use voltage-controlled capac- for minimizing the jitter, but ir makes sense to adjust the
itors, such varactors. A varactor is a diode whose junction loop bandwidth upwards or downwards depending on spur
capacitance may be controlled by changing the DC reverse and lock-time requirements. The maximum loop bandwidth is
bias applied to the diode. The resulting configuration is called typically limited to one-tenth of the phase detector frequency.
a V oltage − ControlledOscillator (VCO). It can also be limited by the VCO input capacitance or by
Generally a varactor is used in either series or parallel with loop filter component values being forced. The minimum
a capacitor in the feedback network to provide a fine-tuning loop bandwidth approaches zero Hz and is limited by the
range about the quiescent resonant frequency. In addition, loop-filter capacitors becoming unrealistically large. The max-
DC blocking capacitors and/or RF chocked must be used to imum loop bandwidth can be limited by either the VCO
provide a reverse bias voltage without detuning or shorting the input capacitance, forced loop components that one designs
RF circuit. around, or discrete sampling effects of the phase detector. In
general, higher loop bandwidth is recommended if the input
clock reference is clean. Crystals, oscillators and TCXOs are
typically considered clean clock sources. A lower PLL loop
bandwidth is typically recommended if the input clock is
noisy and jitter cleaning is required. Clocks traveling through
backplanes, clocks from low performance PLLs, or recovered
clocks from SERDES or FPGAs may be considered noisy
clocks and frequently require filtering to remove excessive
noise. The PLL output directly depends on input clock phase
noise and PLL in-band phase up to the loop bandwidth,
after that VCO phase-noise and buffer’s noise floor dominate.
Setting the loop bandwidth appropriately with respect to the
Fig. 15. A Varactor-Tuned Voltage-Controlled Transistor Oscillator Circuit. input phase noise is always complicated. The phase noise of
the VCO gets noisier close to carrier frequency. Selecting a
The common types of VCO’s are Colpitts, Clapp and lower loop bandwidth means that overall the PLL output is
Harley. The thing that makes them different is how the output more dependent on VCO phase noise closer to the carrier
of amplifying device is applied to the thank circuit. frequency. Therefore, knowing the input clock phase noise
Important parameters of VCO are operating frequency, performance is required to figure out the right loop settings.
tuning range, phase noise, spurious output, tendency to oscil- Along with loop bandwidth value, Phase Margin is important
late at undesired frequency, temperature performance, power for PLL stability. It is typically recommended to keep the
supply sensitivity, frequency drift, output power flatness and phase margin value between 50 degrees to 80 degrees. Jitter
mechanical vibration resistance. Tuning Range and phase noise peaking should also be considered. Too much peaking around
are the conflicting requirements. Most of the structures for the loop bandwidth will degrade the PLL performance.
oscillators can be changed to VCO by replacing the frequency s
determining capacitor with a varactor diode. The transistor K0 ∗ Kvco
ωn = . (7)
noise especially flicker noise is an important characteristic in N (C1 + C2 )
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 7
A. Phase Noise 1. So as not to further degrade the phase noise that is gener-
The choice of loop bandwidth has a significant impact in ated within the PLL chip itself, use only an exceptionally clean
the phase-noise. For all noise not coming from the VCO, reference oscillator, since the phase noise of the reference will
this transfer function multiplies up the phase-noise within the be amplified by 20log( N R ) within the loop filter’s bandwidth.
loop bandwidth and then suppresses then the filter attenuation 2. Use a VCO designed for low noise, since this oscillator
begins to kick it after the loop bandwidth. For the VCO, the is the major wideband phase-noise contributor. (When a VCO
noise is suppressed below the loop bandwidth frequency and is placed within the loop of a PLL, close in VCO phase
unshaped above the loop bandwidth frequency. noise will be attenuated as compared to its free-running state,
but the VCO frequencies that are farther away from the loop
bandwidth will actually be increased in amplitude.)
3. Keep the number of the N-divider divisions as low as
possible, as the higher the divide ratio, the higher will be the
phase noise (the phase detector noise will equal 20log10(N ),
in dB). Thus, we would want to decrease the frequency of
the VCO, while increasing fCOM , in order to lower this noise
(phase noise is improved by a high fCOM ). But this would
also limit the channel spacing, since channel width equals
fCOM . A fractional-N PLL can overcome this problem. (We
can further improve phase noise, at the expense of increased
Fig. 16. PLL Noise Transfer Function. cost and complexity, by utilizing multiple PLL loops to reduce
the division ratio.)
In addition to the desired signal, a PLL will also produce 4. Make the loop filter narrow, as narrow PLL loop band-
undesired noise. This noise can be thought of as noise on the widths can provide decreased phase noise and lower spurious
phase of the output and is therefore called phase − noise. In outputs. However, if the loop bandwidth is too narrow, the
the frequency domain, this is more commonly thought of as VCO’s phase noise will begin to degrade close-in to the fout
the density of the noise power relative to the carrier power carrier, as there will now be more of the VCO itself that
and measured in dBc/Hz. is not within the loop bandwidth. Yet, if the loop filter is
Since PLL’s are used extensively as local-oscillators in designed to be too wide, then the PLL chip’s own internal
digital radios, and LO phase-noise degrades a communications noise bandwidth will be extended further outward from the
system’s SNR and ACPR (adjacent channel power rejection), fout carrier, making for a less than optimal phase-noise profile
we see why such noise suppression is extremely critical. The for the synthesizer. So, the perfect loop-filter bandwidth is
major noise sources within a PLL are the VCO’s own phase designed to be exactly at the frequency where the PLL chip’s
noise, the reference oscillator noise, and the phase-frequency own internally generated noise amplitude equals the noise
detector noise. Generally, close-in phase noise (i.e., noise amplitude of a free running VCO. This will supply us with
within the bandwidth of the loop filter) is dictated by the the best of both worlds: the lowest close-in and the lowest
phase-frequency detector and reference oscillator, while farther wideband phase-noise characteristics for a PLL.
out the major phase-noise contributor is the VCO (Fig. 5.8). 5. Confirm that the loop filter’s resistors are not of too high
a value, since due to random electron motion all resistors will
generate white noise. This noise power can be considered as an
in-series noise generator, with the higher the resistance value
the higher will be the noise produced.
6. If possible, avoid ceramic loop-filter capacitors because
of their piezoelectric effects and microphonics, which can
sometimes create noise transients. Also, never use carbon
composition or carbon film resistors in a PLL loop filter due
to their extreme random-noise-producing qualities; use only
thin or thick metal film types.
7. Try increasing the VCO’s output feedback signal into
the N-divider port, if it is too low in amplitude, since a small
feedback level back into the PLL’s IC can increase noise levels.
8. Low reference oscillator drive levels into the PLL’s R-
divider will increase noise. Make sure the reference oscillator
is inputting the recommended R-divider input signal ampli-
Fig. 17. The major Noise contributors and output Spectrum of a PLL tude.
Synthesizer, narrow Frequency sweep. 9. Confirm that the Phase-Locked Loop (PLL) or VCO
power supply is properly filtered by decoupling networks
Steps to minimize the phase-noise Phase-Locked Loop at both low-frequency AC and at high-frequency RF. Also,
(PLL): resistively isolate the Phase-Locked Loop (PLL) IC’s power
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 8
supply line from the VCO’s power supply line by employing C. Spurious
a low-value series resistor in each line of approximately 20Ω. Spurs can be thought as noise that is concentrated at a
10. Make sure that the VCO’s loop filter and the VCO’s specific offset from the carrier. These are typically measured in
VCN T RL tuning line are not too exposed to EMI or digital dBc with a spectrum analyzer. There are many kinds of spurs
noise, as well as to any pulse coupling from the charge pump’s and they can have multiple causes, but most of them occur
output. Keep the VCO tuning line short, and away from at very predictable offsets. Spurs have a tendency to occur
noisy circuits of any kind. These issues can be aggravated at multiples of the phase detector frequency, input reference
by excessively cramped PCB part’s placement or a generally frequency, channel spacing and fraction of channel spacing.
poor PCB layout.
B. Jitter
Phase noise generation in oscillators/VCOs has been a
focus of important research efforts. It is still an issue despite
significant gains in practical experience and modern CAD
tools for design. In the design of VCOs, minimizing phase
noise is the prime task. This has been accomplished using
empirical rules or numerical optimizations, which are often
held as trade secrets by many manufacturers. The ability to
achieve optimum phase noise performance is paramount in
most RF designs, and the continued improvement of phase
noise in oscillators is required for efficient use of the frequency
spectrum. The degree to which an oscillator generates constant
frequency throughout a specified period of time is defined as Fig. 20. Spurs as seen on a Spectrum Analyzer.
the frequency stability of the oscillator. Frequency instability
is due to the presence of noise in the oscillator circuit that Reference spurs are spurious PLL outputs that form outside
effectively modulates the signal, causing a change in the of our desired passband. These spurs can be found on each side
frequency spectrum commonly known as phase noise. Phase of the VCO’s carrier, at a frequency offset that is equal to the
noise and timing jitter are measures of uncertainty in the output PLL’s channel spacing, and are created by PLL charge-pump
of an oscillator. Phase noise defines the frequency domain leakage and mismatch. Spurs must be reduced in amplitude
uncertainty of an oscillator, and timing jitter is a measure of as much as possible to prevent interference into the pass-
oscillator uncertainty in the time domain. band from a strong adjacent channel mixing with these spurs,
Figures 18 and 19 illustrate the frequency spectrum of and creating in-band interference within the receiver’s IF
ideal and real oscillators, as well as the frequency fluctuation frequency. (Keeping reference spurs low in amplitude will
corresponding to jitter in the time domain, which is random minimize reciprocal mixing of these LO spurs with any large
perturbation of the zero crossing of a periodic signal. amplitude RF interferers that are within the receiver’s first
mixer stage, and which can overwhelm the low-amplitude
desired signal within the IF. This could seriously decrease a
receiver system’s sensitivity.)
The spurs are produced, as stated, by the charge pump’s
own output pulses, which are being generated even when the
Phase-Locked Loop (PLL) is in perfect lock. Indeed, while
both a charge pump’s Iup and Idwn current pulses are normally
designed to source and sink equal values of current, this is not
really possible. There will always be a slight current offset, and
Fig. 18. Frequency Spectrum of Ideal and Real Oscillators.
any mismatch between Iup and Idwn currents will create these
reference spurs. The pulses will then modulate the VCO’s
DC control voltage VCN T RL at a frequency that is exactly
at fCOM , creating reference spurs at fout that are at the exact
same frequency of fCOM and its harmonics, and on both sides
of the PLL’s carrier fout . Therefore, a value of fCOM of 100
kHz will give us reference spurs at +100 kHz and −100 kHz,
and at integer multiples thereof, away from fout .
To make sure that the reference spurs are as low as possible
in divided-by-N PLLs, we should select a synthesizer chip
that has low charge-pump-leakage characteristics, and that
Fig. 19. Jitter in the Time Domain Related to Phase Noise in the Frequency has well-matched charge-pump currents. However, the only
Domain. remedial action we could easily take with an already built
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 9
PLL would be to improve the filtering of the close-in spurs of magnitude. The minimum loop bandwidth approaches zero
by tightening up the loop filter’s bandwidth, as well as making Hz and is limited by the filter capacitors becoming large. The
sure that the VCC power supplies are extremely well filtered. maximum loop bandwidth can be limited by either the VCO
Any assorted spurs that are over and above the typical fCOM input capacitance, forced loop components that one designs
reference spurs can sometimes be seen in the output of some around, or discrete sampling effects of the phase detector. This
synthesizers at assorted frequencies. These irregular spurs can discrete effects tend to become an issue around one-tenth of
be caused by conducted or radiated coupling of noise or RF the phase detector frequency and result in instability around
interference into the PLL. The cure is the standard one, and can one-third of the phase detector frequency. This leaves a very
significantly reduce these atypical spurs to low levels: effective wide range of choices for the loop bandwidth and it has a very
decoupling of all PLL voltage supplies, as well as proper EMI profound impact in lock-time, jitter, phase noise and spurs.
board layout procedures. There is no loop bandwidth that is optimal for all performance
metrics, but there is one that is optimal for jitter, BWJIT ,
D. Lock-Time which serves as a good starting point for discussing the trade-
offs in choosing the loop bandwidth. BWJIT can be found
PLL lock time can be shortened by raising the fCOM as the offset frequency where the VCO and PLL (and input
frequency, since fCOM controls the charge pump’s pulse reference) noise cross as shown in the following Figure .
frequency, and will also permit an increase in the loop-
filter bandwidth. While increasing the loop bandwidth will
decrease lock-time, it will also increase phase-noise and spur
amplitudes, as well as possibly creating loop instability if
widened by more than fCOM 5 . However, the lock time can be
considerably sped up by never permitting the VCO’s tuning
voltage to be any closer than 1 V from either supply voltage
rail of the charge pump. This particular effect on lock time is
caused by saturation of the charge pump at its supply voltage
extremes, and can be circumvented by:
2. Using a higher charge-pump voltage supply; Fig. 21. Optimal Jitter Bandwidth.
11
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 12
List of Figures
1 Standard Negative Feedback Control System
Model. . . . . . . . . . . . . . . . . . . . . . . 2
2 Typical PLL Receiver. . . . . . . . . . . . . . 2
3 Phase-Locked Loop (PLL) Synthesizer. . . . . 3
4 Equivalent Circuit of a Crystal. . . . . . . . . 3
5 A Typical Crystal Oscillator Diagram. . . . . . 3
6 Input Reactance of a Crystal Resonator. . . . . 3
7 Pierce Crystal Oscillator Circuit. . . . . . . . . 4
8 PFD and its Input/Output Characteristic. . . . 4
9 XOR Gate as a PFD. . . . . . . . . . . . . . . 4
10 A Charge Pump PLL Chip. . . . . . . . . . . 4
11 PFD, Charge-Pump and Loop-Filter. . . . . . . 5
12 The Waveform from the Charge-Pump, and the
Output Waveform from Loop-Filter. . . . . . . 5
13 Typical Loop-Filter. . . . . . . . . . . . . . . . 5
14 A Third Order Loop-Filter. . . . . . . . . . . . 5
15 A Varactor-Tuned Voltage-Controlled Transis-
tor Oscillator Circuit. . . . . . . . . . . . . . . 6
16 PLL Noise Transfer Function. . . . . . . . . . 7
17 The major Noise contributors and output Spec-
trum of a PLL Synthesizer, narrow Frequency
sweep. . . . . . . . . . . . . . . . . . . . . . . 7
18 Frequency Spectrum of Ideal and Real Oscil-
lators. . . . . . . . . . . . . . . . . . . . . . . 8
19 Jitter in the Time Domain Related to Phase
Noise in the Frequency Domain. . . . . . . . . 8
20 Spurs as seen on a Spectrum Analyzer. . . . . 8
21 Optimal Jitter Bandwidth. . . . . . . . . . . . 9
22 Complete Microwave Phase-Lock Lopp (PLL)
for Wideband. . . . . . . . . . . . . . . . . . . 11