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Contents
I Introduction 2

II Phase-Locked Loop (PLL) Operation and Structure 2


II-A Phase-Locked Loop (PLL) Operation . . . . . 2
II-B Phase-Locked Loop (PLL) Structure . . . . . . 3
II-B1 Crystal Oscillator (OSC) . . . . . . . . 3
II-B2 Phase Frequency Detector (PFD) . . . 4
II-B3 Low-Pass Filter (LPF) . . . . . . . . . 5
II-B4 Voltage-Controlled Oscillator (VCO) . 6

III Effects of Loop Bandwidth 6


III-A Phase Noise . . . . . . . . . . . . . . . . . . . 7
III-B Jitter . . . . . . . . . . . . . . . . . . . . . . . 8
III-C Spurious . . . . . . . . . . . . . . . . . . . . . 8
III-D Lock-Time . . . . . . . . . . . . . . . . . . . 9

IV Loop Bandwidth Optimization 9


IV-A Numerical Loop Bandwidth Optimization . . . 10

V Conclusion 11

References 11

Biographies 11
Eng. Bruno Taranto Alvim . . . . . . . . . . . . . . 11

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RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 2

RF Phase-Locked Loop (PLL) Synthesizer Loop


Bandwidth Optimization
RF PLL Synthesizer - Electrical Engineer Bruno Taranto Alvim

Abstract—This work cover the RF Phase-Locked Loop (PLL) F orwardGain :


Synthesizer Loop Bandwidth Optimization. Chapter 1 is a
introduction about Phase-Locked Loop (PLL) operation and G(s), [s = jω = 2πf ]. (1)
structure. Chapter 2 about effects of Loop Bandwidth like Jitter,
phase noise, spurious and lock-time. Chapter 4 the benefits of LoopGain :
optimized loop bandwidth with a numerical example. Chapter 5 G(s)xH(s). (2)
our conclusions based on numerical example and the theoretical
studies. Closed − LoopGain :
Index Terms—Phase-Locked Loop Synthesizer, Loop Band- G(s)
width, Lock-Time, PLL. . (3)
1 + G(s)H(s)
In a Phase-Locked Loop (PLL), the error signal from the
I. I NTRODUCTION phase comparator is proportional to the relative phase of the
input and feedback signals. The average output of the phase

P hased-Locked Loop (PLL) Synthesizers is the most


widespread method of frequency synthesis, which is
easy to design, versatile and operate at high frequencies.
A Phase-Locked Loop (PLL) is a feedback system combining
detector will be constant when the input and feedback signals
are the same frequency. The usual equations for a negative-
feedback system apply. A PLL is a feedback system that
includes a VCO, phase detector, and low pass filter within
a voltage-controlled oscillator and a phase comparator so its loop. Its purpose is to force the VCO to replicate and track
connected that the oscillator maintains a constant phase angle the frequency and phase at the input when in lock. The PLL is
relative to a reference signal. Phase-Locked Loop can be used, a control system allowing one oscillator to track with another.
for example, to generate stable output frequency signals from It is possible to have a phase offset between input and output,
a fixed low-frequency signal, used for filtering, frequency syn- but when locked, the frequencies must exactly track.
thesis, motor-speed control, frequency modulation, demodula-
tion, signal-detection and others applications. The first Phase- II. P HASE -L OCKED L OOP (PLL) O PERATION AND
Locked Loop (PLL) were implemented in the early 1930s by S TRUCTURE
a French engineer, de Bellescize. Has an output frequency
that is exact multiple of the input reference frequency. A
Phase-Locked Loop (PLL) multiplies a reference frequency
by the value placed within a programmable frequency divider,
and then outputs stable frequency from voltage-controlled
oscillator. The Phase-Locked Loop (PLL) can be analyzed in
general as a negative-feedback system with a forward gain
term and a feedback term. A simple block diagram of a
voltage-based negative-feedback system is shown in Figure 1.

Fig. 2. Typical PLL Receiver.

Fig. 1. Standard Negative Feedback Control System Model. A. Phase-Locked Loop (PLL) Operation
Delving much further within the circuit of Figure 3, which
The usual equations for a negative-feedback system apply: comprises a common single-loop PLL synthesizer: A low-
frequency crystal oscillator, the reference oscillator, feeds the
highly stable frequency of fosc into the R − divider, which
This paper is a final project of RF PLL Synthesizer course of the RF decreases fosc to the same frequency as the fCOM that is
Engineering Certification of UCSD - University of California San Diego
(Extension). Is given by Mr. Moazzam, Reza, RF Systems Architect, Mixed coming out of the adjustable N − divider. This new fREF
Signal. Bruno have Bachelor’s Degree in Electrical Engineering. frequency out of the R−divider is then inserted into the P F D
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 3

(phase-frequency detector), which compares the phase of the The fundamental frequency of oscillation, fosc , is easy to
R−divider0 s fREF signal to that of the N −divider0 s fCOM calculate once the delay, τ is know.
signal. The N −divider receives its own input frequency from
the V CO0 s output as fout , and then lowers fout’s frequency
to a value of fCOM , which must be exactly equal to the 1
fosc = . (4)
R − divider0 s fREF output. As the P F D is comparing the τ
two frequencies of fCOM and fREF at its input from the N −
and R − dividers to see if they are of the same phase, it will
produce a rectified DC correction voltage, Verror , at its output
port, which is then placed into the PLL loop filter if these two
fCOM and fREF frequencies differ. This lowpass filter almost
completely eliminates any AC variations and noise products
emanating from the PFD’s output port, and places the now
nearly pure DC correction voltage (VCN T RL ) directly into
the VCO’s frequency control input. The VCO immediately
generates a variable and controllable output frequency that is
as stable as the reference oscillator’s fosc . Fig. 5. A Typical Crystal Oscillator Diagram.

A quartz crystal resonator consists of a small slab of quartz


mounted between two metallic plates. Mechanical oscillations
can be excited in the crystal through the piezoelectric effect.
Are used to generate source (or clock) signals where high
frequency stability at precise frequency are required.

Fig. 3. Phase-Locked Loop (PLL) Synthesizer.

Each PLL system is composed of four basic parts:


A. Crystal Oscillator (OSC);
B. Phase Frequency Detector (PFD);
C. Low-Pass Filter (LPF);
D. Voltage-Controlled Oscillator (VCO);

Fig. 6. Input Reactance of a Crystal Resonator.


B. Phase-Locked Loop (PLL) Structure
1) Crystal Oscillator (OSC): The resonant frequency on an
oscillator is determined from the condition a 180° phase shift This circuit has series and parallel resonant frequencies, ωs
occurs between the input and output of the transistor. If the and ωp , given by
resonant feedback circuit has a high Q, so that there is a very
rapid change in the phase shift with frequency, the oscillator 1
will have a good frequency stability. ωs = p . (5)
The most basic oscillator is called the ringoscillator. (LC)
Quartz crystal are useful for this purpose, especially at
frequencies below a few hundred M Hz, where LC resonator
seldom have QS greater than a few hundred. Crystal-controlled 1
ωp = q . (6)
oscillators find extensive use as stable frequency sources in
L( CC00+C
C
)
wireless systems.

They have good noise performance, but drawbacks are:


- Low frequency of operation
- Low-output power

Crystal is one of the important component of PLL frequency


Fig. 4. Equivalent Circuit of a Crystal. synthesizers.
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 4

a DC output voltage. This filtering action removes most of


the charge pump’s glitches and overshooting, instructing the
VCO to move slightly higher or slightly lower in frequency
if it has drifted or if the operator/command-signal desires a
rapid change in frequency. When the fCOM and fREF inputs
to the PFD are perfectly aligned in both frequency and phase,
then the loop is deemed fully locked. This locked condition is
very temporary due to the extremely poor frequency stability
of a VCO. During the short period of perfect lock when fCOM
and fREF are in perfect frequency and phase alignment, the
charge pump will tri-state with a high-impedance output and
with narrow (approximately 30ns wide) positive and negative
Fig. 7. Pierce Crystal Oscillator Circuit. charge-pump current pulses at a 50 − 50 duty cycle. The
outputting of pulses even when in perfect lock is done to
2) Phase Frequency Detector (PFD): The phase detector prevent dead-band behavior. The PLL dead-band is a condition
is a device that converts the differences in the two phases in which the phase-frequency detector would have no control
from the N-divider and R-divider into an output voltage. This of the loop when the PLL was very close to, or is actually
output voltage can either be applied directly to the loop filter in, lock. In other words, when there is an almost 0° phase
or converted to a current by a charge-bump. difference between fCOM and fREF . (This is so, jitter is not
A PFD is a circuit that senses two periodic inputs and created with the excessive PLL loop hysteresis). And even
produces an output whose average value is proportional to though the PFD is still outputting current pulses when fCOM
the difference between the phases of the inputs. Shown in and fREF are in perfect in-phase alignment, the charge pump
Fig. 9.1, the input/output characteristic of the PFD is ideally itself will neither charge up nor charge down the loop filter’s
a straight line, with a slope called the “gain” and denoted by capacitors, since these charge-pump pulses are comprised of
KP D . For an output voltage quantity, KP D is expressed in evenly spaced, 50 − 50 duty cycle, very narrow Iup and Idwn
V
rad . In practice, the characteristic may not be linear or even pulses. Unlike many of the old PLL detectors, all modern PLL
monotonic. chips use PFDs which will force a lock, even when the PLL
itself is drastically out of lock. The PFD does this by first
comparing, then finding the same fCOM and fREF frequency,
and only after it completes this wide frequency lock function
does it then force an almost perfect “fine tune” phase lock for
the synthesizer circuit.
Fig. 8. PFD and its Input/Output Characteristic. a) Charge Pump: Most modern PLL chips are of the
charge − pump type (Figure 10). A PLL with a charge-pump
How is the phase detector implemented? We seek a circuit permits the use of a passive filter, which is cheaper and adds
whose average output is proportional to the input phase dif- little extra noise.
ference. For example, an exclusive-OR (XOR) gate can serve
this purpose. As shown in Fig. 9.3, the XOR gate generates
pulses whose width is equal to ∆φ. In this case, the circuit
produces pulses at both the rising edge and the falling edge
of the inputs.

Fig. 10. A Charge Pump PLL Chip.

Fig. 9. XOR Gate as a PFD. The filter then converts this charge-pump current output
into a DC control voltage for the VCO’s input control port,
The PLL’s phase-frequency detector detects a change in VCN T RL .
phase between fCOM and fREF . It does this by lining up A charge-pump’s output is connected to the simple loop-
the rising edges of fCOM and fREF , and then outputs control filter of Figure 11 to demonstrate charge-pump/loop-filter
signals to the charge pump to tell it to sink or source current action: As soon as the PFD senses that fREF and fCOM are
in or out of the low-pass loop filter to keep the PLL locked. not perfectly equal, a phase error is detected and the PFD
The charge pump outputs a single amplitude, but changeable sends a voltage command to the charge-pump circuit to turn
duty cycle, current pulse which the loop filter converts into on Iup , which begins to charge C1 through R1. This causes
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 5

VCN T RL to ramp up to a value of IR1 .Iup is then ordered


by the PFD to shut off at the same time that Idwn is ordered
on, which draws the current back out of C1, through R1,
and sinks it through Idwn , causing the VCO control voltage
VCN T RL to drop to a lower value, and changing the fout
value from the VCO’s output port. (We could actually calculate
this VCN T RL value by taking the average DC current that is
pumped out of the charge-pump and multiplying it by the
loop-filter’s impedance.)

Fig. 12. The Waveform from the Charge-Pump, and the Output Waveform
from Loop-Filter.

A typical PLL’s IC charge-pump current gain setting is


adjustable. Setting a charge-pump to the maximum current
gain setting can be advantageous, since it permits a third-order
loop-filter’s resistors to be lower in value, creating less resistor
noise. The loop capacitor that is in shunt with the VCO can
also now be higher in value, which dramatically decreases the
parasitic effects of the VCO’s input capacitance (the VCO’s
input capacitance can be as high as 100pF , with the exact
input capacitance value varying over the VCO’s full tuning
range). Phase noise may also be improved for certain Phase-
Locked Loop (PLL) chip models with a higher charge-pump
current gain.
3) Low-Pass Filter (LPF): Low-Pass Filter translates the
Fig. 11. PFD, Charge-Pump and Loop-Filter.
charge-pump output current into a tuning voltage for the VCO.
The loop-filter transfer function is actually a part of the entire
closed loop PLL which also includes the N-divider value,
charge pump gain, and VCO gain. This closed loop transfer
function has a profound impact on PLL switching speed, spurs,
phase-noise and stability.
Low-voltage charge-pumps, which are used with a typi- A Loop-Filter can be implemented with resistors and ca-
cal passive loop-filter, depend largely on the charge-pump’s pacitors and a simple one is shown in the following figure:
voltage supply (and the charge-pump’s current setting) for
the best lock time, since the charge-pump gain will increase
in a linear manner with its voltage supply amplitude. Thus,
the higher the charge-pump’s supply voltage, the faster the
charge-pump output forces the loop-filter voltage to reach a
steady-state value into the VCN T RL port of the VCO, and
therefore the faster the PLL lock time. This effect is due to the
loop-filter itself (Figure 10), since as the charge-pump begins
to pulse current into the filter to force the VCO’s voltage
Fig. 13. Typical Loop-Filter.
to some specific amplitude, these pulses begin to charge,
principally, C1, creating voltage increases at the loop-filter’s The Loop−F ilterOrder is defined by the number of poles
output. However, directly between these charge-pump current in the loop-filter.
pulses, or at zero current, the charge in C1 then discharges
into R1 and C2, which decreases the voltage at the output
of the loop-filter, forming voltage charge/discharge ramps as
shown. Since C2 now has a charge, we need C10 s voltage level
to be higher than C20 s if we want significantly more current
flow into this larger value capacitor, C2. But, due to the lower
charge-pump voltage, the charging of C2 will now take longer
because of the decreased current flow to C2 caused by the
lower voltage across C1. End result: slower VCO lock time
because the charging of the loop-filter must trade minimum
charge-pump voltage amplitude for charging time. Fig. 14. A Third Order Loop-Filter.
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In general, it is ideal to implement the loop-filter with just designing oscillators. JFETS have low i/f noise but are used
resistors and capacitors for the reasons of cost and noise. at lower frequency range.
However, in some situations, there may be reasons to use an
active device such as an op-amp. The most common reason III. E FFECTS OF L OOP BANDWIDTH
for this is when the charge pump cannot put out a high enough Based on the VCO noise characteristics and incoming ref-
voltage. erence phase-noise the PLL loop bandwidth can be optimized
The loop-filter is a key performance of the PLL system to produce lower phase noise at the output clocks. The closed-
and has a lot of degrees of flexibility for one to design. The loop transfer function from the input of the phase detector to
loop-filter can have different orders; this book assumes that it the VCO output is determined by the N-divider, VCO gain,
can be of order two, three or four. There is no one loop-filter charge-pump gain and the loop-filter. This is a low-pass func-
that is right for every application as it involves performance tion with a cutoff frequency called the loopbandwidth(BW ).
trade-offs. Later chapters will cover the characteristics of the The choice of a loop bandwidth is the most critical design
loop-filter in much greater depth. parameter and has a significant impact on phase-noise, spurs,
4) Voltage-Controlled Oscillator (VCO): In many wireless lock time, jitter, magnitude and the switching speed of a
applications it is necessary to vary the frequency of the local PLL. In fact, it is practically nonsense to talk about spurs
oscillator. This requirement occurs in AM and FM broadcast or lock time without knowing the loop bandwidth. Wider
receivers, and multichannel telecommunications systems such loop bandwidths give better lock times, but spurs that are
as cellular telephones and wireless local area networks. Be- not crosstalk dominated will be increased. Inside the loop
cause the resonant frequency of an oscillator is controlled bandwidth, the PLL phase-noise is passed, but the VCO
by an LC network, changing the frequency os an oscillator phase-noise is attenuated. At the offset frequency where the
requires changing either the inductance or capacitance, and it PLL and VCO phase noise cross is a good starting point
is usually easer and cheaper to use voltage-controlled capac- for minimizing the jitter, but ir makes sense to adjust the
itors, such varactors. A varactor is a diode whose junction loop bandwidth upwards or downwards depending on spur
capacitance may be controlled by changing the DC reverse and lock-time requirements. The maximum loop bandwidth is
bias applied to the diode. The resulting configuration is called typically limited to one-tenth of the phase detector frequency.
a V oltage − ControlledOscillator (VCO). It can also be limited by the VCO input capacitance or by
Generally a varactor is used in either series or parallel with loop filter component values being forced. The minimum
a capacitor in the feedback network to provide a fine-tuning loop bandwidth approaches zero Hz and is limited by the
range about the quiescent resonant frequency. In addition, loop-filter capacitors becoming unrealistically large. The max-
DC blocking capacitors and/or RF chocked must be used to imum loop bandwidth can be limited by either the VCO
provide a reverse bias voltage without detuning or shorting the input capacitance, forced loop components that one designs
RF circuit. around, or discrete sampling effects of the phase detector. In
general, higher loop bandwidth is recommended if the input
clock reference is clean. Crystals, oscillators and TCXOs are
typically considered clean clock sources. A lower PLL loop
bandwidth is typically recommended if the input clock is
noisy and jitter cleaning is required. Clocks traveling through
backplanes, clocks from low performance PLLs, or recovered
clocks from SERDES or FPGAs may be considered noisy
clocks and frequently require filtering to remove excessive
noise. The PLL output directly depends on input clock phase
noise and PLL in-band phase up to the loop bandwidth,
after that VCO phase-noise and buffer’s noise floor dominate.
Setting the loop bandwidth appropriately with respect to the
Fig. 15. A Varactor-Tuned Voltage-Controlled Transistor Oscillator Circuit. input phase noise is always complicated. The phase noise of
the VCO gets noisier close to carrier frequency. Selecting a
The common types of VCO’s are Colpitts, Clapp and lower loop bandwidth means that overall the PLL output is
Harley. The thing that makes them different is how the output more dependent on VCO phase noise closer to the carrier
of amplifying device is applied to the thank circuit. frequency. Therefore, knowing the input clock phase noise
Important parameters of VCO are operating frequency, performance is required to figure out the right loop settings.
tuning range, phase noise, spurious output, tendency to oscil- Along with loop bandwidth value, Phase Margin is important
late at undesired frequency, temperature performance, power for PLL stability. It is typically recommended to keep the
supply sensitivity, frequency drift, output power flatness and phase margin value between 50 degrees to 80 degrees. Jitter
mechanical vibration resistance. Tuning Range and phase noise peaking should also be considered. Too much peaking around
are the conflicting requirements. Most of the structures for the loop bandwidth will degrade the PLL performance.
oscillators can be changed to VCO by replacing the frequency s
determining capacitor with a varactor diode. The transistor K0 ∗ Kvco
ωn = . (7)
noise especially flicker noise is an important characteristic in N (C1 + C2 )
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A. Phase Noise 1. So as not to further degrade the phase noise that is gener-
The choice of loop bandwidth has a significant impact in ated within the PLL chip itself, use only an exceptionally clean
the phase-noise. For all noise not coming from the VCO, reference oscillator, since the phase noise of the reference will
this transfer function multiplies up the phase-noise within the be amplified by 20log( N R ) within the loop filter’s bandwidth.
loop bandwidth and then suppresses then the filter attenuation 2. Use a VCO designed for low noise, since this oscillator
begins to kick it after the loop bandwidth. For the VCO, the is the major wideband phase-noise contributor. (When a VCO
noise is suppressed below the loop bandwidth frequency and is placed within the loop of a PLL, close in VCO phase
unshaped above the loop bandwidth frequency. noise will be attenuated as compared to its free-running state,
but the VCO frequencies that are farther away from the loop
bandwidth will actually be increased in amplitude.)
3. Keep the number of the N-divider divisions as low as
possible, as the higher the divide ratio, the higher will be the
phase noise (the phase detector noise will equal 20log10(N ),
in dB). Thus, we would want to decrease the frequency of
the VCO, while increasing fCOM , in order to lower this noise
(phase noise is improved by a high fCOM ). But this would
also limit the channel spacing, since channel width equals
fCOM . A fractional-N PLL can overcome this problem. (We
can further improve phase noise, at the expense of increased
Fig. 16. PLL Noise Transfer Function. cost and complexity, by utilizing multiple PLL loops to reduce
the division ratio.)
In addition to the desired signal, a PLL will also produce 4. Make the loop filter narrow, as narrow PLL loop band-
undesired noise. This noise can be thought of as noise on the widths can provide decreased phase noise and lower spurious
phase of the output and is therefore called phase − noise. In outputs. However, if the loop bandwidth is too narrow, the
the frequency domain, this is more commonly thought of as VCO’s phase noise will begin to degrade close-in to the fout
the density of the noise power relative to the carrier power carrier, as there will now be more of the VCO itself that
and measured in dBc/Hz. is not within the loop bandwidth. Yet, if the loop filter is
Since PLL’s are used extensively as local-oscillators in designed to be too wide, then the PLL chip’s own internal
digital radios, and LO phase-noise degrades a communications noise bandwidth will be extended further outward from the
system’s SNR and ACPR (adjacent channel power rejection), fout carrier, making for a less than optimal phase-noise profile
we see why such noise suppression is extremely critical. The for the synthesizer. So, the perfect loop-filter bandwidth is
major noise sources within a PLL are the VCO’s own phase designed to be exactly at the frequency where the PLL chip’s
noise, the reference oscillator noise, and the phase-frequency own internally generated noise amplitude equals the noise
detector noise. Generally, close-in phase noise (i.e., noise amplitude of a free running VCO. This will supply us with
within the bandwidth of the loop filter) is dictated by the the best of both worlds: the lowest close-in and the lowest
phase-frequency detector and reference oscillator, while farther wideband phase-noise characteristics for a PLL.
out the major phase-noise contributor is the VCO (Fig. 5.8). 5. Confirm that the loop filter’s resistors are not of too high
a value, since due to random electron motion all resistors will
generate white noise. This noise power can be considered as an
in-series noise generator, with the higher the resistance value
the higher will be the noise produced.
6. If possible, avoid ceramic loop-filter capacitors because
of their piezoelectric effects and microphonics, which can
sometimes create noise transients. Also, never use carbon
composition or carbon film resistors in a PLL loop filter due
to their extreme random-noise-producing qualities; use only
thin or thick metal film types.
7. Try increasing the VCO’s output feedback signal into
the N-divider port, if it is too low in amplitude, since a small
feedback level back into the PLL’s IC can increase noise levels.
8. Low reference oscillator drive levels into the PLL’s R-
divider will increase noise. Make sure the reference oscillator
is inputting the recommended R-divider input signal ampli-
Fig. 17. The major Noise contributors and output Spectrum of a PLL tude.
Synthesizer, narrow Frequency sweep. 9. Confirm that the Phase-Locked Loop (PLL) or VCO
power supply is properly filtered by decoupling networks
Steps to minimize the phase-noise Phase-Locked Loop at both low-frequency AC and at high-frequency RF. Also,
(PLL): resistively isolate the Phase-Locked Loop (PLL) IC’s power
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 8

supply line from the VCO’s power supply line by employing C. Spurious
a low-value series resistor in each line of approximately 20Ω. Spurs can be thought as noise that is concentrated at a
10. Make sure that the VCO’s loop filter and the VCO’s specific offset from the carrier. These are typically measured in
VCN T RL tuning line are not too exposed to EMI or digital dBc with a spectrum analyzer. There are many kinds of spurs
noise, as well as to any pulse coupling from the charge pump’s and they can have multiple causes, but most of them occur
output. Keep the VCO tuning line short, and away from at very predictable offsets. Spurs have a tendency to occur
noisy circuits of any kind. These issues can be aggravated at multiples of the phase detector frequency, input reference
by excessively cramped PCB part’s placement or a generally frequency, channel spacing and fraction of channel spacing.
poor PCB layout.

B. Jitter
Phase noise generation in oscillators/VCOs has been a
focus of important research efforts. It is still an issue despite
significant gains in practical experience and modern CAD
tools for design. In the design of VCOs, minimizing phase
noise is the prime task. This has been accomplished using
empirical rules or numerical optimizations, which are often
held as trade secrets by many manufacturers. The ability to
achieve optimum phase noise performance is paramount in
most RF designs, and the continued improvement of phase
noise in oscillators is required for efficient use of the frequency
spectrum. The degree to which an oscillator generates constant
frequency throughout a specified period of time is defined as Fig. 20. Spurs as seen on a Spectrum Analyzer.
the frequency stability of the oscillator. Frequency instability
is due to the presence of noise in the oscillator circuit that Reference spurs are spurious PLL outputs that form outside
effectively modulates the signal, causing a change in the of our desired passband. These spurs can be found on each side
frequency spectrum commonly known as phase noise. Phase of the VCO’s carrier, at a frequency offset that is equal to the
noise and timing jitter are measures of uncertainty in the output PLL’s channel spacing, and are created by PLL charge-pump
of an oscillator. Phase noise defines the frequency domain leakage and mismatch. Spurs must be reduced in amplitude
uncertainty of an oscillator, and timing jitter is a measure of as much as possible to prevent interference into the pass-
oscillator uncertainty in the time domain. band from a strong adjacent channel mixing with these spurs,
Figures 18 and 19 illustrate the frequency spectrum of and creating in-band interference within the receiver’s IF
ideal and real oscillators, as well as the frequency fluctuation frequency. (Keeping reference spurs low in amplitude will
corresponding to jitter in the time domain, which is random minimize reciprocal mixing of these LO spurs with any large
perturbation of the zero crossing of a periodic signal. amplitude RF interferers that are within the receiver’s first
mixer stage, and which can overwhelm the low-amplitude
desired signal within the IF. This could seriously decrease a
receiver system’s sensitivity.)
The spurs are produced, as stated, by the charge pump’s
own output pulses, which are being generated even when the
Phase-Locked Loop (PLL) is in perfect lock. Indeed, while
both a charge pump’s Iup and Idwn current pulses are normally
designed to source and sink equal values of current, this is not
really possible. There will always be a slight current offset, and
Fig. 18. Frequency Spectrum of Ideal and Real Oscillators.
any mismatch between Iup and Idwn currents will create these
reference spurs. The pulses will then modulate the VCO’s
DC control voltage VCN T RL at a frequency that is exactly
at fCOM , creating reference spurs at fout that are at the exact
same frequency of fCOM and its harmonics, and on both sides
of the PLL’s carrier fout . Therefore, a value of fCOM of 100
kHz will give us reference spurs at +100 kHz and −100 kHz,
and at integer multiples thereof, away from fout .
To make sure that the reference spurs are as low as possible
in divided-by-N PLLs, we should select a synthesizer chip
that has low charge-pump-leakage characteristics, and that
Fig. 19. Jitter in the Time Domain Related to Phase Noise in the Frequency has well-matched charge-pump currents. However, the only
Domain. remedial action we could easily take with an already built
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 9

PLL would be to improve the filtering of the close-in spurs of magnitude. The minimum loop bandwidth approaches zero
by tightening up the loop filter’s bandwidth, as well as making Hz and is limited by the filter capacitors becoming large. The
sure that the VCC power supplies are extremely well filtered. maximum loop bandwidth can be limited by either the VCO
Any assorted spurs that are over and above the typical fCOM input capacitance, forced loop components that one designs
reference spurs can sometimes be seen in the output of some around, or discrete sampling effects of the phase detector. This
synthesizers at assorted frequencies. These irregular spurs can discrete effects tend to become an issue around one-tenth of
be caused by conducted or radiated coupling of noise or RF the phase detector frequency and result in instability around
interference into the PLL. The cure is the standard one, and can one-third of the phase detector frequency. This leaves a very
significantly reduce these atypical spurs to low levels: effective wide range of choices for the loop bandwidth and it has a very
decoupling of all PLL voltage supplies, as well as proper EMI profound impact in lock-time, jitter, phase noise and spurs.
board layout procedures. There is no loop bandwidth that is optimal for all performance
metrics, but there is one that is optimal for jitter, BWJIT ,
D. Lock-Time which serves as a good starting point for discussing the trade-
offs in choosing the loop bandwidth. BWJIT can be found
PLL lock time can be shortened by raising the fCOM as the offset frequency where the VCO and PLL (and input
frequency, since fCOM controls the charge pump’s pulse reference) noise cross as shown in the following Figure .
frequency, and will also permit an increase in the loop-
filter bandwidth. While increasing the loop bandwidth will
decrease lock-time, it will also increase phase-noise and spur
amplitudes, as well as possibly creating loop instability if
widened by more than fCOM 5 . However, the lock time can be
considerably sped up by never permitting the VCO’s tuning
voltage to be any closer than 1 V from either supply voltage
rail of the charge pump. This particular effect on lock time is
caused by saturation of the charge pump at its supply voltage
extremes, and can be circumvented by:

1. Using a VCO with a higher tuning sensitivity;

2. Using a higher charge-pump voltage supply; Fig. 21. Optimal Jitter Bandwidth.

3. Using an active op-amp loop filter with a higher VCC;

4. Using loop capacitor types that do not characteristically


show signs of capacitor current soakage, since this internal The frequency ωp , can be defined as the loop bandwidth.
dielectric effect will prevent the capacitor from fully This definition is some what different from that of the loop
discharging within the short time permitted. The plastic film bandwidth ω3dB of the second-order loop filter, but it can
types are superior to other capacitors in this specification. be used to identify a newly defined loop bandwidth with
maximum phase margin.
p
−ln( tolerance
f2 −f1 ∗ 1 − ξ2)
Lock − T ime = (8)
ωn ∗ ξ
The time taken to reach the steady state is know as lock −
1
time. The lock-time is defined as the time typically taken to ωp = √ . (10)
reach within 5% of the steady state’s value. The lock-time τ2 τ1
usually varies depending on ξ, but for ξ = 0.707, gives
1
Tlock = (9)
fn
In the above figure, the optimal bandwidth is where the
IV. L OOP BANDWIDTH O PTIMIZATION PLL and VCO noise cross; about 242.5 KHz. If we assume
It is well known that the overall noise performance of a PLL that the loop filter is an ideal filter with a brick wall response
depends not only on the choice of the loop bandwidth, but also and integration limits over the whole range, we can reason
on the performance of the individual components in a PLL. this by remembering that jitter is related to the area under
Therefore, the first step of reducing the overall noise of the the curve. If the loop bandwidth was narrower, then the VCO
PLL should be to identify the components generating noise in noise would dominate at some offset below the BWJIT , if
the PLL. The loop bandwidth is the most critical of all design the loop bandwidth was wider, then the PLL noise would be
parameters and can impact spurs, lock-time and jitter by orders higher for some effects above BWJIT .
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 10

Performance Optimal Typical Limiting Factors From the given values:


Metric Loop
Bandwidth 900M Hz
N= = 4500 (11)
Jitter BWJIT or 0 Hz A bandwidth close to BWJIT is optimal for jitter
provided that this number is greater than the lower
200KHz
integration limit for the jitter. If this is not the case,
then the optimal bandwidth is as narrow as possible.
secφp − tanφp
Lock-Time
fP D
Increasing the loop bandwidth improves lock-time with τ1 = =
10
provided it is not limited by discrete sampling effects ωp
(which start to be a consideration when BW >
π π
fP D
10
or VCO digital calibration (in the case of sec(45 ∗ 180 ) − tan(45 ∗ 180 ) (12)
integrated VCO). Also, the ability to increase the lood = =
bandwidth may be limited by the VCO input capaci-
tance, or if there are fixed components in the loop filter.
2π10 ∗ 103
= 6.592 ∗ 10−6 sec
Spurs 0 Hz Reducing the loop bandwidth generally improve spurs,
but some spurs can also have causes that are not filtered
by the loop filter (like crosstalk) which will limit much 1
spurs can be improved by decreasing the loop band- τ2 = =
width. ωp2 τ1
Phase Noise 0 Hz or Infinite If the phase noise is less than the optimal jitter band- 1 (13)
width, then it will improve with wider bandwidths until
= =
is just the noise due to the input reference and the PLL.
If the phase noise offset is greater than the optimal (62831.85)2 (6.592 ∗ 10−6 )
jitter bandwidth, then it will improve for narrower loop
bandwidths until it becomes just the free-running VCO = 3.842 ∗ 10−5 sec
noise.
s
Table X gives a good summary about how to choose a loop Kτ1 1 + (ωp τ2 )2
C1 = 2 = 2.33nF (14)
bandwidth. If jitter is the only care about, then the optimal loop ωp N τ2 1 + (ωp τ1 )2
bandwidth is theoretically where VCO and PLL noise cross.
τ2
In practice, the fact that the loop filter does not have an ideal C2 = C1 ( − 1) = 11.26nF (15)
brick wall response can cause this to be off by a good 25%. τ1
Even if BWJIT is not the optimal bandwidth, it is close and τ2
the definition still remains as the frequency where the PLL and R2 = = 3.413kΩ (16)
C2
VCO noise cross. If lock-time is the only concern, then make
Loop Bandwidth (ωp ) for the maximum phase margin:
the loop bandwidth as wide as realistically possible, however
at some point it will be limited by the fact that loop filter 1
capacitors get swamped out by the VCO input capacitance, ωp = √ =
τ2 τ1
1
or by the loop bandwidth getting larger than about 10 of the 1
=p = (17)
phase detector frequency. Furthermore, for devices that have
(3.842 ∗ 10 ) ∗ (6.592 ∗ 10−6 )
−5
integrated VCO’s, the VCO digital calibration time can start to
dominate the lock-time at some point. For a spur that is outside = 62828.4rad/s
the loop bandwidth, narrower bandwidths can improve the spur Lock-Time:
to a point. However, if the spur is due to a mechanism that
crosstalk around the loop filter, then narrowing the bandwidth 1 1
will do no good. For a spur that is inside the loop bandwidth, Tlock−time = = = 1.59164 ∗ 10−5 sec (18)
ωp 62828.4
sometimes widening the loop bandwidth can help. Typically
the worst bandwidth for a spur is when it is right near where
the loop bandwidth peaks, which gives it the combination of Attenuation = 10 ∗ log[(2πfCOM R3 C3 )2 + 1]0.5 ≈ ≈ 25dB
PLL and VCO spur mechanism work together. For phase noise (19)
of offset less then the optimal jitter bandwidth, opening up the We can relate it to the Attenuation as:
bandwidth will help because it filters out the effect of the VCO q
noise cropping in. It also improves the flatness of the close 10( Attenuation
10 )−1
loop response at this offset. If the phase noise is at an offset τ3 = =
(2πfCOM )2
greater than the optimal jitter bandwidth, then the narrowing q (20)
25
the bandwidth typically is optimal as it filters out the PLL 10( 10 )−1
noise contribution. = = 1.412 ∗ 10−5 sec
(2π200 ∗ 103 )2

A. Numerical Loop Bandwidth Optimization 0 1


τ2 = =
Design of a frequency synthesizer of fo = 900M Hz ωc2 (τ1 + τ3 )
requires the use of a third-order loop filter. The third-order 1 (21)
= =
loop filter must have a loop bandwidth of ωp = 2π ∗10kHz = 251322 ((6.592 ∗ 10−6 ) + (1.412 ∗ 10−5 ))
62831.85rad/s and a phase margin of φp = 45 deg. The = 7.644 ∗ 10−5 sec
comparison (or reference) frequency fCOM = 200KHz. The
tuning sensitivity of VCO is Kv = 2π ∗ 20M rad/V . The s
0
phase detector constant is Kp = 5/(2π)mA/rad. Compare τ1 Kφ Kvco 1 + (ωc τ2 )2
C1 = 0 =
the element values of the third-order loop filter. τ2 N ωc2 (1 + (ωp τ1 )2 )(1 + (ωc τ3 )2 ) (22)
Solution : = 274.929nF
R EFERENCES
C1 274.929 ∗ 10−9 [1] Mr. Moazzam, Reza, ”RF PLL Synthesizers for Wireless Commu-
C3 = = = 27.492nF (23) nications”, UCSD - University of California San Diego (Extension),
10 10
California, 2019.
[2] Dean, Banerjee, ”PLL Performance Simulation and Design Handbook”
5th , USA, 2017.
τ3 1.412 ∗ 10−5 [3] Ulrich L., Rohde, ”Microwave and Wireless Synthesizers: Theory and
R3 = = = 513.60Ω (24)
C3 27.492 ∗ 10− 9 Design”, USA, 1997.
[4] Jack A., Smith., ”Modern Communication Circuits” 2nd , USA, 1997.
Optimized Loop Bandwidth (BW) results: [5] Venceslav F., Kroupa., ”Phase Lock Loops, and Frequency Synthesis”,
England, 2003.
[6] Pozar, David M., ”Microwave and RF Design of Wireless Systems”,
1 USA, 2001.
ωp = p 0
= [7] Analog Devices, ”PLL For High Frequency Receivers and Transmitters”
τ2 τ1 1st , 2nd , 3rd , 1999, USA.
1 (25) [8] Rohde Schwarz GmbH Co. KG, ”Mastering Phase Noise Measurements
=p = (Part 1)”, Germany.
(7.644 ∗ 10−5 ) ∗ (6.592 ∗ 10−6 ) [9] Ulrich L., Rohde, ”RF/Microwave Circuit Design for Wireless Applica-
= 44548.3 rad/s tions” 2nd , New Jersey, 2013.
[10] Razavi, Behzad, ”RF Microeletronics” 2nd , New York, USA, 2012.
[11] Razavi, Behzad, ”Design of Analog CMOS Integrated Circuits” 2nd ,
BW=7.090 KHz New York, USA, 2000.
Lock-Time=2.2447 ∗ 10−5 sec [12] Kyung-Whan Yeom, ”Microwave Circuit Design: A pratical Approach
Using ADS”, USA, 2015.
[13] Ulrich L., Rohde, ”The Deisgn of Modern Microwave Oscillators for
Wireless Applications: Theory and Optimization”, New Jersey, USA,
V. C ONCLUSION 2005.
[14] Ulrich L., Rohde, ”Digital PLL Frequency Synthesizers: Theory and
The impact of a loop bandwidth cannot be ignored and it is Design”, USA, 1983.
therefore critical to choose this in optimal way. According to
results we can confirm that as we decrease the loop bandwidth
increases the lock-time, but it will also decrease phase-noise
and spur amplitudes, and the opposite is true. Phase-noise,
spurs and lock-time are key performance characteristics and
are all impacted dramatically by loop characteristics, specially
the loop bandwidth. The loop is stable (≤ fCOM /5). We added
a low-pass (3rd order loop filter so that it generates 25dB
attenuation at the comparison frequency fCOM = 200KHz.
Improving the level of comparison frequency spurious a low-
pass filter in the form of R3 C3 can be added to reduce the
comparison frequency spurious. For the low-pass reference
spurious attenuator we set its bandwidth small enough to
generate required attenuation for reference and high enough
(usually greater than 5 times of the ωp ) to not disturb the
loop stability. Adding R3 C3 causes reduction in the phase-
margin. C1 and C2 was increased and R2 reduced (slightly) to
increases phase-margin. C2 and R2 . For R3 and C3 we set C3
smaller that C1 and C3 ≤ C1 /10 to keep τ3 from interacting
with τ1 and τ2 , also R3 ≥ 2R2 . The design of the loop filter
starts with understanding the key performance parameters of
loop bandwidth. The benefits of higher filter orders depend
manly on how far the noise/spur frequency of interest is from
the loop bandwidth.

Eng. Bruno Taranto Alvim was born


(1978) in city of Vila Velha, Brazil,
living in San Diego, California (CA),
USA. Bruno have Bachelor’s Degree in
Electrical Engineering (2016), doing Radio
Frequency Engineering Certification (2019)
in University of California San Diego
(Extension).
”... by the what i saw, by the
what i read, by the what i lived ...

Fig. 22. Complete Microwave Phase-Lock Lopp (PLL) for Wideband.

11
RF ENGINEERING CERTIFICATION - UCSD - FEBRUARY 2019, CALIFORNIA, USA 12

List of Figures
1 Standard Negative Feedback Control System
Model. . . . . . . . . . . . . . . . . . . . . . . 2
2 Typical PLL Receiver. . . . . . . . . . . . . . 2
3 Phase-Locked Loop (PLL) Synthesizer. . . . . 3
4 Equivalent Circuit of a Crystal. . . . . . . . . 3
5 A Typical Crystal Oscillator Diagram. . . . . . 3
6 Input Reactance of a Crystal Resonator. . . . . 3
7 Pierce Crystal Oscillator Circuit. . . . . . . . . 4
8 PFD and its Input/Output Characteristic. . . . 4
9 XOR Gate as a PFD. . . . . . . . . . . . . . . 4
10 A Charge Pump PLL Chip. . . . . . . . . . . 4
11 PFD, Charge-Pump and Loop-Filter. . . . . . . 5
12 The Waveform from the Charge-Pump, and the
Output Waveform from Loop-Filter. . . . . . . 5
13 Typical Loop-Filter. . . . . . . . . . . . . . . . 5
14 A Third Order Loop-Filter. . . . . . . . . . . . 5
15 A Varactor-Tuned Voltage-Controlled Transis-
tor Oscillator Circuit. . . . . . . . . . . . . . . 6
16 PLL Noise Transfer Function. . . . . . . . . . 7
17 The major Noise contributors and output Spec-
trum of a PLL Synthesizer, narrow Frequency
sweep. . . . . . . . . . . . . . . . . . . . . . . 7
18 Frequency Spectrum of Ideal and Real Oscil-
lators. . . . . . . . . . . . . . . . . . . . . . . 8
19 Jitter in the Time Domain Related to Phase
Noise in the Frequency Domain. . . . . . . . . 8
20 Spurs as seen on a Spectrum Analyzer. . . . . 8
21 Optimal Jitter Bandwidth. . . . . . . . . . . . 9
22 Complete Microwave Phase-Lock Lopp (PLL)
for Wideband. . . . . . . . . . . . . . . . . . . 11

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