SMPTE 259M Error Detection and Handling
(EDH) Generation and Detection IP Core
Application Note Abstract
This application note provides an explanation of the EDH Generation and Detection of the IP Core for SMPTE259M.
1.0 Introduction
The Society of Motion Picture and Television Engineers
(SMPTE) has specifications regarding how errors should be
detected in Standard Definition (SD) data signals. For SD
applications, the process is called Error Detection and Han-
dling (EDH). EDH must conform to standards of SD signals
as specified in SMPTE 259M, and SMPTE Recommended
Practice (RP) 165. EDH generation and detection includes
the use of Cyclic Redundancy Code (CRC) checkword gener-
ation for SD data using the X16 + X12 + X5 + 1 polynomial. By
adhering to the EDH practice, errors in SD transmission can
be detected.
2.0 Functional Blocks
EDH generation and detection is separated into four main
blocks: The generation of the CRC checkwords, the detection
of the CRC checkwords, the generation of the actual EDH
packet, and the detection of the EDH packets. The main HDL
module necessary for EDH generation and detection is
edh.vhd. The code for the SD CRC generation is included in
crc.vhd, and the detection is included within edh.vhd. The
generation of the SD CRC checkword in the EDH packet
should not be confused with the CRC checkword in SMPTE
292M standards. The two checkwords are not the same.
2.1 CRC Generation
CRC checkwords are generated using the received parallel
data coming from the HOTLink II™ SERDES. There are two
categories for SD CRC checkwords: active field and full field.
Section 2.1.1 gives a more in-depth explanation on active
and full field samples. The CRC calculations are carried out
using the SMPTE RP165 CRC-CCITT polynomial generation
algorithm on each rising edge of the incoming clock signal.
Figure 1 displays the polynomial and diagram for CRC-
CCITT.
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Associated Project: No
Associated Part Family: HOTLink II™ Video PHY
Software Version: None
Associated Application Notes: None
Figure 1. CRC-CCITT Polynomial and Diagram
Polynomial: X16 + X12 + X5 + 1
15 14 13 12 11 + 10 9 8 7 6 5 4 + 3 2 1 0 +
Serial Data
The 16 bit CRC checkwords generated are then inserted into
the EDH packets when the EDH word is generated. Please
see section 2.3.2 for more information on where the CRC
packet is inserted in the EDH packet.
Separate CRC calculations are made for the active field and
the full-field as specified by SMPTE, and each calculation
produces a 16 bit word. Calculations for both the active field
samples and full-field samples are necessary for continuous
error checking. If data is changed outside the active field, the
full-field CRC value does not need to be recalculated. The
edh.vhd and crc.vhd HDL modules are used to perform the
CRC calculations.
2.1.1 Active Field and Full-Field CRCs
The active samples and full-field samples are determined
according to the recommended practices given by SMPTE
RP165, and SMPTE 347M provides more information for the
4:4:4:4 composite video types. Table 1 and Table 2 give the
active and full-field ranges for NTSC and PAL video types.
The function crc_ranges in edh.vhd determines whether a
sample is in an active field, full-field, or neither. The neces-
sary inputs for this function are the linecount, the wordcount,
and the video_type. If a sample is deemed to be within the
active field sample range, the flag active_crc_range is set to
‘1’. If a sample is deemed to be within the full-field sample
range, the flag full_crc_range is set to ‘1’. Another purpose of
this function is that the flag reset_crc is set to ‘1’ prior to the
reception of the EDH words. When this flag is set to ‘1’, the
variables storing the active and full-field CRC results are
cleared in preparation for a new calculation.
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Table 1. NTSC Active and Full-field Samples

Data Item Lines 4:4:4:4 Word 13.5 MHz Word 18 MHz Word
First full-field sample 12 and 275 2884 1444 1924
First active picture sample 21 and 284 0 0 0
Last active picture sample 262 and 525 2879 1439 1919
Last full-field sample 8 and 271 2879 1439 1919

Table 2. PAL Active and Full-field Samples

Data Item Lines 4:4:4:4 Word 13.5 MHz Word 18 MHz Word
First full-field sample 8 and 321 2884 1444 1924
First active picture sample 24 and 336 0 0 0
Last active picture sample 310 and 622 2879 1439 1919
Last full-field sample 4 and 317 2879 1439 1919

2.2 CRC Detection
For SD applications, CRC detection is embedded in the EDH
detection process. The CRC words are detected when the
rest of the EDH packet is detected as well. Verification of the
correct CRC word also occurs at that time. Please refer to
section 2.4 for more information.
2.3 EDH Generation
2.3.1 EDH Checkword Generation
The information in each EDH word is determined based on
Table 3. Table 3 describes the different information which
each EDH word carries. There is a total of 23 EDH words in
the packet. Excluding the ancillary data, all of the words have
‘0’s for the two least significant bits. Since the EDH words are
10 bits, this allows for compatibility with equipment using 8
bits. Words 6 through 11 contain the active and full-field CRC
checkwords. ‘P’ is the parity bit. If bits 2 through 7 combine to
be an odd number, the P is set to ‘1’ so that bits 0 through 8
combine to be an even number. In this manner even parity is
achieved. P is always set as the inverse of P. The ‘V’ in words
8 and 11 may be used to flag whether a CRC calculation is
valid or not. In this manner, implementations which only per-
form either active or full-field calculations can be achieved.
However, in this HDL module, V is always set to ‘1’. In EDH
generation, the correct bits are simply moved into the corre-
sponding words. Words 12 through 14 contain the error flags.
However, this EDH module does not employ the error flags.
Therefore, words 12 through 14 are always set to
“1000000000”. For designers who wish to employ the error
flags, Table 4 contains descriptions for each one. The final
EDH word is the checksum. Checksum is a sum of the 9 least
significant bits of all the words from Data ID up to and includ-
ing the Full-field error flags. he carry for the sum is ignored.

Table 3. EDH Word Information

Word b9
Number Data Item msb b8 b7 b6 b5 b4 b3 b2 b1 b0
0 Ancillary data header, word 1 - component 0 0 0 0 0 0 0 0 0 0
1 Ancillary data header, word 2 - component 1 1 1 1 1 1 1 1 1 1
2 Ancillary data header, word 3 - component 1 1 1 1 1 1 1 1 1 1
Ancillary data flag - composite 1 1 1 1 1 1 1 1 0 0
3 Data ID 0 1 1 1 1 1 0 1 0 0
4 Block number 1 0 0 0 0 0 0 0 0 0
5 Data count 0 1 0 0 0 1 0 0 0 0
6 Active picture data word 0 crc<5:0> P P c5 c4 c3 c2 c1 c0 0 0
7 Active picture data word 1 crc<11:6> P P c11 c10 c9 c8 c7 c6 0 0
8 Active picture data word 2 crc<15:12> P P V 0 c15 c14 c13 c12 0 0
9 Full-field data word 0 crc<5:0> P P c5 c4 c3 c2 c1 c0 0 0
10 Full-field data word 1 crc<11:6> P P c11 c10 c9 c8 c7 c6 0 0
11 Full-field data word 2 crc<15:12> P P V 0 c15 c14 c13 c12 0 0

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Table 3. EDH Word Information (Continued)

Word b9
Number Data Item msb b8 b7 b6 b5 b4 b3 b2 b1 b0
12 Ancillary data error flags P P 0 ues ida idh eda edh 0 0
13 Active picture error flags P P 0 ues ida idh eda edh 0 0
14 Full-field error flags P P 0 ues ida idh eda edh 0 0
15-21 Reserved words (7 total) 1 0 0 0 0 0 0 0 0 0
22 Checksum S8 S8 S7 S6 S5 S4 S3 S2 S1 S0

Table 4. Error Flag Descriptions wordcount. The function edh_insert in edh.vhd carries out the
insertion.
Error Flag Description
edh Error Detected Here—Serial transmission error Figure 2. EDH Packet Location in Each Line
was detected. In other words, a checksum mis-
match occurred in at least one of the ANC blocks.

EDH PACKET
eda Error Detected Already—Serial transmission error
was detected upstream. If the edh flag has been

EAV

SAV
raised upstream, then upon reception in another Active Video Data
device, the edh flag is lowered, and the eda flag is
raised in its place.
idh Internal Error Detected Here—An internal hard-
ware error, unrelated to the serial transmission, Horizontal Blanking
was detected. Interval

ida Internal Error Detected Already—An idh error was

2.4 EDH Detection
detected upstream.
As specified in Table 5, EDH words are only inserted in cer-
ues Unknown Error Status—The received signal is
tain lines and within a specified word range. In the EDH HDL
generated by a source which does not support
module, three functions are dedicated to EDH detection:
EDH.
edh_locate, crc_compare, and crc_error_counters. The func-
2.3.2 EDH Insertion tion edh_locate requires the inputs linecount and wordcount.
Regardless of the video type, there are a total of 23 EDH
EDH insertion is carried out based on SMPTE RP165. EDH
words. Hence, edh_locate first determines the video type.
information is inserted in different places for different video
Consequently, if the received word is within the correct line
types. Table 5 is a table which describes where insertion is
and word range, then the word number is remapped into the
performed based on the various video types. Each video type
range of 0 to 22. For example, if the video type is NTSC 13.5
demands 23 EDH words.
MHz, the linecount is either 9 or 272, and the wordcount is
Table 5. EDH Insertion Points between 1689 to 1711, then the following code is executed:
Video Type Lines Word range edhcount ≤ wordcount - 1689.
NTSC 13.5 MHz 9 and 272 1689–1711
This conversion is necessary due to the fact that there are
NTSC 18 MHz 9 and 272 2261–2283 different video types, but all video types still share the same
PAL 13.5 MHz 5 and 318 1701–1723 23 EDH words.
PAL 18 MHz 5 and 318 2277–2299 The function crc_compare is used to compare the locally
NTSC 4:4:4:4 9 and 272 3405–3427 calculated CRC values against the received CRC values.
As seen in Table 3, the active CRC data is located in words 6,
PAL 4:4:4:4 5 and 318 3429–3451
7, and 8, and the full-field CRC data is located in words 9, 10,
Figure 2 displays where the EDH packet is located in respect and 11. The crc_compare function first determines whether
to the rest of the data in a line. The EDH packet is located an EDH word is detected by verifying the contents of word 1
within the horizontal blanking interval prior to the SAV packet as given by Table 3. The crc_compare function copies the
for the lines specified in Table 5. In the EDH HDL module, CRC data from words 6 through 11 into the 16 bit vectors
insertion is done on every rising edge of the input clock. If the rx_acrc and rx_fcrc. The received CRC data is then com-
pared against the locally calculated CRC data. If the two do
line number and word number correspond to that of an EDH
word, then the EDH information is inserted into the output not match then a flag is raised and the function
data. The line and word information come from linecount and crc_error_counters increases the error count.

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3.0 IP Core Features ■ Complies with SMPTE 259M for SD standards

This IP Core allows system designers to generate and detect
EDH packets according to SMPTE 259M and SMPTE RP165
standards.
The deliverables of this IP Core include two pieces of VHDL
code: edh.vhd, and crc.vhd. Also included in this document is
a block diagram of EDH generation and detection, and Input
and Output descriptions.
This IP Core assume prior knowledge of the HOTLink II SER-
DES. For more information, please visit www.cypress.com.
■ The HDL module, edh.vhd, generates and detects EDH
packets
■ The library, crc.vhd, generates the SD CRC word
■ Complies with SMPTE RP165 for EDH generation and
detection
■ Communicates with the HOTLink II SERDES
■ Uses the RP165 X16 + X12 + X5 + 1 CRC-CCIT polynomial
generation to generate SD CRC information
4.0 Resource Usage
The EDH uses 554 logic cells out of a total of 20,060 logic
cells in an Altera Cyclone FPGA, using the Quartus II com-
piler. The code is also compatible with Xilinx and other pro-
grammable logic devices.

5.0 Block Diagram

Figure 3. EDH Block Diagram

CLK 8 ACRC_ERRORS

ENABLE 8 FCRC_ERRORS

DATA_IN 10 10 DATA_OUT

LINECOUNT 10

EDH Generation and Detection

WORDCOUNT 12

VIDEO_TYPE 3

READ_ACRC_ERRORS

READ_FCRC_ERRORS

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6.0 Signal Descriptions

System Inputs Width Active Description
ENABLE 1 HIGH Enables the EDH detection.
LINECOUNT 10 N/A Indicates the current line being processed. When receiving data, this input is generated by
video_detect.vhd. When transmitting data this information is generated by the test pattern
generators.
WORDCOUNT 12 N/A Indicates the current word count in a line. When receiving data, this input is generated by
video_detect.vhd. When transmitting data this information is generated by the test pattern
generators.
VIDEO_TYPE 3 N/A Indicates whether the video is NTSC 13.5-MHz, 18-MHz, 4:4:4:4 or PAL 13.5-MHz, 18-
MHz, or 4:4:4:4. Comes from video_detect.vhd
READ_ACRC_ERRORS 1 HIGH When active the active CRC data is reset.
READ_FCRC_ERRORS 1 HIGH When active the full-field CRC data is reset.

System Outputs Width Active Description

ACRC_ERRORS 8 N/A A counter for the total number of Active CRC errors.
FCRC_ERRORS 8 N/A A counter for the total number of Full-field CRC errors.

Signal Inputs Width Active Description

CLK N/A N/A The clock signal for the FPGA provided by an external source.
DATA_IN 10 N/A The data received from the HOTLink II SERDES.

Signal Outputs Width Active Description

DATA_OUT 10 N/A The output data going to the HOTLink II SERDES which has the EDH information inserted
into it.

Summary
This application note provides an HDL code to communicate with HOTLink II Video PHY SERDES with an Altera FPGA to test
EHD Generation and Detection for SMPTE 259M.

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Document History Page

Document Title: SMPTE 259M Error Detection and Handling (EDH) Generation and Detection IP Core
Document Number: 001-14933
Orig. of Submission
Revision ECN Change Date Description of Change
** 998941 SFV 04/20/2007 Re-catalogued application note.
*A 1776911 SAAC 11/27/2007 Old App Note Conversion Project - Applied new template with new copyright info, format style,
doc number, and added info into properties of file for Google search engine. Did not change
any text within the app notes.
*B 3158263 SAAC 02/01/2011 No change. Sunset review spec. Template update.

In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new
documentation number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all
subsequent revisions.
HOTLink II is a trademark of Cypress Semiconductor Corporation. All other product and company names mentioned in this document may be
the trademarks of their respective holders.

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