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IV Semester B. Tech Examinations – May 2018

Course Title: Fundamentals of HDL Course Code: 16EC210
Duration: 03 Hours Date: 29-05-2018
Time: 10:00 AM to 01:00 PM Max Marks: 60

Note: 1. Answer 5 full questions choosing one from each Section

2. Each Section carries 12 Marks
3. Draw neat sketches wherever necessary
4. Missing Data may be suitably assumed


1.a. Explain the various steps involved in FPGA design, using design flow
diagram. (08 Marks)
1.b. Explain the major activities involved in development of an ASIC. (04 Marks)


2.a. Explain the Xilinx 3000 Series Logic Cell with a neat diagram. (08 Marks)
2.b. Explain the following terms briefly: (04 Marks)
(i) Synthesis (ii) Simulation
(iii) Network Isomorphism (iv) Layout Extraction


3.a. Compare the various modelling styles available in Verilog with suitable
examples. (08 Marks)
3.b. Define Identifiers. What are the restrictions in assigning identifier names? (04 Marks)


4.a. Explain with an example, the general structure of a module and a

simulation module in Verilog. (06 Marks)
4.b. Explain with examples various Lexical Tokens available in Verilog. (06 Marks)

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5.a. Write a module and its test bench to implement a 3:8 decoder instantiating
2:4 decoder. Interpret the simulation results obtained and derive the
synthesis output. (08 Marks)
5.b. Explain the various tri-state buffer primitives available in Verilog. (04 Marks)


6.a. Write a module and its stimulus to convert a 4-bit binary coded number
into its equivalent gray code using Gate Level Modeling. Interpret the
simulation results obtained and derive the synthesis output. (06 Marks)
6.b. Explain content resolution in Verilog. Illustrate the use of “wand” type of
net declaration for contention resolution. (06 Marks)


7.a. Design an ALU and write HDL code using case statement to implement the
following operations:
(i) Ctrl = “00” ; Addition of two 4 bit numbers;
(ii) Ctrl = “01” : Multiplication of two 4 bit numbers;
(iii) Ctrl = “10” ; Two’s Complement of a 4 bit number;
(iv) Ctrl = “11” ; Logical OR operation;
The output should consider the carry generated from addition and
overflow from multiplication.
Write the test bench and deduce the simulation results for the same. (08 Marks)
7.b. Explain the various operators available in Verilog. (04 Marks)


8.a. Implement a 4-bit up-down counter using the Verilog if statement. Use
subsidiary input (clear) to reset the counter and a control signal (u_d) to
show the up/down count. Write the test bench for the same. (06 Marks)
8.b. Explain the various Verilog switch level primitives. Write a module to
implement a 2 input NOR gate using switch primitives. (06 Marks)

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9.a. Explain the following: (04 Marks)

(i) specparam (ii) defparam
9.b. Discuss about the scope of function in Verilog. Using functions, write
Verilog code to check the parity of an 8 bit number. (08 Marks)


10.a. Discuss about the path delays associated with the following assignment
statements. (02 Marks)
(a,b *>s)=1
(p,q =>r)=(2,3)
10.b. What are the characteristics of task in Verilog? Write Verilog code to
implement a full adder using half adder as a task. (06 Marks)
10.c. Write UDP and test bench to define a 2 input AND gate. (04 Marks)

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