Proceedings of the 3rd IEEE Int. Conf.

on
Nano/Micro Engineered and Molecular Systems
January 6-9, 2008, Sanya, China

Analysis and Extraction of Contact Resistance in Pentacene Thin

Film transistors
Wenbin Guo1*, Liang Shen1, Caixia Liu1, Weiyou Chen1 and Dongge Ma2

1
State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering,
Jilin UniversityˈChina
2
State Key Laboratory of Polymer Physics and Chemistry, Changchun Institute of Applied Chemistry, China

Abstract—We have fabricated pentacene organic thin film

transistors (TFTs) on p-doped Si substrate serving as the
gate electrode with good yield and uniformity. These
transistors have excellent electrical characteristics, with
carrier field-effect mobility as large as 0.5cm2/Vs, on/off
current ratio of 106, subthreshold slope of 1V/decade, and
near-zero threshold voltage. The devices consisted of metal
source and drain electrodes contacting a 30nm-thick
pentacene film thermally deposited on SiO2 dielectrics .
We have applied a simple model to analyze and extract the
resistance of the source and drain contacts in these
transistors. The model was done based on the
dependencies of the channel resistances on the gate length
and gate voltage. We found that the contact resistance is
typically greater than the channel resistance. This suggests
that the electrical performance of organic TFTs, in which
reliable contact doping is difficult, may be dictated by the
contacts, rather than by the intrinsic carrier mobility of
the organic semiconductor.
Keywords-pentacene; transistors; contact resistance
I. INTRODUCTION
During the past decade, organic thin film transistors
(TFTs) have attracted intense research activity industrially and
academically due to their potential applications[1-9]. Such
applications may include active-matrix liquid-crystal displays,
active-matrix emissive displays, active-matrix flat panel
imagers, smart cards, smart price and inventory tags, and
large-area sensor arrays. Organic TFTs provide two principle
advantages over TFTs based on inorganic semiconductors.
They can be fabricated at lower temperature and, potentially,
at significantly lower cost. Low process temperatures in
particular may allow organic TFTs to be integrated on
inexpensive plastic substrates, rather than glass, and the
prospect of flexible, unbreakable, extremely low-weight flat
panel displays at low cost has spurred significant commercial
interest. Organic TFTs may also allow simple integrated
circuits to be fabricated at extremely low cost, for applications
such as radio-frequency identifi-cation tags, which are
envisioned to some day replace traditional barcode labels.
Many organic and polymer materials have attracted much
attention in recent years[10-18]. The interest can be attributed
to emerging demands in novel electronic devices like radio
Figure.1 Schematic of the top contact pentacene TFT structure
frequency tags, smart cards, and display media (active and
passive) on low cost and/or flexible substrates. Progress in this
field has been sustained by improvements of the material
properties and in the development of processing techniques
such as printing, stamping, or other high volume parallel
processing technologies. Up to now amorphous and
polycrystalline silicon have dominated low cost electronics
due to low processing temperatures and the application of low
cost substrates like glass or flexible foil, which facilitates
scaling of the process to larger substrates. Pentacene has
demonstrated the highest hole and electron mobility of organic
small molecules. The material exhibits a strong tendency to
form highly ordered films which depend on the growth
conditions and the substrate. Bulk single crystals are not
favorable for low cost electronics, because the fabrication is
time consuming and the crystals are small. Thin films are
more favorable, because they can be fabricated on various low
cost substrates. The hole mobility of thin film pentacene is
close to the intrinsic transport limit of bulk single crystals, and
thin film transistors (TFTs) with mobility of >1cm2/Vs have
been fabricated by several groups. The mobility is therefore
comparable with that achieved by amorphous silicon TFTs
and hence pentacene TFTs might be considered for large area
active matrix arrays.
In this paper we present results of contact resistance
analysis and extraction in the pentacene OTFTs, which was
top contact pentacene TFTs structure.
II. DEVICE FABRICATION
The pentacene TFTs we studied in this paper, which have
a p-doped Si substrate serving as the gate electrode. Thermally
grown silicon dioxide of 300nm thickness serves as the gate
dielectric. Pentacene active layer of 30nm thickness was
thermally deposited in vacuum from commercially available

*Contact author: Wenbin Guo is with the State Key Laboratory on

Integrated Optoelectronics, College of Electronic Science and Engineering,
Jilin University, 2699 Qianjin Street, Changchun 130012, China (phone:86-
431-85262357, fax:86-431-85262873, mail:guowb2008@gmail.com

978-1-4244-1908-1/08/$25.00 ©2008 IEEE. 99

prepurfied pentacene powder. The fabrication details can be In the saturation regime (V DS ! VGS  VT ) , mobility was
found in Ref.[19]. The pentacene TFT design, referred as top-
contact (TC) TFT is presented in Fig.1. TC OTFTs were Extracted from the transfer characteristics ( I D  VGS
fabricated by thermally evaporating the source and drain
contact metal (Au) through a shadow mask to define contacts characteristics) Plotted as I D  VGS . The mobility is
directly on the blanket layer of pentacene. Thermal calculated using Eq.(3) by solving for P,
evaporation is used in an effort to minimize the damage to the
2L w I D 2
organic film and the metal penetration The resulting TFT gate P ( ) . (5)
lengths, L, defined as a distance between the adjacent parallel WCi wVGS
contacts, were 10, 20, 30, 40, and 50mDŽThe contact width, The threshold voltage was determined from the intercept of
W, was 1200m. the fitting line used to extract the mobility in the linear regime

ċ. CONTACT RESISTANCE ANALYSIS

We present here an analysis of the electrical
characteristics and the contact performance of pentacene
organic TFTs fabricated in our lab. we can get the expressions
of channel resistance and contact resistance from the Ref.[20].
( I D  VGS characteristics) or the intercept of the fitting line
used to extract the mobility in the saturation regime
( I D  VGS characteristics). The parasitic source and drain
contact resistance ( RS and R D , respectively) are accounted
for in expressions that relate the effective gate-source ( VGS )
'

From simple FET theory a linear variation of I D with drain- '

and drain-source voltage ( V DS ) to their externally applied
source voltage ( V DS ) is expected for an ideal device biased
voltages through the potential drop across the parasitic
with a small V DS . Specifically, the channel of the device has resistance. These effective voltage are given by
the characteristics of a resistor with a resistance that is VGS' VGS  I D R S , (6)
dependent on the gate-source voltage ( VGS ). In the linear '
V DS V DS  I D ( R S  R D ) , (7)
regime, V DS  (VGS  VT ) , the following expression is and can be used to correct for the series contact resistances in
used to describe ID : Eqs. (2) and (3). Inserting Eqs.(6) and (7) into Eqs.(2) and (3)
yields
WPCi
ID
L
> @
VGS  VT VDS  VDS2 / 2 . (1) ID
WPCi '
(VGS  VT )VDS '
, (8)
L
Equation (1) can be simplified for V DS d (VGS  VT ) to WPCi '
WPCi ID (VGS  VT ) 2 . (9)
ID (VGS  VT )VDS , (2) 2L
L If RS and RD are known and constant (bias independent)
Where W is the transistor channel width, L is the transistor their parasitic effects are easily corrected using Eqs.(8) and (9).
channel length, P is the field-effect mobility, VT is the The extrinsic OTFT can be simplistically viewed as the
series combination of the intrinsic OTFT resistance and the
threshold voltage, and C i is the capacitance per unit area of parasitic source and drain contact resistances. Thus for small
the gate insulator. V DS the measured resistance of the extrinsic device ( RON
In the saturation regime, V DS ! (VGS  VT ) , I D is given
defined as wV DS / wI D ) when modeled as the series
by
WPCi RD , is given by
combination of Rch , RS , and
ID (VGS  VT ) 2 , (3)
L
2L RON Rch  RS  R D |  R p , (10)
Where all terms remain as previously defined. WPC i (VGS  VT )
The field-effect mobility in the linear regime was extracted
where R p RS  R D . Importantly, Rch as defined by
From the transconductance ( g m wI D / wVGS , for small and
Eq.(10) is still an approximation since the externally applied
constant V DS ) of the device. If W , L , and C i are known VGS is used rather than V'GS .
the field-effect mobility in the linear regime is calculated from
According to the basic equation of TFT, we established a
the relationship
numerical model to simulate the output and contact
Lg m 1
P . (4)
characteristics of pentacene TFT. The simulation results
illustrate how the device design can affect the operation of
WCi VDS
devices when a Schottky barrier is formed at the contacts.

100
 The total on-state resistance of the device was shown in
-5
Fig.2, It can be seen from the graph, the on-state resistance 3.0x10

shows a great dependence on the VGS . Fig.3 shows the -5

2.5x10
L=10Pm

relation between the channel length and channel resistance,

which was simulated based on Ref.[5]. When the channel -5
2.0x10

-IDS(A)
length increases, the channel resistance will also rise. So if we
-5
1.5x10 20Pm
7
7x10 30Pm
On-state resistance ( : )

-5
1.0x10
7 40Pm
6x10
-6
7 5.0x10 50Pm
5x10
7
4x10 0.0
0 -10 -20 -30 -40 -50 -60
7
3x10
VDS(v)
7
2x10
7 Figure.5 Output characteristics of TC pentacene TFTs with Au contacts.
1x10
0
want to raise the charge mobility of the device, the channel
0 -10 -20 -30 -40 -50 -60 must be decreased. Fig.4 is the results which we measured in
VGS(v) the TFTs, while the contact resistance is independent of
channel length, the channel resistance is proportional to the
Figure.2 The On-state resistance shows dependence on the VGS channel length. The contact resistance in source and drain
electrodes are much larger than the channel resistance.
5x10
11 Consequently, the relative influence of the contact resistance
increases as the channel length is reduced. Therefore, any
channel resistance ( :)

Vg=-10v
11 design or process improvements should specifically be
4x10
directed at a reduction of the contact resistance in organic
11
TFTs.
3x10
Fig.5 shows the Output characteristics of TC pentacene
11
-20v TFTs with Au contacts. The device dimensions are L=10, 20,
2x10 30, 40, 50m, W=1200m, and SiO2 gate insulator thickness
-30v
11
of 300nm. The small decrease of I DS for the TC TFT is due to
1x10 -40v
-50v
-60v the parasitic series resistance associated with the ungated
0 material between the metal contact formed on top of the
0 20 40 60 80 100 organic semiconductor and the field accumulated channel
channel length(Pm) formed at the SiO2 interface. Accordingly, the extrinsic
mobility calculated from the current-voltage characteristics is
Figure.3 the channel resistance is dependence on the channel length larger for TC TFTs when an injection barrier is present. While
it is not clearly visible from Fig. 5, it is worth noting that an
5
4x10 injection barrier at the contacts also results in a deviation from
Rch per 10um channel length the ideal power law behavior given in Eqs. (2) and (3).
channel resistance (: )

Rc contact resistance Specifically, our simulations show that for both designs and
5
3x10 regardless of the injection barrier the sheet carrier density is
nearly identical in the middle of the TFT channel for a given
2x10
5 VGS above threshold. In the vicinity of the contacts the charge
density increases for the case of no injection barrier. Not
5
surprisingly, a depletion region is formed when contacts with
1x10 an injection barrier are formed to the semiconductor of the
TFT. The depletion region forms between the field
0
accumulated channel and the contact metal for the TC TFT.
0 -10 -20 -30 -40 -50 -60
Č. SUMMARY
VGS(v)
For OTFTs, the parasitic resistance is the mostly drawback
Figure.4 Extraction of channel and contact resistance of the device for enhance of mobility. Because parasitic resistance

101
degenerates performance of OTFT, it is important to discover
and decrease the parasitic resistance. Basing on the I-V
equation of OTFT, we simulated the channel and contact
resistance and gave the effects of resistance on OTFT. Contact
barrier height between metal and semiconductor were
analyzed. We have investigated parasitic contact effects for
OTFT device designs of technological interest and using top
contact structure. Charge injection is shown to be dependent
on choice of the contact metal in a nontrivial way. The device
operation and performance are shown to be dominated by
effects related to the device design and processing, and
simplistic energy-band diagrams are shown to be of limited
use for selecting contact metals. The electrical characteristics
of devices with asymmetric metals for the source and drain
contacts show that charge injection at the source contact
dominates the extrinsic device performance. Importantly, we
show that parameters used to describe the device performance
and operation, such as VT and P , are strongly dependent on
the contacts and may not reflect the channel properties of the
device. We think this analysis about the contact resistance will
have good effect in designing and fabrication of the OTFT
device.
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