La A972p PDF

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : Goliad MLK 12 UMA ENTRY
1 1
PCB NO : LA-A972P
BOM P/N : 4319RK31LXX
GPIO MAP: 3.3b
2
Goliad MLK 12" UMA ENTRY 2
Broadwell U Processor
2013-12-23
REV : 0.2 (X01)
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
3 CXDP@ : XDP Component 3
CONN@ : Connector Component

VPRO@ : Vpro Component
Layout Dell logo
NVPRO@ : Non-Vpro Component
COPYRIGHT 2013
ALL RIGHT RESERVED
REV: X01
PWB: FGFC2
4 DATE: 1352-01 4
MB PCB
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
DA8000ZB000 PCB 14A LA-A972P REV0 MB W/O DOCKING 2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-A972P
Date: Monday, March 17, 2014 Sheet 1 of 48
A B C D E
A B C D E
Reverse Type
Goliad MLK 12 UMA Entry Block Diagram DDR3L-DIMM X2
BANK 0, 1, 2, 3
Trough eDP Cable
Memory BUS (DDR3L)
1333/1600MHz PAGE 18 19 LCD Touch
1 USB2.0[4] PAGE 23 1
eDP CONN Dual Lane eDP1.3

USB2.0[5]
Camera
PAGE 23
PAGE 23
USB2.0[0] TPS2544
INTEL USB POWER SHARE
DDI2 USB3.0/2.0+PS
mDP CONN PAGE 33 USB3.0[1] PAGE 31
PAGE 24
BROADWELL ULT USB
USB2.0[3]
Parade USB3.0[4] USB3.0/2.0
PAGE 31
WIGIG_DP
PS8339 DDI1
PAGE 25
USB2.0[1]
USB3.0[2] USB3.0/2.0
2
PAGE 32 2
HDMI CONN HDMI

PAGE 24 HD Audio I/F
PAGE 6~17
INT.Speaker
PAGE 21
SD4.0 Card reader PCIE1
O2 Micro OZ777FJ2LN SATA1
PAGE 29 PAGE 29 HDA Codec Universal Jack
ALC3234
SPI
PAGE 21
PAGE 21
PCI Express BUS W25Q64CVSSIQ Dig. MIC Trough eDP Cable
LPC
PCIE3 PCIE5_L0 PCIE4 64M 4K sector
W25Q32BVSSIQ LID switch

Full Mini Card SIM+HALL/B
32M 4K sector PAGE 7
mSATAPAGE 20
3
Intel Clarkville SMSC SIO USH CONN 3
WLAN/BT/ Discrete TPM PAGE 27

I218LM WIGIG ECE1099 AT97SC3205
PAGE 27
PAGE 28 PAGE 35 CPU XDP Port
PAGE 30
PAGE 9
USB2.0[2]
Transformer KB/TP CONN Automatic Power
PAGE 28
WIGIG_DP BC BUS SMSC KBC PAGE 37 Switch (APS)PAGE 9
MEC5085
PAGE 36 FAN CONN
RJ45 PAGE 36
PAGE 28
DC/DC Interface
PAGE 38
Power On/Off
4
Smart Card USH SW & LED PAGE 39 4
TDA8034HN
BCM5882
RFID
Fingerprint Compal Electronics, Inc.
FP_USB USB2.0[6] PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
CONN TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block diagram
PAGE 27 USH board BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
0.1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-A972P
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Monday, March 17, 2014 Sheet 2 of 48
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS PCIE USB3.0 SATA DESTINATION
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
USB3.0 1 JUSB1-->Rear left
D S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON D
USB3.0 2 JUSB3-->Right
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
PCIE 1 USB3.0 3 MMI (CARD READER)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
PCIE 2 USB3.0 4 JUSB2-->Rear Right
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
PCIE 3 LOM
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE 4 WLAN - JNGFF1
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCIE 5 WiGig - JNGFF1
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE 6 SATA 3 NA
SATA 2 NA
C
PM TABLE C
+5V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M SATA 1 JMINI3

+3.3V_ALW +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M
+3.3V_ALW_PCH +0.675V_DDR_VTT (M-OFF) SATA 0 NA
power
plane +3.3V_RTC_LDO +1.05V_RUN
+VCC_CORE
USB PORT# DESTINATION
State 0 JUSB1
1 JUSB3
S0 ON ON ON ON ON
2 WLAN + BT
B S3 ON ON OFF ON OFF BDW B
3 JUSB2
ULT
S5 S4/AC ON OFF OFF ON OFF
4 Touch Screen
S5 S4/AC doesn't exist OFF OFF OFF OFF OFF
5 CAMERA
6 USH
7 WWAN
0 BIO
USH
1 NA
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
LA-A972P
5 4 3 2 1
5 4 3 2 1
RUN_ON MPHYP_PWR_EN
TPS22966 SI3456
(UZ2) (QZ6)
D D
EN_INVPWR FDC654P
ADAPTER +BL_PWR_SRC
(QV1)
+1.05V_RUN +1.05V_MODPHY
A_ON SY8208
+1.05V_M
(PU300)
BATTERY +PWR_SRC
ALWON
TPS51285
+5V_ALW
(PU100)
C C
CHARGER
+3.3V_ALW
AUX_EN_WOWL
SIO_SLP_LAN#
PCH_ALW_ON
3.3V_HDD_EN
EN_LCDPWR
SUS_ON
RUN_ON
RUN_ON
A_ON
USB_PWR_SHR_EN# USB_PWR_EN1# USB_PWR_EN2#
ISL95813 RT8207
(PU501) (PU200)
TPS22966 TPS22966 TPS22966 APL3512 TPS22965 TPS22966 TPS2544 G547I2P81U G547I2P81U
(UZ8) (UZ2) (UZ3) (UV24) (UZ11) (UZ9) (UI3) (UI1) (UI2)
H_VR_EN
B B
SUS_ON
0.675V_DDR_VTT_ON
+VCC_CORE +1.35V_MEM
+3.3V_SUS +3.3V_M +3.3V_LAN +LCDVDD +3.3V_RUN +5V_RUN +5V_USB_CHG_PWR +USB_SIDE_PWR +USB_RIGHT_PWR

3.3V_CAM_EN#
+0.675V_DDR_VTT +3.3V_WLAN +3.3V_ALW_PCH
+3.3V_HDD LP2301ALT1G
A A
(QZ1)
+3.3V_CAM
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power rails
LA-A972P
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH +3.3V_RUN
2.2K 2.2K
AP2 MEM_SMBCLK
4 202
MEM_SMBDATA
2N7002
AH1 200 DIMMA
2N7002
1K
202
D
BDW D
+3.3V_ALW_PCH 200 DIMMB
1K
SML0CLK 28
AN1
SML0DATA 31 LOM
AK1 53
AH3 AU3
51 XDP
2.2K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K
A5 B6 2.2K
3A 3A
2.2K +3.3V_ALW
B4 DOCK_SMB_CLK
1A
1A A3 DOCK_SMB_DAT
2.2K
C C
+3.3V_ALW
2.2K
B5 LCD_SMBCLK
1B
A4 LCD_SMDATA
1B
2.2K
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K
+3.3V_SUS
2.2K
A50 M9
1E USH_SMBCLK
MEC 5085 1E
B53
USH_SMBDAT
L9 USH
B B
2.2K
+3.3V_ALW
2.2K
2B A49 CARD_SMBCLK
2B B52 CARD_SMBDAT
10K
+3.3V_ALW
10K
B50 9
1G CHARGER_SMBCLK
A47
CHARGER_SMBDAT
8 Charger
1G
2.2K
+3.3V_ALW
2.2K
2D B7 BAY_SMBDAT
A A
2D A7 BAY_SMBCLK
2.2K
+3.3V_ALW DELL CONFIDENTIAL/PROPRIETARY
2.2K
2A B48 GPU_SMBDAT PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMbus Block diagram
2A B49 GPU_SMBCLK BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
LA-A972P
5 4 3 2 1
5 4 3 2 1
UMA SATA port SATA0 SATA1 PCB SATA2/PCIE6 L1 SATA3/PCIE6 L0

M2 3042 M2 3042
E-Dock mSATA G12 UMA 2nd PCIe Lane for PCIe Cache (HCA & SATA-Cache)
contact to WWAN
Service Mode Switch:

Add a switch to ME_FWP signal to unlock the ME region and
NA mSATA G12 Entry NA NA
D D
allow the entire region of the SPI flash to be updated using FPT.
M2 3042
SATA2/PCIE6_L1 contact to WWAN
+3.3V_ALW_PCH ME_FWP_EC 2
@ RC301
1 ME_FWP
0_0402_5%
E-Dock mSATA G14 DSC SATA-Cache(no HCA)
M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN
PT, ST pop RC2 & SW1; MP pop RC301.
M2 3042 M2 3042
E-Dock HDD G14 UMA contact to WWAN
1
RC2
2nd PCIe Lane for PCIe Cache (HCA & SATA-Cache)
1K_0402_5%
SW1
NA mSATA G14D_En NA M2 3030 WIGIG contact to WLAN
2
<36> ME_FWP_EC 1
2 A
+RTC_CELL ME_FWP 3
4
B
C
NA HDD G14U_En NA NA
5 G1
G2
1
330K_0402_5%
SS3-CMFTQR9_3P
RC1
ME_FWP PCH has internal 20K PD.

2
FLASH DESCRIPTOR SECURITY OVERRIDE

PCH_INTVRMEN LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
CC1
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1
INTVRMEN - INTEGRATED SUS 1.05V VRM @ RC4 0_0402_5%
ENABLE
10M_0402_5%
C 12P_0402_50V8J C
1
High - Enable Internal VRs
1
RC7
Low - Enable External VRs
YC1 UC1E BDW_ULT_DDR3L
2
2
32.768KHZ_12.5PF_9H03220008
CC2
1 2 PCH_RTCX2 AW5
AY5 RTCX1
1 2 12P_0402_50V8J INTRUDER# AU6 RTCX2 J5
RC9 1M_0402_5% PCH_INTVRMEN AV7 INTRUDER SATA_RN0/PERN6_L3 H5
+RTC_CELL 1 2 SRTCRST# AV6 INTVRMEN RTC
SATA_RP0/PERP6_L3 B15 for DOCK
RC10 1 2 20K_0402_5% PCH_RTCRST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15
RC8 20K_0402_5% RTCRST SATA_TP0/PETP6_L3
<9> PCH_RTCRST# J8
SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1 <20>
H8
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 <20>
1 2 A17
1 2 SATA_TN1/PETN6_L2 B17 SATA_PTX_DRX_N1 <20> SATA HDD
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <20>
PCH_AZ_BITCLK AW8 J6
@ PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
CMOS1 SHORT PADS~D PCH_AZ_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
1 2 1 2
<21> PCH_AZ_CODEC_SDIN0
PCH_AZ_CODEC_SDIN0 AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15 for PCIe Cache (WWAN)
CC3 1U_0402_6.3V6K CC4 1U_0402_6.3V6K AU12 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
ME_FWP 1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
CMOS place near DIMM RC11 1K_0402_5% AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 for SATA-CACHE (WWAN)
I2S1_SCLK SATA_TP3/PETP6_L0
ME_CLR1 TPM setting CMOS_CLR1 CMOS setting
V1 MPCIE_RST#
B
Shunt Clear ME RTC Registers Shunt Clear CMOS SATA0GP/GPIO34 U1 B
SATA1GP/GPIO35 HDD_DET# <20>
V6
Open Keep ME RTC Registers Open Keep CMOS SATA2GP/GPIO36 AC1
SATA2_PCIE6_L1 <12>
SATA3GP/GPIO37 mCARD_PCIE#_SATA_R <36,7>
<9> PCH_JTAG_TRST# PCH_JTAG_TRST# AU62
+1.05V_M PCH_JTAG_TCK AE62 PCH_TRST A12
<9> PCH_JTAG_TCK PCH_TCK SATA_IREF +PCH_ASATA3PLL
RPC21 <9> PCH_JTAG_TDI PCH_JTAG_TDI AD61 L11
PCH_JTAG_TDO AE61 PCH_TDI RSVD K10
<9> PCH_JTAG_TDO PCH_TDO RSVD
1 8 PCH_JTAG_TDI @ RC300 <9> PCH_JTAG_TMS PCH_JTAG_TMS AD62 JTAG C12 SATA_COMP
2 7 PCH_JTAG_TMS AL11 PCH_TMS SATA_RCOMP U3 SATA_ACT# +3.3V_RUN
3 6 1 2 AC4 RSVD SATALED SATA_ACT# <39> RPC18
PCH_JTAG_TDO +1.05V_M PM_TEST_RST
4 5 AE63 RSVD MPCIE_RST# 5 4
<9> PCH_JTAG_JTAGX JTAGX
10K_0402_5% AV2 HDD_DET# 6 3
51_0804_8P4R_5% RSVD 7 2
<29,7> MMICLK_REQ#
2
8 1
<10> DGPU_PWROK
2 1 PCH_JTAG_JTAGX @ CC100
@ RC18 1K_0402_1% 1U_0402_6.3V6K 10K_8P4R_5%
1
2 1 PCH_JTAG_TCK BDW-ULT-DDR3L_BGA1168
@ RC21 51_0402_5% 5 OF 19 SATA Impedance Compensation
+PCH_ASATA3PLL
SATA_COMP 1 2
3.01K_0402_1% RC17
HDA for Codec
CAD note:
1 2 PCH_AZ_SDOUT Place the resistor within 500 mils of the PCH. Avoid
<21> PCH_AZ_CODEC_SDOUT
RC19 33_0402_5% routing next to clock pins.
1 2 PCH_AZ_SYNC
<21> PCH_AZ_CODEC_SYNC
RC20 33_0402_5%
A 1 2 PCH_AZ_RST# A
<21> PCH_AZ_CODEC_RST#
RC22 33_0402_5%
1 EMC@ 2 PCH_AZ_BITCLK
<21> PCH_AZ_CODEC_BITCLK
RC23 33_0402_5%
27P_0402_50V8J
1
@EMC@
CC5

2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (1/12)
Reserve for EMI BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
LA-A972P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_ALW_PCH
UC1G BDW_ULT_DDR3L
LPC_LAD0 AU14 AN2

<20,36> LPC_LAD0 LAD0 SMBALERT/GPIO11 PCH_SMB_ALERT# <11>
2
LPC_LAD1 AW12 AP2 MEM_SMBCLK RPC14
<20,36> LPC_LAD1 AY12 LAD1 SMBCLK AH1 1 8
LPC_LAD2 LPC MEM_SMBDATA SML1_SMBDATA
<20,36> LPC_LAD2 LAD2 SMBUS SMBDATA
LPC_LAD3 AW11 AL2 MEM_SMBCLK 6 1 SML1_SMBCLK 2 7
<20,36> LPC_LAD3 LAD3 SML0ALERT/GPIO60 DDR_XDP_WAN_SMBCLK <18,19,9>
LPC_LFRAME# AV12 AN1 SML0_SMBCLK MEM_SMBCLK 3 6
<20,36> LPC_LFRAME# LFRAME SML0CLK AK1 SML0_SMBDATA QC1A MEM_SMBDATA 4 5
SML0DATA
5
AU4 DMN66D0LDW-7_SOT363-6
SML1ALERT/PCHHOT/GPIO73 AU3 SML1_SMBCLK PCH_GPIO73 <12> 2.2K_0804_8P4R_5%
SML1CLK/GPIO75 AH3 SML1_SMBDATA SML1_SMBCLK <36> MEM_SMBDATA 3 4
SML1DATA/GPIO74 SML1_SMBDATA <36> DDR_XDP_WAN_SMBDAT <18,19,9>
PCH_SPI_CLK AA3 SML0_SMBCLK 2 1
<27> PCH_SPI_CLK PCH_SPI_CS0# Y7 SPI_CLK AF2 PCH_CL_CLK1 QC1B 499_0402_1% RC33
PCH_SPI_CS1# Y4 SPI_CS0 CL_CLK AD2 PCH_CL_DATA1 PCH_CL_CLK1 <30> DMN66D0LDW-7_SOT363-6 SML0_SMBDATA 2 1
D D
AC2 SPI_CS1 CL_DATA AF4 PCH_CL_DATA1 <30>
PCH_SPI_CS2# SPI C-LINK PCH_CL_RST1# 499_0402_1% RC34
<27> PCH_SPI_CS2# PCH_SPI_DO AA2 SPI_CS2 CL_RST PCH_CL_RST1# <30> +3.3V_RUN
<27> PCH_SPI_DO PCH_SPI_DIN AA4 SPI_MOSI
<27> PCH_SPI_DIN SPI_MISO
PCH_SPI_DO2 Y6 SML0_SMBCLK 2 1
PCH_SPI_DO3 AF1 SPI_IO2 @ RC30 0_0402_5% LAN_SMBCLK <28> DDR_XDP_WAN_SMBDAT 2 1
SPI_IO3 SML0_SMBDATA 2 1 2.2K_0402_5% RN3
LAN_SMBDATA <28>
@ RC32 0_0402_5% DDR_XDP_WAN_SMBCLK 2 1
+3.3V_SPI 2.2K_0402_5% RN4
CC6
BDW-ULT-DDR3L_BGA1168 1 2
7 OF 19
64Mb Flash ROM 0.1U_0402_25V6
UC2
SOFTWARE TAA SPI_PCH_CS0# 1 2 SPI_PCH_CS0#_R 1 8
@RC35
@ RC35 0_0402_5% SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64
RPC11 SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64
SPI_PCH_DIN 1 8 SPI_DIN64 4 /WP(IO2) CLK 5 SPI_DO64
SPI_CLK32 SPI_CLK64 +3.3V_SPI SPI_PCH_DO 2 7 SPI_DO64 GND DI(IO0)
SPI_PCH_CLK 3 6 SPI_CLK64 W25Q64FVSSIQ_SO8
1 2 SPI_PCH_DO2 SPI_PCH_DO3 4 5 SPI_PCH_DO3_64
2
2
33_0402_5%
33_0402_5%
RC29 1K_0402_5% +3.3V_SPI

RC61
@EMC@
RC62
@EMC@
1 2 SPI_PCH_DO3 33_0804_8P4R_5%
RC31 1K_0402_5% CC7 VPRO@
SPI_PCH_DO2 1 2 SPI_PCH_DO2_64 1 2
RC38 33_0402_5%
32Mb Flash ROM
1
0.1U_0402_25V6
33P_0402_50V8J
33P_0402_50V8J
UC3 VPRO@
SPI_PCH_CS1# RC50 1 2 0_0402_5% SPI_PCH_CS1#_R 1 8
/CS VCC
2
2
CC9
@EMC@
CC10
@EMC@
VPRO@ SPI_DIN32 2 7 SPI_PCH_DO3_32

RPC12 VPRO@ SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32
SPI_PCH_DO3 1 8 SPI_PCH_DO3_32 4 /WP/IO2 CLK 5 SPI_DO32
1
SPI_PCH_CLK 2 7 SPI_CLK32 GND DI/IO0

SPI_PCH_DO 3 6 SPI_DO32 W25Q32FVSSIQ_SO8
C C
SPI_PCH_DIN 4 5 SPI_DIN32
33_0804_8P4R_5%
CC8
SPI_PCH_DO2 1 2 SPI_PCH_DO2_32 2 1
RC55 33_0402_5%
VPRO@ 15P_0402_50V8J
2
1M_0402_5%
PCIECLK for UMA
3
4
BDW_ULT_DDR3L
RC63
UC1F
YC2
24MHZ_12PF_X3G024000DC1H
1
2
C43 A25 XTAL24_IN CC11
<29> CLK_PCIE_MMI# C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 1 2 XTAL24_OUT_R 2 1
MMI ---> <29> CLK_PCIE_MMI MMICLK_REQ# U2 CLKOUT_PCIE_P0 XTAL24_OUT @ RC65 0_0402_5%
<29,6> MMICLK_REQ# PCIECLKRQ0/GPIO18 K21 15P_0402_50V8J
B41 RSVD M21
A41 CLKOUT_PCIE_N1 RSVD C26 CLK_BIASREF
RC66 1 2 10K_0402_5% PCH_GPIO19 Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
+3.3V_RUN PCIECLKRQ1/GPIO19
+3.3V_RUN C35 MCP_TESTLOW1 +PCH_VCCACLKPLL
C41 CLOCK TESTLOW_C35 C34 MCP_TESTLOW2
<28> CLK_PCIE_LAN# B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 MCP_TESTLOW3 CLK_BIASREF 1 2
10/100/1G LAN ---> <28> CLK_PCIE_LAN LANCLK_REQ# AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 MCP_TESTLOW4 3.01K_0402_1% RC69
<28> LANCLK_REQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
RPC6 B38 AN15 PCI_CLK_LPC_0
4 5 <30> CLK_PCIE_WLAN# C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 1 2
WLAN (NGFF1)---> PCI_CLK_LPC_1 MCP_TESTLOW1 RC240 10K_0402_5%
CONTACTLESS_DET# <10,27> <30> CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1
3 6 LANCLK_REQ# WLANCLK_REQ# N1 MCP_TESTLOW2 RC241 1 2 10K_0402_5%
<12,30> WLANCLK_REQ# PCIECLKRQ3/GPIO21
2 7 B35 MCP_TESTLOW3 RC242 1 2 10K_0402_5%
mCARD_PCIE#_SATA_R <36,6> CLKOUT_ITPXDP
1 8 A39 A35 MCP_TESTLOW4 RC243 1 2 10K_0402_5%
PCH_GPIO16 <12> <30> CLK_PCIE_WIGIG# B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
10K_8P4R_5%
WGIG (NGFF1)---> <30> CLK_PCIE_WIGIG
WIGIGCLK_REQ# U5 CLKOUT_PCIE_P4
<12,30> WIGIGCLK_REQ# PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
B HCA/PCIe cache (NGFF2)---> RC68 1 2 10K_0402_5% PCH_GPIO23
T2 CLKOUT_PCIE_P5
B
+3.3V_RUN PCIECLKRQ5/GPIO23
BDW-ULT-DDR3L_BGA1168
6 OF 19
support SPI TPM support LPC TPM
from CPU to SPI ROM
PCB PCIE1 PCIE2 PCIE3 PCIE4 PCIE5 PCIE6 JSPI1 LPC_0 LPC_1 LPC_0 LPC_1
PCI_CLK_LPC_0 EMC@ RC74 1 2 22_0402_5% PCH_SPI_CS1# 2 1 SPI_PCH_CS1# 1
CLK_PCI_MEC <36> RC224 0_0402_5% 2 1
PCH_SPI_DO 2 1 SPI_PCH_DO 3 2 2
G12 UMA SD card NA LOM WLAN WIGIG M2 3042 PCI_CLK_LPC_1 EMC@ RC67 1 2 22_0402_5% RC225 0_0402_5% 4 3
SIO DOCK CLKBUFF DOCK
(HCA & SATA-Cache) CLK_PCI_LPDEBUG <20,36>
PCH_SPI_DIN 2 1 SPI_PCH_DIN 5 4 4
MEC DEBUG DEBUG
RC226 0_0402_5% 6 5 SIO
PCH_SPI_CLK 2 1 SPI_PCH_CLK 7 6 6
G12 Entry SD card NA LOM WLAN WIGIG NA CLK_PCI_MEC 2 1 PCH_SPI_CS0#
RC227
2
0_0402_5%
1
8 7
SPI_PCH_CS0# 9 8 8 MEC
12P_0402_50V8J @EMC@ RC228 0_0402_5% 10 9 TPM
CC12 PCH_SPI_DO2 2 1 SPI_PCH_DO2 11 10 10
G14 DSC SD card NA LOM WLAN GPU WIGIG CLK_PCI_LPDEBUG 2 1 PCH_SPI_DO3
RC229
2
0_0402_5%
1
12 11
SPI_PCH_DO3 13 12 12
12P_0402_50V8J @EMC@ RC230 0_0402_5% 14 13
M2 3042 CC13 15 14 14
G14 UMA SD card NA LOM WLAN WIGIG (HCA & SATA-Cache)
+3.3V_SPI
+3.3V_M 16 15
17 16 16
Reserve for EMI 2 1 18 17
RC231 0_0402_5% 19 18 18
G14D_En SD card NA LOM WLAN GPU WIGIG 20 19
20 20
Please place RC224~RC331 with JSPI1 at the same MB side. 21
G1 22
G14U_En SD card NA LOM WLAN WIGIG NA G2
G3
23
24
G4
A A
E-T_6700K-Y20N-00L
CONN@
0.1
5 4 3 2 1
5 4 3 2 1
D UC1C BDW_ULT_DDR3L UC1D BDW_ULT_DDR3L D

<19> DDR_B_D[0..63]
<18> DDR_A_D[0..63]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0
SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <18>
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AY31 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <18> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <19>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AW31 AN38 M_CLK_DDR2
AK62 SA_DQ2 SA_CLK#1 AY36 M_CLK_DDR#1 <18> AY29 SB_DQ1 SB_CK0 AK38 M_CLK_DDR2 <19>
DDR_A_D3 M_CLK_DDR1 DDR_B_D2 M_CLK_DDR#3
AH61 SA_DQ3 SA_CLK1 M_CLK_DDR1 <18> AW29 SB_DQ2 SB_CK#1 AL38 M_CLK_DDR#3 <19>
DDR_A_D4 DDR_B_D3 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <19>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_B_D4 AV31
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <18> SB_DQ4
DDR_A_D6 AK61 AW43 DDR_CKE1_DIMMA DDR_B_D5 AU31 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <18> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <19>
DDR_A_D7 AK60 AY42 DDR_B_D6 AV29 AU50 DDR_CKE3_DIMMB
AM63 SA_DQ7 SA_CKE2 AY43 AU29 SB_DQ6 SB_CKE1 AW49 DDR_CKE3_DIMMB <19>
DDR_A_D8 DDR_B_D7
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_B_D9 AW27 SB_DQ8 SB_CKE3
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <18> SB_DQ9
DDR_A_D11 AP62 AR32 DDR_CS1_DIMMA# DDR_B_D10 AY25 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <18> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <19>
DDR_A_D12 AM61 DDR_B_D11 AW25 AK32 DDR_CS3_DIMMB#
AM60 SA_DQ12 AP32 AV27 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <19>
DDR_A_D13 DDR_B_D12
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AU27 SB_DQ12 AL32
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_B_D14 AV25 SB_DQ13 SB_ODT0
SA_DQ15 SA_RAS DDR_A_RAS# <18> SB_DQ14
DDR_A_D16 AP58 AW34 DDR_A_WE# DDR_B_D15 AU25 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <18> SB_DQ15 SB_RAS DDR_B_RAS# <19>
DDR_A_D17 AR58 AU34 DDR_A_CAS# DDR_B_D16 AM29 AK35 DDR_B_WE#
AM57 SA_DQ17 SA_CAS DDR_A_CAS# <18> AK29 SB_DQ16 SB_WE AM33 DDR_B_WE# <19>
DDR_A_D18 DDR_B_D17 DDR_B_CAS#
AK57 SA_DQ18 AU35 AL28 SB_DQ17 SB_CAS DDR_B_CAS# <19>
DDR_A_D19 DDR_A_BS0 DDR_B_D18
SA_DQ19 SA_BA0 DDR_A_BS0 <18> SB_DQ18
DDR_A_D20 AL58 AV35 DDR_A_BS1 DDR_B_D19 AK28 AL35 DDR_B_BS0
SA_DQ20 SA_BA1 DDR_A_BS1 <18> SB_DQ19 SB_BA0 DDR_B_BS0 <19>
DDR_A_D21 AK58 AY41 DDR_A_BS2 DDR_B_D20 AR29 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <18> SB_DQ20 SB_BA1 DDR_B_BS1 <19>
DDR_A_D22 AR57 DDR_B_D21 AN29 AU49 DDR_B_BS2
AN57 SA_DQ22 AU36 DDR_A_MA[0..15] <18> AR28 SB_DQ21 SB_BA2 DDR_B_BS2 <19>
DDR_A_D23 DDR_A_MA0 DDR_B_D22
AP55 SA_DQ23 SA_MA0 AY37 AP28 SB_DQ22 AP40 DDR_B_MA[0..15] <19>
DDR_A_D24 DDR_A_MA1 DDR_B_D23 DDR_B_MA0
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
C DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5 C
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D32 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW56 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AY21 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..7] <18> SB_DQ38 SB_MA15
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D39 AU21
SA_DQ40 SA_DQSN0 SB_DQ39 DDR_B_DQS#[0..7] <19>
DDR_A_D41 AW54 AN62 DDR_A_DQS#1 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
AK42 SA_DQ48 AJ62 DDR_A_DQS[0..7] <18> AR21 SB_DQ47 SB_DQSN7
DDR_A_D49 DDR_A_DQS0 DDR_B_D48
SA_DQ49 SA_DQSP0 SB_DQ48 DDR_B_DQS[0..7] <19>
DDR_A_D50 AM43 AN61 DDR_A_DQS1 DDR_B_D49 AR22 AV30 DDR_B_DQS0
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_B_DQS1
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ57
DDR_A_D59 AK49 AR51 DDR_B_D58 AK18
SA_DQ59 SM_VREF_DQ0 +SM_VREF_DQ0 SB_DQ58
DDR_A_D60 AM48 AP51 DDR_B_D59 AL18
B SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ59 B
DDR_A_D61 AK48 DDR_B_D60 AK20
DDR_A_D62 AM51 SA_DQ61 DDR_B_D61 AM20 SB_DQ60
DDR_A_D63 AK51 SA_DQ62 DDR_B_D62 AR18 SB_DQ61
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63
BDW-ULT-DDR3L_BGA1168 BDW-ULT-DDR3L_BGA1168
3 OF 19 4 OF 19
A A
0.1
5 4 3 2 1
5 4 3 2 1
@ RC77 1 2 0_0402_5%
+3.3V_RUN
+3.3V_RUN +3.3V_ALW2
5
+3.3V_ALW_PCH
5
XDP_DBRESET# 1 PCH_PLTRST# 1 +RTC_CELL
P
1 2 ME_SUS_PWR_ACK B 4 SYS_RESET# B 4 PCH_PLTRST#_EC SIO_SLP_A# 1
P
O O PCH_PLTRST#_EC <20,27,30,36> B
1
RC79 10K_0402_5% 2 1 ME_RESET# 2 2 4 PM_APWROK_R
A A O
330K_0402_5%
1 2 SUSACK# @ RC80 8.2K_0402_5% @ UC4 UC5 @ RC304 PM_APWROK 1 2 PM_APWROK_L 2
<36> PM_APWROK A
2
RC81 10K_0402_5% 74AHC1G09GW_TSSOP5 TC7SH08FU_SSOP5~D 100K_0402_5% @ RC26 0_0402_5% UC6
RC78
1 2 SUS_STAT#/LPCPD# TC7SH08FU_SSOP5~D
3
@ RC82 10K_0402_5%
2
1 2
+PCH_VCCDSW3_3 <43> 1.05V_M_PWRGD
@ RC27 0_0402_5%
1
D DSWODVREN D
RPC1 Fix Intel 7260 can not detect issue.
4 5 PCH_PCIE_WAKE#
3 6
AC_PRESENT <36,9>
It will cause “floating” situation before 3V_RUN coming of AND gate
2 7
1 8
PCH_BATLOW# <9>
@ RC87 1 2 0_0402_5%
DSWODVREN - ON DIE DSW VR ENABLE
<27> PLTRST_USH#
10K_8P4R_5% @ RC88 1 2 0_0402_5% PCH_PLTRST#
1 2 <29> PLTRST_MMI#
PM_LANPHY_ENABLE @ RC89 1 2 0_0402_5%
HIGH = ENABLED (DEFAULT)
PM_LANPHY_ENABLE <12,28> <28> PLTRST_LAN#
@ RC92 10K_0402_5%
LOW = DISABLED
1 2 PCH_RSMRST#_Q
RC91 47K_0402_5%
UC1H BDW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
SUSACK# AK2 AW7 DSWODVREN JAPS1

<36> SUSACK# AC3 SUSACK DSWVRMEN AV5 1
SYS_RESET# PCH_DPWROK +3.3V_ALW_PCH
+3.3V_RUN AG2 SYS_RESET DPWROK AJ5 PCH_DPWROK <36> 2 1
SYS_PWROK PCH_PCIE_WAKE# SIO_SLP_S3#
<36> SYS_PWROK AY7 SYS_PWROK WAKE PCH_PCIE_WAKE# <35,36> 3 2
<15,36> RESET_OUT# PCH_PWROK +PCH_VCCDSW3_3 3
PM_APWROK_R AB5 SIO_SLP_S5# 4
1 2 ME_RESET# PCH_PLTRST# AG7 APWROK V5 CLKRUN# SIO_SLP_S4# 5 4
PLTRST CLKRUN/GPIO32 AG4 CLKRUN# <10,36> 6 5
@ RC95 8.2K_0402_5% SUS_STAT#/LPCPD# SIO_SLP_A#
SUS_STAT/GPIO61 AE6 SUSCLK_R 1 2 7 6
SUSCLK/GPIO62 SUSCLK <30> +PCH_VCCDSW3_3 7
AP5 SIO_SLP_S5# @ RC136 0_0402_5% 8
PCH_RSMRST#_Q AW6 SLP_S5/GPIO63 SIO_SLP_S5# <36> PCH_RTCRST# 9 8
<37> PCH_RSMRST#_Q AV4 RSMRST T8 PAD~D @ <6> PCH_RTCRST# 10 9
ME_SUS_PWR_ACK
<36> ME_SUS_PWR_ACK AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6 T9 PAD~D @ 11 10
SIO_PWRBTN# SIO_SLP_S4#
<36> SIO_PWRBTN# AJ8 PWRBTN SLP_S4 AT4 SIO_SLP_S4# <36> <36,39> POWER_SW#_MB 12 11
AC_PRESENT SIO_SLP_S3#
<36,9> AC_PRESENT AN4 ACPRESENT/GPIO31 SLP_S3 AL5 SIO_SLP_S3# <36> 13 12
PCH_BATLOW# SIO_SLP_A# SYS_RESET#
<9> PCH_BATLOW# SIO_SLP_S0# AF3 BATLOW/GPIO72 SLP_A AP4 SIO_SLP_SUS# SIO_SLP_A# <36> 14 13
SIO_SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 SIO_SLP_LAN# SIO_SLP_SUS# <36> SIO_SLP_S0# 15 14
<35> SIO_SLP_WLAN# SLP_WLAN/GPIO29 SLP_LAN SIO_SLP_LAN# <36,38> 16 15
17 16
18 17
19 18
20 GND
+3.3V_RUN BDW-ULT-DDR3L_BGA1168 GND
8 OF 19 CONN@
C CC17 CXDP@ ACES_50506-01841-P01 C
2 1
UC7 CXDP@
+1.05V_RUN
20130726 same as Goliad
0.1U_0402_25V6
14 +1.05V_RUN +1.05V_RUN
VCC
0.1U_0402_25V6
0.1U_0402_25V6
1 2 TDO_XDP 2 3 CPU_XDP_TDO
<6> PCH_JTAG_TDO 1A 1B
RC98 0_0402_5% JXDP1
1
@ CC18
@ CC19
CXDP@ 1 2
RUNPWROK 1 CPU_XDP_PREQ# 3 GND0 GND1 4 CFG17
1OE OBSFN_A0 OBSFN_C0 CFG17 <13>
CPU_XDP_PRDY# 5 6 CFG16 CFG16 <13>
2
PCH_JTAG_TDI 1 2 TDI_XDP_R 5 6 CPU_XDP_TDI 7 OBSFN_A1 OBSFN_C1 8
<6> PCH_JTAG_TDI 2A 2B 9 GND2 GND3 10
RC99 0_0402_5% <13> CFG0 CFG0 CFG8 CFG8 <13>
CXDP@ CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9
<13> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <13>
RUNPWROK 4 13 14
2OE CFG2 15 GND4 GND5 16 CFG10
<13> CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 <13>
PCH_JTAG_TMS 9 8 CPU_XDP_TMS <13> CFG3 CFG3 17 18 CFG11 CFG11 <13>
<6> PCH_JTAG_TMS 3A 3B 19 OBSDATA_A3 OBSDATA_C3 20
Place near JXDP1 XDP_OBS0_R 21 GND6 GND7 22 CFG19
OBSFN_B0 OBSFN_D0 CFG19 <13>
RUNPWROK 10 XDP_OBS1_R 23 24 CFG18 CFG18 <13>
3OE 25 OBSFN_B1 OBSFN_D1 26
TRST#_XDP 12 11 CPU_XDP_TRST# CFG4 27 GND8 GND9 28 CFG12
4A 4B <13> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <13>
<13> CFG5 CFG5 29 30 CFG13 CFG13 <13>
31 OBSDATA_B1 OBSDATA_D1 32
RC5 need to close to JCPU1 GND10 GND11
RUNPWROK 13 7 <13> CFG6 CFG6 33 34 CFG14 CFG14 <13>
<36> RUNPWROK 4OE GND OBSDATA_B2 OBSDATA_D2
RC102 1 2 1K_0402_5% <13> CFG7 CFG7 35 36 CFG15 CFG15 <13>
15 <15> H_VCCST_PWRGD 37 OBSDATA_B3 OBSDATA_D3 38
CXDP@
GND PAD H_CPUPWRGD @ RC103 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40
SIO_PWRBTN# 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42
43 HOOK1 ITPCLK#/HOOK5 44
74CBTLV3126BQ_DHVQFN14_2P5X3 VCC_OBS_AB VCC_OBS_CD
45 46 XDP_RST#_R 2 1 PCH_PLTRST#_EC
<15> CPU_PWR_DEBUG# 47 HOOK2 RESET#/HOOK6 48
reference Shark Bay ULT Validation Customer Debug Port SYS_PWROK XDP_DBRESET# RC106 1K_0402_5%
49 HOOK3 DBR#/HOOK7 50 CXDP@
Implementation Requirement Rev 1.0 51 GND14 GND15 52 TDO_XDP
2 1 <18,19,7> DDR_XDP_WAN_SMBDAT 53 SDA TD0 54
CPU_XDP_TRST# TRST#_XDP
<6> PCH_JTAG_TRST# <18,19,7> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56
0_0402_5% RC109 CXDP@ PCH_JTAG_TDI
<6> PCH_JTAG_TCK 57 TCK1 TDI 58
CPU_XDP_TCLK PCH_JTAG_TMS
+1.05V_VCCST 2 1 CPU_XDP_TCLK 59 TCK0 TMS 60 CFG3_R 1 2 CFG3
<6> PCH_JTAG_JTAGX GND16 GND17
0_0402_5% RC112 CXDP@ RC113 1K_0402_5%
1 2 H_CATERR# SAMTE_BSH-030-01-L-D-A CONN@ CXDP@ +1.05V_RUN
@ RC114 49.9_0402_1% 2 1 TDO_XDP
1 2 H_PROCHOT# 0_0402_5% RC115 @
B RC116 62_0402_5% TDO_XDP 2 1 B
PCH_JTAG_TDO 2 1 TDI_XDP_R +3.3V_ALW_PCH 51_0402_5% @ RC117
0_0402_5% RC118 @
2
1K_0402_5%
PCH_JTAG_TCK 2 1 CPU_XDP_TCLK
RC120
CXDP@
0_0402_5% RC119 @
H_PROCHOT#
Place near JXDP1.48
0.1U_0402_25V6
XDP_DBRESET#
1
1
@EMC@
CC21 CXDP@
CC20 SYS_PWROK
22P_0402_50V8J
0.1U_0402_25V6
2
2
1
@ CC22
UC1B BDW_ULT_DDR3L
2
EMI request add D61
H_CATERR# K61 PROC_DETECT MISC
PECI_EC N62 CATERR J62 CPU_XDP_PRDY#
<36> PECI_EC PECI PRDY K62 CPU_XDP_PREQ#
Place near JXDP1.47 +3.3V_RUN
PREQ E60 CPU_XDP_TCLK
PROC_TCK E61 CPU_XDP_TMS
H_CPUPWRGD 1 2 H_PROCHOT#_R K63 JTAG PROC_TMS E59 CPU_XDP_TRST# XDP_DBRESET# 2 1 RC122
<36,45,46> H_PROCHOT# PROCHOT PROC_TRST F63
RC121 56_0402_5% THERMAL CPU_XDP_TDI 1K_0402_5%
PROC_TDI
10K_0402_5%
100P_0402_50V8J
F62 CPU_XDP_TDO
PROC_TDO
1
+1.05V_RUN
@EMC@
RC123
CC83
1 H_CPUPWRGD C61
PROCPWRGD PWR CPU_XDP_TMS 2 1 @ RC124
J60 XDP_OBS0_R 51_0402_5%
BPM#0 H60 XDP_OBS1_R CPU_XDP_TDI 2 1 @ RC125
2
2 BPM#1 H61 XDP_OBS2_R PAD~D T10 @ 51_0402_5%

BPM#2 H62 XDP_OBS3_R PAD~D T11 @ CPU_XDP_PREQ# 2 1 @ RC126
SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R PAD~D T12 @ 51_0402_5%
SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_OBS5_R PAD~D T13 @ CPU_XDP_TDO 2 1 RC127
SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_OBS6_R PAD~D T14 @ 51_0402_5%
CAD Note: AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R PAD~D T15 @
<18> DDR3_DRAMRST#_CPU SM_DRAMRST BPM#7
Avoid stub in the PWRGD path <18> DDR_PG_CTRL AV61
SM_PG_CNTL1 CPU_XDP_TCLK 2 1 RC128
while placing resistors RC123 51_0402_5%
CPU_XDP_TRST# 2 1 @ RC129
A BDW-ULT-DDR3L_BGA1168 51_0402_5% A
2 OF 19
DDR3 COMPENSATION SIGNALS

200_0402_1% 2 1 RC130 SM_RCOMP0
121_0402_1% 2 1 RC131 SM_RCOMP1
100_0402_1% 2 1 RC132 SM_RCOMP2 DELL CONFIDENTIAL/PROPRIETARY

CAD Note: Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Trace width=12~15 mil, Spcing=20 mils TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (4/12)
Max trace length= 500 mil BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
UC1A BDW_ULT_DDR3L
C54 C45 EDP_CPU_LANE_N0

<25> DDI1_LANE_N0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <23> COMPENSATION PU FOR eDP
<25> DDI1_LANE_P0 B58 DDI1_TXP0 EDP_TXP0 A47 EDP_CPU_LANE_P0 <23>
EDP_CPU_LANE_N1
<25> DDI1_LANE_N1 C58 DDI1_TXN1 EDP_TXN1 B47 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <23>
<25> DDI1_LANE_P1 B55 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1 <23> +VCCIOA_OUT
<25> DDI1_LANE_N2 A55 DDI1_TXN2 C47
<25> DDI1_LANE_P2 A57 DDI1_TXP2 EDP_TXN2 C46 EDP_COMP 2 1
<25> DDI1_LANE_N3 B57 DDI1_TXN3 EDP_TXP2 A49 24.9_0402_1% RC133
<25> DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
<24> DDI2_LANE_N0 C50 DDI2_TXN0 A45 EDP_CPU_AUX#
CAD Note:Trace width=20 mils ,Spacing=25mil,
<24> DDI2_LANE_P0 DDI2_TXP0 EDP_AUXN EDP_CPU_AUX# <23>
<24> DDI2_LANE_N1
C53
DDI2_TXN1 EDP_AUXP
B45 EDP_CPU_AUX
EDP_CPU_AUX <23>
Max length=100 mils.
B54
<24> DDI2_LANE_P1 C49 DDI2_TXP1 D20 EDP_COMP
<24> DDI2_LANE_N2 B50 DDI2_TXN2 EDP_RCOMP A43
<24> DDI2_LANE_P2 A53 DDI2_TXP2 EDP_DISP_UTIL
<24> DDI2_LANE_N3 B53 DDI2_TXN3
<24> DDI2_LANE_P3 DDI2_TXP3
C C
1 OF 19
+3.3V_RUN
RPC15
5 4
SIO_RCIN# <12,36> BDW_ULT_DDR3L
6 3 UC1I +3.3V_RUN
CLKRUN# <36,9>
7 2
USH_DET# <12,27>
8 1 RPC2
IRQ_SERIRQ <12,36>
CPU_DPB_CTRLDAT 1 8
10K_8P4R_5% CPU_DPB_CTRLCLK 2 7
EDP_BIA_PWM B8 B9 CPU_DPB_CTRLCLK CPU_DPC_CTRLCLK 3 6
<23> EDP_BIA_PWM EDP_BKLCTL DDPB_CTRLCLK CPU_DPB_CTRLCLK <25>
PANEL_BKLEN A9 C9 CPU_DPB_CTRLDAT CPU_DPC_CTRLDAT 4 5
<23> PANEL_BKLEN EDP_BKLEN DDPB_CTRLDATA CPU_DPB_CTRLDAT <25>
ENVDD_PCH C6 eDP SIDEBAND D9 CPU_DPC_CTRLCLK
<23,36> ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK D11 CPU_DPC_CTRLCLK <24> 2.2K_0804_8P4R_5%
CPU_DPC_CTRLDAT
DDPC_CTRLDATA CPU_DPC_CTRLDAT <24>
U6 RPC20
<27,7> CONTACTLESS_DET# PIRQA/GPIO77
DGPU_PWROK P4 C5 CPU_DPB_AUX# CPU_DPB_AUX# 1 8
<6> DGPU_PWROK PIRQB/GPIO78 DDPB_AUXN CPU_DPB_AUX# <25>
1 2 ENVDD_PCH HDD_FALL_INT N4 B6 CPU_DPC_AUX# CPU_DPB_AUX 2 7
<12> HDD_FALL_INT PIRQC/GPIO79 DDPC_AUXN CPU_DPC_AUX# <24>
@ RC139 100K_0402_5% N2 DISPLAY B5 CPU_DPB_AUX CPU_DPC_AUX 3 6
<12> PCH_GPIO80 PIRQD/GPIO80 DDPB_AUXP CPU_DPB_AUX <25>
2 1 PCH_GPIO53 @ T16 PAD~D AD4 A6 CPU_DPC_AUX CPU_DPC_AUX# 4 5
PME DDPC_AUXP CPU_DPC_AUX <24>
@ RC140 1K_0402_5% PCIE
U7 100K_0804_8P4R_5%
<12> TOUCHPAD_INTR# GPIO55
L1
<12> PCH_GPIO52 GPIO52
L3 C8 DPB_HPD
R5 GPIO54 DDPB_HPD A8 DPC_HPD DPB_HPD <25>
L4 GPIO51 DDPC_HPD D6 DPC_HPD <24>
PCH_GPIO53 EDP_CPU_HPD
GPIO53 EDP_HPD EDP_CPU_HPD <23>
B EDP_CPU_HPD 100K_0402_5% 2 1 RC141 B
DPB_HPD 100K_0402_5% 2 1 RC142
9 OF 19
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
PCIE for UMA

D UC1K BDW_ULT_DDR3L D
PCIE_PRX_WIGIGTX_N5 F10 AN8 USBP0-

<30>
<30>
PCIE_PRX_WIGIGTX_N5
PCIE_PRX_WIGIGTX_P5
PCIE_PRX_WIGIGTX_P5 E10 PERN5_L0
PERP5_L0
USB2N0
USB2P0
AM8 USBP0+
USBP0- <31>
USBP0+ <31> -----> Ext Port 1 Charge PCB USB2 7
WIGIG ---> PCIE_PTX_WIGIGRX_N5 C23 AR7 USBP1-
USBP1- <32>
<30> PCIE_PTX_WIGIGRX_N5 C22 PETN5_L0 USB2N1 AT7
PCIE_PTX_WIGIGRX_P5 USBP1+
<30> PCIE_PTX_WIGIGRX_P5
F8
PETP5_L0 USB2P1
AR8 USBP2-
USBP1+ <32> -----> Ext Port 3 G12 UMA WWAN
PERN5_L1 USB2N2 USBP2- <30>
E8 AP8 USBP2+
PERP5_L1 USB2P2 USBP2+ <30> -----> WLAN/BT
B23
A23 PETN5_L1 USB2N3
AR10
AT10
USBP3-
USBP3+
USBP3- <31>
G12 Entry NA
PETP5_L1 USB2P3 USBP3+ <31> -----> Ext Port 2
H10 AM15 USBP4-
G10 PERN5_L2
PERP5_L2
USB2N4
USB2P4
AL15 USBP4+
USBP4- <23>
USBP4+ <23> -----> Touch G14 DSC WWAN
B21 AM13 USBP5-
PETN5_L2 USB2N5 USBP5- <23>
C21 AN13 USBP5+
E6
PETP5_L2 USB2P5
AP11 USBP6-
USBP5+ <23> -----> Camera G14 UMA WWAN
PERN5_L3 USB2N6 USBP6- <27>
F6 AN11 USBP6+
PERP5_L3 USB2P6 USBP6+ <27> -----> USH
B22
A21 PETN5_L3 USB2N7
AR13
AP13
G14D_En NA
PETP5_L3 USB2P7 -----> WWAN
PCIE_PRX_GLANTX_N3 G11
<28>
<28>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PRX_GLANTX_P3 F11 PERN3
PERP3 USB3RN1
G20
H20
USB3RN1 <31>
G14U_En NA
10/100/1G LAN ---> PCIE_PTX_GLANRX_N3 C29 USB3RP1 USB3RP1 <31>
<28> PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3 B30 PETN3 PCIE USB C33
USB3TN1 <31>
-----> Ext USB3 Port 1 Charge
C <28> PCIE_PTX_GLANRX_P3 PETP3 USB3TN1 B34 C
USB3TP1 USB3TP1 <31>
PCIE_PRX_WLANTX_N4 F13
<30> PCIE_PRX_WLANTX_N4 PERN4
PCIE_PRX_WLANTX_P4 G13 E18
<30> PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 USB3RN2 <32>
F18
WLAN (Mini Card 2)---> PCIE_PTX_WLANRX_N4 B29 USB3RP2 USB3RP2 <32>
<30> PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4 A29 PETN4 B33
USB3TN2 <32>
-----> Ext USB3 Port 3
<30> PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 A33
USB3TP2 USB3TP2 <32>
PCIE_PRX_MMITX_N1 G17
<29> PCIE_PRX_MMITX_N1 PERN1/USB3RN3
PCIE_PRX_MMITX_P1 F17
<29> PCIE_PRX_MMITX_P1 PERP1/USB3RP3
MMI --> PCIE_PTX_MMIRX_N1 C30
<29> PCIE_PTX_MMIRX_N1 C31 PETN1/USB3TN3 AJ10
PCIE_PTX_MMIRX_P1 USBRBIAS
<29> PCIE_PTX_MMIRX_P1 PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10
<31> USB3RN4 PERN2/USB3RN4 RSVD
G15 AM10
<31> USB3RP4 PERP2/USB3RP4 RSVD
B31
<31> USB3TN4 PETN2/USB3TN4
A31
<31> USB3TP4 PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1#
USB_OC0# <31> -----> USB Port0 (JUSB1) +3.3V_ALW_PCH
OC1/GPIO41 USB_OC1# <12,32> -----> USB Port1 (JUSB3)
AH2 USB_OC2#
OC2/GPIO42 USB_OC2# <12,31> -----> USB Port3 (JUSB2)
E15 AV3 USB_OC3#
RSVD OC3/GPIO43 USB_OC3# <12>
E13 RPC19
RC149 1 2 3.01K_0402_1% PCH_PCIE_RCOMP A27 RSVD 4 5
+PCH_AUSB3PLL PCIE_RCOMP <12> PCH_GPIO44
B27 USB_OC0# 3 6
PCIE_IREF 2 7
<7> PCH_SMB_ALERT#
1 8
<12,37> KB_DET#
10K_8P4R_5%
11 OF 19
B B
USBRBIAS
PCB PCIE1 PCIE2 PCIE3 PCIE4 PCIE5 PCIE6
22.6_0402_1%
1
RC152
G12 UMA SD card NA LOM WLAN WIGIG M2 3042
(HCA & SATA-Cache)
2
G12 Entry SD card NA LOM WLAN WIGIG NA
CAD NOTE:
G14 DSC SD card NA LOM WLAN GPU WIGIG Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
G14 UMA SD card NA LOM WLAN WIGIG M2 3042 mils.
(HCA & SATA-Cache)
G14D_En SD card NA LOM WLAN GPU WIGIG

G14U_En SD card NA LOM WLAN WIGIG NA
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
+PCH_VCCDSW3_3
2 1 LAN_WAKE#
RC153 10K_0402_5% +1.05V_VCCST
H_THERMTRIP# 2 1
1K_0402_5% RC25
+3.3V_RUN
D D
2 1 MPHYP_PWR_EN +3.3V_RUN
RC155 100K_0402_5%
2 1 SIO_EXT_SCI#
RC156 100K_0402_5% RPC17
PCH_GPIO76 5 4
6 3
<30,7> WLANCLK_REQ#
7 2
BDW_ULT_DDR3L <10> PCH_GPIO80
UC1J 8 1
10K_8P4R_5%
+3.3V_RUN CPPE# 2 1
PCH_GPIO76 P1 D60 H_THERMTRIP#_R @ 0_0402_5% 2 1 RC161 100K_0402_5% RC160
BMBUSY/GPIO76 THRMTRIP H_THERMTRIP# <36>
SIO_EXT_WAKE# AU2 V4 SIO_RCIN# FFS_INT2 2 1
<12,36> SIO_EXT_WAKE# GPIO8 RCIN/GPIO82 SIO_RCIN# <10,36>
1 2 TPM_PIRQ# AM7 T4 IRQ_SERIRQ 100K_0402_5% RC158
<28,9> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL/GPIO12 SERIRQ IRQ_SERIRQ <10,36>
RC247 10K_0402_5% HOST_ALERT1_R_N AD6 CPU/ AW15 PCH_OPI_COMP PCH_GPIO67 2 1
Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 10K_0402_5% RC163
<7> PCH_GPIO16 GPIO16 RSVD
TPM_PIRQ# T3 AB21 PCH_GPIO68 2 1
<27> TPM_PIRQ# GPIO17 RSVD
AD5 10K_0402_5% RC164
LAN_WAKE# AN5 GPIO24
<28,36> LAN_WAKE# GPIO27
AD7 RPC16
PCH_NFC_RST for Goliad NFC_IRQ AN3 GPIO28 CAM_MIC_CBL_DET# 5 4
GPIO26 R6 GC6_EVENT#_Q PCH_GPIO69 6 3
MEDIACARD_RST# AG6 GSPI0_CS/GPIO83 L6 GPU_GC6_FB_EN GC6_EVENT#_Q 7 2
PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85 PCH_GPIO87 8 1
SLATE_MODE AL4 GPIO57 GSPI0_MISO/GPIO85 L8 BBS_BIT
GPIO58 GSPI0_MOSI/GPIO86 @ T109 PAD~D
PCH_GPIO59 AT5 R7 PCH_GPIO87 10K_8P4R_5%
PCH_GPIO44 AK4 GPIO59 GPIO GSPI1_CS/GPIO87 L5 3.3V_TP_EN
<11> PCH_GPIO44 GPIO44 GSPI1_CLK/GPIO88
AB6 N7 RPC3
<29> MEDIACARD_IRQ# GPIO47 GSPI1_MISO/GPIO89 3.3V_TS_EN <23>
DIMM_DET U4 K2 TOUCH_PANEL_INTR# 5 4
+3.3V_ALW_PCH GPIO48 GSPI_MOSI/GPIO90 3.3V_HDD_EN <20>
C PCH_GPIO49 Y3 J1 CPPE# 6 3 C
@ T22 PAD~D GPIO49 UART0_RXD/GPIO91 <10> PCH_GPIO52
TOUCH_PANEL_INTR# P3 K3 CPUSB# 3.3V_TP_EN 7 2
<23> TOUCH_PANEL_INTR# GPIO50 UART0_TXD/GPIO92
MPHYP_PWR_EN Y2 J2 GPU_GC6_FB_EN 8 1
<38> MPHYP_PWR_EN HSIOPC/GPIO71 UART0_RTS/GPIO93
KB_DET# AT3 SERIAL IO G1
<11,37> KB_DET# GPIO13 UART0_CTS/GPIO94
RPC10 PCH_GPIO14 AH4 K4 10K_8P4R_5%
4 5 @ T21 PAD~D 3.3V_CAM_EN# AM4 GPIO14 UART1_RXD/GPIO0 G2 FFS_INT2
USB_OC2# <11,31> <23> 3.3V_CAM_EN# GPIO25 UART1_TXD/GPIO1
3 6 SIO_EXT_SMI# AG5 J3 LCD_CBL_DET# RPC4
PCH_GPIO46 <12> <36> SIO_EXT_SMI# GPIO45 UART1_RST/GPIO2 LCD_CBL_DET# <23>
2 7 SLATE_MODE AG3 J4 LCD_CBL_DET# 5 4
<12> PCH_GPIO46 GPIO46 UART1_CTS/GPIO3
1 8 F2 I2C0_SDA CPUSB# 6 3
PCH_GPIO73 <7> I2C0_SDA/GPIO4
PCH_GPIO9 AM3 F3 I2C0_SCL 3.3V_TS_EN 7 2
10K_8P4R_5% PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA_VMM PCH_GPIO85 8 1
@ T27 PAD~D GPIO10 I2C1_SDA/GPIO6
P2 F1 I2C1_SCL_VMM
RPC5 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 USH_DET# 10K_8P4R_5%
SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 USH_DET# <10,27>
4 5 SIO_EXT_SMI# L2 F4 CAM_MIC_CBL_DET#
<20> HDD_DEVSLP DEVSLP1/GPIO38 SDIO_CMD/GPIO65 CAM_MIC_CBL_DET# <23>
3 6 PCH_GPIO9 SIO_EXT_SCI# N5 D3 PCH_GPIO66 RPC8
<36> SIO_EXT_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
2 7 MEDIACARD_RST# SPKR V2 E4 PCH_GPIO67 I2C1_SDA_VMM 1 8
<21> SPKR SPKR/GPIO81 SDIO_D1/GPIO67
1 8 MEDIACARD_IRQ# C3 PCH_GPIO68 I2C1_SCL_VMM 2 7
SDIO_D2/GPIO68 E2 PCH_GPIO69 I2C0_SCL 3 6
10K_8P4R_5% SDIO_D3/GPIO69 I2C0_SDA 4 5
RPC7 BDW-ULT-DDR3L_BGA1168 2.2K_0804_8P4R_5%

4 5 10 OF 19
USB_OC3# <11>
3 6 RPC9
SIO_EXT_WAKE# <12,36>
2 7 5 4
USB_OC1# <11,32> <10> HDD_FALL_INT
1 8 PCH_GPIO57 6 3
<30,7> WIGIGCLK_REQ#
7 2
<10> TOUCHPAD_INTR#
10K_8P4R_5% 8 1
<6> SATA2_PCIE6_L1
10K_8P4R_5%
2 1 PCH_GPIO59 +3.3V_RUN +3.3V_RUN

B RC245 100K_0402_5% B
1
1
1K_0402_5%
10K_0402_5%
@ RC176
@ RC302
2 1 3.3V_CAM_EN#
RC174 100K_0402_5%
2 1 NFC_IRQ +3.3V_ALW_PCH +3.3V_RUN
RC175 100K_0402_5%
2
2 1 MPHYP_PWR_EN PCH_OPI_COMP 1 2
1
1
@ RC171
1K_0402_5%
1K_0402_5%
10K_0402_5% PCH_GPIO66 DIMM_DET 49.9_0402_1% RC178
RC179
@ RC180
1
10K_0402_5%
RC303
2
HOST_ALERT1_R_N SPKR
2
TOP-BLOCK SWAP OVERRIDE DIMM Detect TLS CONFIDENTIALITY No Reboot on TCO Timer expiration
HIGH ENABLE HIGH 1 DIMM HIGH ENABLE HIGH ENABLE
LOW(DEFAULT) DISABLE LOW 2 DIMM LOW(DEFAULT) DISABLE LOW(DEFAULT) DISABLE
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
CFG STRAPS for CPU

UC1S BDW_ULT_DDR3L CFG0
1
1K_0402_1%
@ RC183
CFG0 AC60 AV63 PAD~D T28 @
<9> CFG0 CFG0 RSVD_TP PAD~D T29 @
CFG1 AC62 AU63
<9> CFG1
2
AC63 CFG1 RSVD_TP
<9> CFG2 CFG2
AA63
<9> CFG3 CFG3 PAD~D T30 @
CFG4 AA60 C63
<9> CFG4 CFG4 RSVD_TP PAD~D T31 @
Y62 C62
<9> CFG5 CFG5 RSVD_TP
Y61 B43
<9> CFG6 CFG6 RSVD
Y60
<9>
<9>
CFG7
CFG8
CFG8 V62 CFG7 A51 PAD~D T33 @ EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG9 V61 CFG8 RSVD_TP B51 PAD~D T34 @
<9> CFG9 CFG9 RSVD_TP
CFG10 V60
<9> CFG10
U60 CFG10 L60 PAD~D T35 @ 1:(Default) Normal Operation; No stall
<9> CFG11
T63 CFG11 RSVD_TP CFG0
<9>
<9>
CFG12
CFG13
T62 CFG12 RESERVED N60 0:Lane Reversed
T61 CFG13 RSVD
<9> CFG14 CFG14
C T60 W23 C
<9> CFG15 CFG15 RSVD Y22
AA62 RSVD AY15 PROC_OPI_RCOMP
<9> CFG16 CFG16 PROC_OPI_RCOMP
U63 CFG1
<9> CFG18 CFG18
AA61 AV62
<9> CFG17 CFG17 RSVD
U62 D58
<9> CFG19 CFG19 RSVD
1
1K_0402_1%
@ RC184
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
A5 VSS
RSVD P20
2
E1 RSVD R20
D1 RSVD RSVD
J20 RSVD
H18 RSVD
TDI_IREF B12 RSVD
TD_IREF
PCH/PCH LESS MODE SELECTION
19 OF 19
1:(Default) Normal Operation
CFG1
0:Lane Reversed
2 1 CFG_RCOMP
RC185 49.9_0402_1%
1 2 TDI_IREF PROC_OPI_RCOMP 1 2
RC186 8.2K_0402_1% 49.9_0402_1% RC187
B B
CFG10 CFG9 CFG8 CFG4
1
1
1
1K_0402_1%
1K_0402_1%
@ RC189
1K_0402_1%
1K_0402_5%
@ RC188
@ RC190
RC191
2
2
2
SAFE MODE BOOT NO SVID PROTOCOL CAPABLE VR CONNECTED ALLOW THE USE OF NOA ON LOCKED UNITS Display Port Presence Strap
1: POWER FEATURES ACTIVATED DURING 1: VRS support SVID protocol are present 1: Enable(Default): Noa will be disable in
1 : Disabled; No Physical Display Port
RESET 0:No VR support SVID is present locked units and enable in un-locked
CFG10 CFG9 CFG8 CFG4 attached to Embedded Display Port
0: POWER FEATURES (ESPECIALLY CLOCK The chip will not generate(OR Respond to) units
0: Enable Noa will be available pegardless of
0 : Enabled; An external Display Port device is
GATINE ARE NOT ACTIVATED SVID activity the locking of the unit
connected to the Embedded Display Port
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
2
1 1
0_0402_5% @ RC192
UC1Q BDW_ULT_DDR3L
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 DC_TEST_A4
DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 DC_TEST_A60
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 DC_TEST_A62 2
2 1
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 DC_TEST_AV1 0_0402_5% @ RC193
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 DC_TEST_AW1 2 1
B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 0_0402_5% @ RC194
DC_TEST_B62_B63 B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
4
DC_TEST_C1_C2 C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 DC_TEST_AW63
DAISY_CHAIN_NCTF_AW63
C BDW-ULT-DDR3L_BGA1168 C
17 OF 19
3
2 1
0_0402_5% @ RC195
Package Daisy Chain:

1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R BDW_ULT_DDR3L
N23
RSVD R23
RSVD T23
AT2 RSVD
RSVD U10
AU44 RSVD
AV44 RSVD
B RSVD B
D15
RSVD AL1
RSVD AM11
RSVD AP7
F22 RSVD
RSVD AU10
H22 RSVD
RSVD AU15
J21 RSVD
RSVD AW14
RSVD AY14
RSVD
18 OF 19
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
ESD Request
+1.05V_RUN +VCCIO_OUT +VCC_CORE +1.35V_MEM
1 2
2 1 @EMC@ CC23 22U_0603_6.3V6M
+1.05V_RUN @ RC196 0_0603_5% +1.35V_MEM
VDDQ DECOUPLING
+1.05V_RUN +VCC_CORE
RESISTOR STUFFING OPTIONS ARE
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2
D RC197 PROVIDED FOR TESTING PURPOSES @EMC@ CC79 22U_0603_6.3V6M D
1
@ CC25
@ CC26
@ CC30
@ CC33
150_0402_5%
CC27
CC28
CC29
CC31
CC32
CC34
1 2
@EMC@ CC84 22U_0603_6.3V6M
2
CPU_PWR_DEBUG# +1.05V_RUN +3.3V_RUN
1 2
1
10K_0402_5%
@EMC@ CC85 22U_0603_6.3V6M

@ RC198
H_VCCST_PWRGD
2
+1.05V_VCCST
1
@EMC@
1
+VCC_CORE
10K_0402_5%
@ RC199
2 CC24 UC1L BDW_ULT_DDR3L
100P_0402_50V8J
L59 C36
+1.35V_MEM J58 RSVD VCC C40
2
RSVD VCC C44
H_VR_EN 2 1 H_VR_READY AH26 VCC C48
1.5K_0402_5% RC201 AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
+1.05V_VCCST AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
VDDQ VCC
2
+3.3V_ALW
1K_0402_5%
AY35 E31
VDDQ VCC
RC202
C AY40 E33 C
UC8 AY44 VDDQ VCC E35
1 5 1 2 AY50 VDDQ VCC E37
NC VCC @ CC35 0.1U_0402_25V6 VDDQ VCC E39
1
2 F59 VCC E41
<36,9> RESET_OUT# A +VCC_CORE VCC VCC
4 H_VCCST_PWRGD N58 E43
3 Y AC58 RSVD VCC E45
GND RSVD VCC E47
74AUP1G07GW_TSSOP5 VCCSENSE E63 VCC E49
AB23 VCC_SENSE VCC E51
A59 RSVD VCC E53
+VCCIO_OUT VCCIO_OUT VCC
+VCCIOA_OUT E20 E55
AD23 VCCIOA_OUT VCC E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
+1.05V_VCCST H_CPU_SVIDALRT# L62 VCC F36
SVID ALERT <45> VIDSCLK
VIDSCLK
VIDSOUT
N63
L63
VIDALERT
VIDSCLK
VIDSOUT
HSW ULT POWER VCC
VCC
VCC
F40
F44
H_VCCST_PWRGD B59 F48
<9> H_VCCST_PWRGD VCCST_PWRGD VCC
1
75_0402_1%
H_VR_EN F60 F52

<45> H_VR_EN VR_EN VCC
RC204
H_VR_READY C59 F56

CAD Note: Place the PU resistors close to CPU <45> H_VR_READY VR_READY VCC G23
RC204 close to CPU 300 - D63 VCC G25
H59 VSS VCC G27
1500mils <9> CPU_PWR_DEBUG#
2
P62 PWR_DEBUG VCC G29

2 1 H_CPU_SVIDALRT# P60 VSS VCC G31
<45> VIDALERT_N @ T74 PAD~D RSVD_TP VCC
43_0402_5% RC207 @ T75 P61 G33
PAD~D RSVD_TP VCC
@ T76 N59 G35
PAD~D RSVD_TP VCC
@ T77 N61 G37
PAD~D RSVD_TP VCC
T59 G39
+1.05V_VCCST AD60 RSVD VCC G41
B
SVID DATA AD59 RSVD
RSVD
VCC
VCC
G43 B
110_0402_1%
AA59 G45
RSVD VCC
1
AE60 G47
CAD Note: Place the PU resistors close to CPU RSVD VCC
RC208
AC59 G49
RC208close to CPU 300 - 1500mils AG58 RSVD VCC G51
U59 RSVD VCC G53
V59 RSVD VCC G55
2
RSVD VCC G57

VIDSOUT AC22 VCC H23
<45> VIDSOUT +1.05V_VCCST VCCST VCC
AE22 J23
AE23 VCCST VCC K23
VCCST VCC K57
AB57 VCC L22
+VCC_CORE VCC VCC
AD57 M23
AG57 VCC VCC M57
C24 VCC VCC P57
VCC_SENSE +VCC_CORE C28
C32
VCC
VCC
VCC
VCC
VCC
VCC
U57
W57
1
100_0402_1%
RC209
12 OF 19
+1.05V_RUN +1.05V_VCCST
@ PJP23
2
1 2
22U_0603_6.3V6M
VCCSENSE PAD-OPEN1x1m
<45> VCCSENSE
1U_0402_6.3V6K
1
1
CC36
@
CC37
CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU

2
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
+1.05V_M +1.05V_RUN
PAD-OPEN1x1m
+1.05V_MODPHY @ +1.05V_MODPHY_PCH
PJP51
1 2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
@EMC@ CC41
330U_D3_2.5VY_R6M
@EMC@ CC42
1 1
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@ CC39
+ + +
CC40 place near K9;
1
1
1
@ CC43
CC44
CC40
CC44 place near L10
2
2 2
2
2
2
CC43 place near M9
D
VCCHSIO D
S0 Iccmax = 1.838A
+RTC_CELL
CC48,CC49, CC50 place near AG10

+1.05V_MODPHY
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
+PCH_AUSB3PLL UC1M BDW_ULT_DDR3L
1
1
@
LC1
CC48
CC49
CC50
1 2 K9
+1.05V_RUN +1.05V_MODPHY_PCH VCCHSIO
2.2UH_LQM2MPN2R2NG0L_30% L10
2
VCCHSIO
2
22U_0603_6.3V6M
22U_0603_6.3V6M M9
VCCHSIO
1
N8 HSIO RTC AH11

VCC1_05 VCCSUS3_3 +PCH_RTC_VCCSUS3_3
CC51
CC47
1U_0402_6.3V6K
P9 AG10
CC47 place near B18 +PCH_AUSB3PLL
B18 VCC1_05 VCCRTC AE7 +DCPRRTC 1 2
2
VCCUSB3PLL DCPRTC
@ CC53
B11 CC52 0.1U_0402_10V7K
VCCUSB3PLL +PCH_ASATA3PLL VCCSATA3PLL +3.3V_M
S0 Iccmax = 41mA
2
Y20 SPI Y8 CC54 place near Y8
RSVD VCCSPI
0.1U_0402_10V7K
AA21 OPI
W21 VCCAPLL
+V1.05S_APLLOPI VCCAPLL
@ CC54
AG14
VCCASW +1.05V_M
AG13
VCCASW +1.05V_RUN
CC59 and CC60 place near
2
+1.05V_MODPHY +PCH_ASATA3PLL +3.3V_ALW_PCH J13 USB3
LC2 DCPSUS3 J11 J11; CC58 place near AE8 +PCH_VCCDSW 2 1
1 2 VCC1_05 H11 RC211 5.11_0402_1%
VCC1_05 +1.05V_M
10U_0603_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% AH14 HDA H15
+PCH_VCCDSW_R
CC57 place near AH14 VCCHDA VCC1_05
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
AE8
VCC1_05
1
1
1
0.1U_0402_10V7K
CC59
AF22
CC56 place near B11 VCC1_05
1
22U_0603_6.3V6M
CC58
CC60
AH13 VRM AG19 +PCH_VCCDSW
DCPSUS2 DCPSUSBYP
1
+3.3V_ALW_PCH
CC55
CC56
1U_0402_6.3V6K
@ CC62
CORE AG20
VCCSATA3PLL 1
2
DCPSUSBYP
2
1
CC57
AE9 CC61 CC62 place near AE9
2
VCCASW
CC61
AF9
S0 Iccmax = 42mA VCCASW
2
CC63 place near AC9 AC9 AG8

CC65 place near AG19
2
AA9 VCCSUS3_3 GPIO/LPC
VCCASW AD10 2
22U_0603_6.3V6M +3.3V_RUN VCCSUS3_3 DCPSUS1
1U_0402_6.3V6K
AH10 AD8
C +PCH_VCCDSW3_3 VCCDSW3_3 DCPSUS1 C
V8
VCC3_3
1
+3.3V_RUN
CC63
CC64 place near V8 W9
VCC3_3
1
2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back J15
VCCTS1_5 +1.5V_RUN
22U_0603_6.3V6M
0.1U_0402_10V7K
CC65
THERMAL SENSOR K14
2
VCC3_3
1
K16
VCC3_3
2
1
+1.05V_RUN +V1.05S_APLLOPI CC64
2013/06/10 refer 6L_WP chnage to float,6/14 change back
+3.3V_RUN
CC66
LC3
2
1 2 +1.05V_RUN J18
+PCH_VCC1P05
2
2.2UH_LQM2MPN2R2NG0L_30% K19 VCCCLK SERIAL IO U8
VCCCLK VCCSDIO CC69 place near U8
100U_1206_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
A20 T9
+PCH_VCCACLKPLL VCCACLKPLL VCCSDIO
J17
CC68 place near AA21 VCCCLK
1
1
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
CC70 close to Pin J17 R21
VCCCLK
CC67
CC68
CC69
T21 LPT LP POWER
VCCAPLL CC71 close to Pin R21 VCCCLK
1
1
K18 SUS OSCILLATOR AB8 2 1
RSVD DCPSUS4
2
2
CC70
CC71
M20 0_0402_5% RC212 @
S0 Iccmax = 57mA V21 RSVD +1.05V_RUN
2
AE20 RSVD AC20 +3.3V_ALW

+3.3V_ALW_PCH VCCSUS3_3 RSVD
AE21 AG16 CC72 place near AG16
VCCSUS3_3 VCC1_05
1U_0402_6.3V6K
USB2 AG17 2 1
VCC1_05
1U_0402_6.3V6K
0_0402_5% RC213 @
CC72
1
CC73
CC73 place near AH11
2
2
+PCH_VCCDSW3_3 +PCH_VCCDSW 13 OF 19
VCCSUS3_3
1 2 +1.05V_RUN +PCH_VCC1P05
S0 Iccmax = 63mA
LC4
@ CC97 0.47U_0402_10V6K 1 2
2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
1U_0402_6.3V6K
CC97 place near AH10

CC78 place near J18
1
intel DG Rev 1.2 , page 500

CC77
CC78
VCCCLK
47.3 Boot Strap Capacitor
2
B S0 Iccmax = 200mA B
Reminder below power rail need isolation for layout refer

+3.3V_ALW_PCH +PCH_VCCDSW3_3
attach file for more detail that from Intel review feedback.
1 2
@ RC216 0_0402_5% +PCH_VCCACLKPLL
+1.05V_RUN
+3.3V_ALW LC5
1 2
@ RC2171 2 0_0402_5% 2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
CC80 place near AH10 CC82 place near A20

1
1
CC81
CC82
1
@ CC80
VCCDSW3_3 VCCACLKPLL
2
S0 Iccmax = 114mA S0 Iccmax = 31mA

2
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
UC1N BDW_ULT_DDR3L UC1O BDW_ULT_DDR3L
A11 AJ35 AP22 AV59

A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
A40 VSS VSS AJ52 AP39 VSS VSS AW4 UC1P BDW_ULT_DDR3L
A44 VSS VSS AJ54 AP48 VSS VSS AW40 H17
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D33 VSS H57
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D34 VSS VSS J10
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D35 VSS VSS J22
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D37 VSS VSS J59
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D38 VSS VSS J63
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D39 VSS VSS K1
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D41 VSS VSS K12
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D42 VSS VSS L13
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D43 VSS VSS L15
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D45 VSS VSS L17
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D46 VSS VSS L18
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D5 VSS VSS L61
AE5 VSS VSS AL29 AT13 VSS VSS AY33 D50 VSS VSS L7
AE58 VSS VSS AL31 AT35 VSS VSS AY4 D51 VSS VSS M22
C AF11 VSS VSS AL33 AT37 VSS VSS AY51 D53 VSS VSS N10 C
AF12 VSS VSS AL36 AT40 VSS VSS AY53 D54 VSS VSS N3
AF14 VSS VSS AL39 AT42 VSS VSS AY57 D55 VSS VSS P59
AF15 VSS VSS AL40 AT43 VSS VSS AY59 D57 VSS VSS P63
AF17 VSS VSS AL45 AT46 VSS VSS AY6 D59 VSS VSS R10
AF18 VSS VSS AL46 AT49 VSS VSS B20 D62 VSS VSS R22
AG1 VSS VSS AL51 AT61 VSS VSS B24 D8 VSS VSS R8
AG11 VSS VSS AL52 AT62 VSS VSS B26 E11 VSS VSS T1
AG21 VSS VSS AL54 AT63 VSS VSS B28 E17 VSS VSS T58
AG23 VSS VSS AL57 AU1 VSS VSS B32 F20 VSS VSS U20
AG62 VSS VSS AM1 AU20 VSS VSS B40 F34 VSS VSS U9
AG63 VSS VSS AM17 AU22 VSS VSS B44 F38 VSS VSS V10
AH17 VSS VSS AM23 AU24 VSS VSS B48 F42 VSS VSS V3
AH19 VSS VSS AM31 AU26 VSS VSS B52 F46 VSS VSS V7
AH20 VSS VSS AM52 AU28 VSS VSS B56 F50 VSS VSS W20
AH22 VSS VSS AN17 AU30 VSS VSS B60 F54 VSS VSS W22
AH24 VSS VSS AN23 AU33 VSS VSS C11 F58 VSS VSS Y10
AH28 VSS VSS AN31 AU51 VSS VSS C14 F61 VSS VSS Y59
AH30 VSS VSS AN32 AU53 VSS VSS C18 G18 VSS VSS Y63
AH32 VSS VSS AN35 AU55 VSS VSS C20 G22 VSS VSS
AH34 VSS VSS AN36 AU57 VSS VSS C25 G3 VSS
AH36 VSS VSS AN39 AU59 VSS VSS C27 G5 VSS V58
AH38 VSS VSS AN40 AV14 VSS VSS C38 G6 VSS VSS AH46
AH40 VSS VSS AN42 AV16 VSS VSS C39 G8 VSS VSS V23
AH42 VSS VSS AN43 AV20 VSS VSS C57 H13 VSS VSS E62
AH44 VSS VSS AN45 AV24 VSS VSS D12 VSS VSS_SENSE AH16 VSSSENSE <45>
AH49 VSS VSS AN46 AV28 VSS VSS D14 VSS
AH51 VSS VSS AN48 AV33 VSS VSS D18 BDW-ULT-DDR3L_BGA1168
AH53 VSS VSS AN49 AV34 VSS VSS D2 16 OF 19
AH55 VSS VSS AN51 AV36 VSS VSS D21
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26 VSSSENSE 1 2
AJ23 VSS VSS AN7 AV46 VSS VSS D27 RC218 100_0402_1%
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS VSS
15 OF 19
CAD Note: RC218 SHOULD BE PLACED CLOSE TO CPU
14 OF 19
A A
LA-A972P
5 4 3 2 1
5 4 3 2 1
<8> DDR_A_DQS#[0..7]
<8> DDR_A_D[0..63]
H=4mm
<8> DDR_A_DQS[0..7] +DIMM1_VREF_DQ +1.35V_MEM
Reverse Type +1.35V_MEM
JDIMM1 CONN@
<8> DDR_A_MA[0..15] 1 2
VREF_DQ VSS
2.2U_0402_6.3V6M
3 4 DDR_A_D9
VSS DQ4
0.1U_0402_25V6
DDR_A_D13 5 6 DDR_A_D12
D DDR_A_D8 7 DQ0 DQ5 8 D
DQ1 VSS
1
9 10 DDR_A_DQS#1
VSS DQS0#
CD5
CD1
11 12 DDR_A_DQS1
13 DM0 DQS0 14 +1.35V_MEM
Note: VSS VSS
2
Check voltage tolerance of DDR_A_D10 17 DQ2 DQ6 18 DDR_A_D11
VREF_DQ at the DIMM socket 19 DQ3 DQ7 20
Layout Note: VSS VSS
1
470_0402_5%
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
Place near JDIMM1 DQ9 DQ13
RD2
25 26
DDR_A_DQS#3 27 VSS VSS 28
DDR_A_DQS3 29 DQS1# DM1 30 DDR3_DRAMRST#
2
31 DQS1 RESET# 32
DDR_A_D30 33 VSS VSS 34 DDR_A_D27
DQ10 DQ14
0.1U_0402_25V6
DDR_A_D31 35 36 DDR_A_D26 1 2
+1.35V_MEM 37 DQ11 DQ15 38 <19> DDR3_DRAMRST# DDR3_DRAMRST#_CPU <9>
@ RD3 0_0402_5%
VSS VSS
@ CD6
DQ16 DQ20
1
43 DQ17 DQ21 44
VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_DQS#5 45 46
2
DDR_A_DQS5 47 DQS2# DM2 48
DQS2 VSS
1
1
49 50 DDR_A_D42
VSS DQ22
CD7
CD2
CD3
CD8
CD9
CD4
CD10
CD11
DDR_A_D47 53 DQ18 DQ23 54
DQ19 VSS
2
2
55 56 DDR_A_D52 CAD NOTE
DDR_A_D51 57 VSS DQ28 58 DDR_A_D53
DDR_A_D50 59 DQ24 DQ29 60 PLACE THE CAP NEAR TO DIMM RESET PIN
61 DQ25 VSS 62 DDR_A_DQS#6
63 VSS DQS3# 64 DDR_A_DQS6 +1.35V_MEM
65 DM3 DQS3 66
DDR_A_D49 67 VSS VSS 68 DDR_A_D54
DQ26 DQ30
1
1.8K_0402_1%
DQ27 DQ31
RD4
71 72
+1.35V_MEM VSS VSS
C +DIMM1_VREF_DQ +SM_VREF_DQ0 C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
2
75 76
VDD VDD
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
77 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14 1 2
<8> DDR_A_BS2 81 BA2 A14 82 RD5 2_0402_1%
VDD VDD
1
@ CD13
@ CD16
0.022U_0402_16V7K
DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11
1
1
CD12
CD14
CD15
CD17
CD18
CD19
CD20
1.8K_0402_1%
+ DDR_A_MA9 85 86 DDR_A_MA7
A9 A7
1
87 88
VDD VDD
1
RD6
CD21
A8 A6
2
93 A5 A4 94
VDD VDD
2
2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
A1 A0
1
24.9_0402_1%
99 100
VDD VDD
RD7
M_CLK_DDR0 101 102 M_CLK_DDR1
<8> M_CLK_DDR0 103 CK0 CK1 104 M_CLK_DDR1 <8>
M_CLK_DDR#0 M_CLK_DDR#1
<8> M_CLK_DDR#0 105 CK0# CK1# 106 M_CLK_DDR#1 <8>
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8>
2
DDR_A_BS0 109 110 DDR_A_RAS#
<8> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <8>
DDR_A_WE# 113 VDD VDD 114 DDR_CS0_DIMMA#
<8> DDR_A_WE# 115 WE# S0# 116 DDR_CS0_DIMMA# <8>
DDR_A_CAS# M_ODT0
Layout Note: <8> DDR_A_CAS# 117 CAS# ODT0 118
DDR_A_MA13 119 VDD VDD 120 M_ODT1
Place near DDR_CS1_DIMMA# 121 A13 ODT1 122 +SM_VREF_CA_DIMM
<8> DDR_CS1_DIMMA# 123 S1# NC 124
JDIMM1.203,204 125 VDD VDD 126
127 TEST VREF_CA 128
VSS VSS
0.1U_0402_25V6
2.2U_0402_6.3V6M
DDR_A_D1 131 DQ32 DQ36 132 DDR_A_D4
DQ33 DQ37
1
CD22
CD23
133 134
DDR_A_DQS0 137 DQS4# DM4 138
DQS4 VSS
2
139 140 DDR_A_D3
B +0.675V_DDR_VTT DDR_A_D2 141 VSS
DQ34
DQ38
DQ39
142 DDR_A_D7
+5V_ALW
DDR3L SODIMM ODT GENERATION B
DDR_A_D6 143 144
145 DQ35 VSS 146 DDR_A_D18
DDR_A_D21 147 VSS DQ44 148 DDR_A_D19 +1.35V_MEM QD1
DQ40 DQ45
1
L2N7002WT1G_SC-70-3
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
220K_0402_5%
DDR_A_D20 149 150
DQ41 VSS
RD9
151 152 DDR_A_DQS#2
VSS DQS5#
1
153 154 DDR_A_DQS2 1 3 1 2 M_ODT0
S
DM5 DQS5
CD24
CD25
CD26
CD27
CD28
CD29
155 156 RD10 66.5_0402_1%

DDR_A_D17 157 VSS VSS 158 DDR_A_D22 1 2 M_ODT1
DQ42 DQ46
2
2
DDR_A_D16 159 160 DDR_A_D23 RD11 66.5_0402_1%
G
DQ43 DQ47
2
161 162 1 2
163 VSS VSS 164 M_ODT2 <19>
DDR_A_D36 DDR_A_D37 0.675V_DDR_VTT_ON RD12 66.5_0402_1%
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32 1 2
167 DQ49 DQ53 168 M_ODT3 <19>
RD13 66.5_0402_1%
DQS6# DM6
2
2M_0402_5%
DDR_A_DQS4 171 172
DQS6 VSS
@ RD14
173 174 DDR_A_D35
DDR_A_D34 175 VSS DQ54 176 DDR_A_D39
DDR_A_D38 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D63
VSS DQ60
1
DDR_A_D62 181 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7 +1.35V_MEM
189 DM7 DQS7 190
DDR_A_D60 191 VSS VSS 192 DDR_A_D56 UD1
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57 1 5 1 2
195 DQ59 DQ63 196 NC VCC @ CD30 0.1U_0402_25V6
1 2 197 VSS VSS 198 2
199 SA0 EVENT# 200 <9> DDR_PG_CTRL A 4
@ RD15 0_0402_5% +3.3V_RUN 0.675V_DDR_VTT_ON
1 2 201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <19,7,9> 3 Y 0.675V_DDR_VTT_ON <42>
203 SA1 SCL 204 DDR_XDP_WAN_SMBCLK <19,7,9> GND
@ RD16 0_0402_5% +0.675V_DDR_VTT +0.675V_DDR_VTT
VTT VTT 74AUP1G07GW_TSSOP5
2.2U_0402_6.3V6M
0.1U_0402_25V6
205 206
207 GND1 GND2 208
A BOSS1 BOSS2 A
1
1
@ CD31
CD32
LCN_DAN06-K4406-0103
2
20130730 SP07000LT00 CIS Link OK

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR3L
LA-A972P
5 4 3 2 1
5 4 3 2 1
H=4mm
+DIMM2_VREF_DQ
Reverse Type
+1.35V_MEM +1.35V_MEM
<8> DDR_B_DQS#[0..7]
JDIMM2 CONN@
1 2
<8> DDR_B_D[0..63] 3 VREF_DQ VSS 4 DDR_B_D12
VSS DQ4
2.2U_0402_6.3V6M
DDR_B_D8 5 6 DDR_B_D9
<8> DDR_B_DQS[0..7] DQ0 DQ5
0.1U_0402_25V6
DDR_B_D14 7 8
9 DQ1 VSS 10 DDR_B_DQS#1
<8> DDR_B_MA[0..15] Note: VSS DQS0#
1
D 11 12 DDR_B_DQS1 D
Check voltage tolerance of DM0 DQS0
CD33
CD34
13 14
VREF_DQ at the DIMM socket DDR_B_D10 15 VSS VSS 16 DDR_B_D13
2
DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D15 +1.35V_MEM
19 DQ3 DQ7 20
DDR_B_D28 21 VSS VSS 22 DDR_B_D25
DQ8 DQ12
1
1.8K_0402_1%
25 DQ9 DQ13 26
VSS VSS
RD18
DDR_B_DQS#3 27 28
DDR_B_DQS3 29 DQS1# DM1 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# <18> +SM_VREF_CA_DIMM +SM_VREF_CA
Layout Note:
2
VSS VSS
0.1U_0402_25V6
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
Place near JDIMM2 DQ11 DQ15
@ CD35
37 38 1 2
DDR_B_D40 39 VSS VSS 40 DDR_B_D45 RD19 2_0402_1%
DQ16 DQ20
0.022U_0402_16V7K
2
DQ17 DQ21
1.8K_0402_1%
43 44
VSS VSS
1
DDR_B_DQS#5 45 46
DQS2# DM2
1
RD20
CD36
DDR_B_DQS5 47 48
49 DQS2 VSS 50 DDR_B_D47
DDR_B_D46 51 VSS DQ22 52 DDR_B_D43
2
+1.35V_MEM DDR_B_D42 53 DQ18 DQ23 54
DQ19 VSS CAD NOTE
2
55 56 DDR_B_D61
VSS DQ28 PLACE THE CAP NEAR TO DIMM RESET PIN
1
24.9_0402_1%
DQ24 DQ29
RD21
DDR_B_D57 59 60
DQ25 VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
61 62 DDR_B_DQS#7
63 VSS DQS3# 64 DDR_B_DQS7
DM3 DQS3
1
1
65 66
2
VSS VSS
CD37
CD38
CD39
CD40
CD41
CD42
CD43
CD44 DDR_B_D59 67 68 DDR_B_D63

DQ27 DQ31
2
71 72
VSS VSS
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB <8>
C
77 VDD VDD 78 DDR_B_MA15 +1.35V_MEM C
DDR_B_BS2 79 NC A15 80 DDR_B_MA14
<8> DDR_B_BS2 BA2 A14
1
1.8K_0402_1%
81 82
+1.35V_MEM DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
RD22
87 A9 A7 88
DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6 +DIMM2_VREF_DQ +SM_VREF_DQ1
A8 A6
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
DDR_B_MA5 91 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD VDD 96 DDR_B_MA2 1 2
A3 A2
1
@ CD46
@ CD47
DDR_B_MA1 97 98 DDR_B_MA0 RD23 2_0402_1%

A1 A0
1
1
CD45
CD48
CD49
CD50
CD51
CD52
CD53
0.022U_0402_16V7K
+ 99 100
VDD VDD
1.8K_0402_1%
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <8>
1
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<8> M_CLK_DDR#2 M_CLK_DDR#3 <8>
2
CK0# CK1#
1
RD24
CD54
105 106
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <8>
DDR_B_BS0 109 110 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS#
2
111 112 DDR_B_RAS# <8>
2
DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
24.9_0402_1%
DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <18>
1
117 118
VDD VDD
RD25
DDR_B_MA13 119 120
121 A13 ODT1 122 M_ODT3 <18> +SM_VREF_CA_DIMM
DDR_CS3_DIMMB#
<8> DDR_CS3_DIMMB# S1# NC
123 124
125 VDD VDD 126
TEST VREF_CA
2
127 128
VSS VSS
0.1U_0402_25V6
2.2U_0402_6.3V6M
133 DQ33 DQ37 134
VSS VSS
1
CD55
CD56
DDR_B_DQS#0 135 136
Layout Note: DDR_B_DQS0 137 DQS4# DM4 138
Place near VSS DQ38
2
DDR_B_D7 143 DQ34 DQ39 144
B
JDIMM2.203,204 145 DQ35 VSS 146 DDR_B_D16 B
DDR_B_D20 149 DQ40 DQ45 150
155 DM5 DQS5 156
+0.675V_DDR_VTT DDR_B_D22 157 VSS VSS 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
161 DQ43 DQ47 162
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
DQ49 DQ53
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
167 168
DDR_B_DQS#4 169 VSS VSS 170
DQS6# DM6
1
1
CD57
CD58
CD59
CD60
CD61
CD62
DDR_B_DQS4 171 172

DQ50 DQ55
2
DDR_B_D39 177 178

179 DQ51 VSS 180 DDR_B_D51
DDR_B_D49 183 DQ56 DQ61 184
189 DM7 DQS7 190
DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50
195 DQ59 DQ63 196
+3.3V_RUN 197 VSS VSS 198
199 SA0 EVENT# 200
+3.3V_RUN VDDSPD SDA DDR_XDP_WAN_SMBDAT <18,7,9>
2 1 201 202
SA1 SCL DDR_XDP_WAN_SMBCLK <18,7,9>
@ RD27 0_0402_5% 203 204
+0.675V_DDR_VTT VTT VTT +0.675V_DDR_VTT
1
0_0402_5%
@ RD28
205 206
GND1 GND2
2.2U_0402_6.3V6M
0.1U_0402_25V6
207 208
BOSS1 BOSS2
1
1
@ CD63
2
A A
CD64
LCN_DAN06-K4406-0103
2
20130730 SP07000LT00 CIS Link OK
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR3L
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_HDD source
+3.3V_RUN
C UZ11 C
3
<12> 3.3V_HDD_EN ON
1
@ PJP4
@ RN6 +3.3V_RUN 1 7 +3.3V_HDD_UZ11 1 2 +3.3V_HDD
VIN VOUT
10K_0402_5%
2 8
VIN VOUT PAD-OPEN1x3m
2
0.1U_0402_10V7K
2
3.3V_HDD_EN
CZ64
+5V_ALW 4 @
VBIAS
1
1
RN7 6 GND 9
10K_0402_5% CT GND
1
470P_0402_50V7K
CZ65
TPS22967DSGR_SON8_2X2
2
+3.3V_HDD
Mini mSATA H=4
1 2 HDD_DEVSLP
@ RN1 10K_0402_5% +3.3V_HDD +3.3V_HDD
JMINI3 CONN@
1 2
3 1 2 4
5 3 4 6
B 7 5 6 8 LPC_LFRAME# B
7 8 LPC_LFRAME# <36,7>
9 10 LPC_LAD3 LPC_LAD3 <36,7>
11 9 10 12 LPC_LAD2
11 12 LPC_LAD2 <36,7>
13 14 LPC_LAD1 LPC_LAD1 <36,7>
15 13 14 16 LPC_LAD0
15 16 LPC_LAD0 <36,7>
PCH_PLTRST#_EC 17 18
<27,30,36,9> PCH_PLTRST#_EC 17 18
19 20
<36,7> CLK_PCI_LPDEBUG 21 19 20 22
2 1 SATA_PRX_DTX_P1_C 23 21 22 24
<6> SATA_PRX_DTX_P1 23 24
<6> SATA_PRX_DTX_N1 CN3 2 1 .01U_0402_16V7K SATA_PRX_DTX_N1_C 25 26
CN4 .01U_0402_16V7K 27 25 26 28
29 27 28 30
CN5 2 1 .01U_0402_16V7K SATA_PTX_DRX_N1_C 31 29 30 32
<6> SATA_PTX_DRX_N1 31 32
CN6 2 1 .01U_0402_16V7K SATA_PTX_DRX_P1_C 33 34
<6> SATA_PTX_DRX_P1 33 34
35 36
37 35 36 38
+3.3V_HDD 39 37 38 40
41 39 40 42
43 41 42 44 HDD_DEVSLP
43 44 HDD_DEVSLP <12>
0.1U_0402_25V6
0.1U_0402_25V6
45 46
47 45 46 48
@ 49 47 48 50
1 1 49 50
CN1
CN2
HDD_DET# 51 52
<6> HDD_DET# 51 52
53 54
2 2 GND1 GND2
LCN_DAN08-52406-0500
A A
Place near JMINI3
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONN
LA-A972P
5 4 3 2 1
2 1
+5V_RUN_AUDIO +1.5V_RUN +3.3V_RUN_AUDIO +5V_RUN_AUDIO
1
0_0805_5%
place close to pin26
0_0603_5%
@ RA3
0_0603_5%
@ RA4
@ RA39
LA5
+VDDA_AVDD1 1 2
0.1U_0402_25V6
10U_0603_6.3V6M
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) +3.3V_RUN_AUDIO BLM15PX600SN1D_2P
CA10,CA11 close to pin1
Internal Speakers Header
2
1
1
place close to pin40
CA8
CA9
+1.5V_RUN_AUDIO
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
CONN@
4.7U_0603_6.3V6K
40 mils trace keep 20 mil spacing
2
JSPK1 1 place close to pin36
1
CA10
CA11
INT_SPK_L+ EMC@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L+ 1
1
CA50
CA16
0.1U_0402_25V6
INT_SPK_L- EMC@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2
4.7U_0603_6.3V6K
2 place close to pin41 place close to pin46
INT_SPK_R+ EMC@ LA8 1 2 BLM15PX330SN1D_2P INT_SPKR_R+ 3 1
3
1
2
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
INT_SPK_R- EMC@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 4 UA1
4
CA17
CA18
1 26
DVDD AVDD1
1
L03ESDL5V0CC3-2_SOT23-3
5 40
GND AVDD2
2
2
3
2
CA45
CA46
CA47
CA48
6 9
GND DVDD-IO
@EMC@ DA6
@EMC@ DA7
2
ACES_50279-0040N-001 36 +VDDA_PVDD
CPVDD
@EMC@ CA22
@EMC@ CA23
@EMC@ CA19
@EMC@ CA24
20130730 CIS Link OK 41

PVDD1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
PCH_AZ_CODEC_BITCLK 6 46 +5V_RUN_PVDD
<6> PCH_AZ_CODEC_BITCLK BCLK PVDD2
1
PCH_AZ_CODEC_SDOUT 5
<6> PCH_AZ_CODEC_SDOUT SDATA-OUT 13 JD1
HP/LINE1 JD(JD1)
2
10 14
<6> PCH_AZ_CODEC_SYNC SYNC MIC2/LINE2 JD(JD2)
1
Place RA9 close to UA1 15
1 2 PCH_AZ_SDIN0_R 8 SPDIFO/FRONT JD(JD3)/GPIO3
<6> PCH_AZ_CODEC_SDIN0 RA9 33_0402_5% SDATA-IN
PCH_AZ_CODEC_RST# 11
<6> PCH_AZ_CODEC_RST# RESETB 32 AUD_OUT_L 1 2 AUD_HP_OUT_L
HPOUT-L(PORT-I-L) 33 AUD_OUT_R RA7 1 2 24.9_0402_1% AUD_HP_OUT_R
MIC1_R 21 HPOUT-R(PORT-I-R) RA8 24.9_0402_1%
Close to UA1 LINE1-R(PORT-C-R)
B MIC1_L 22 AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width B
+MIC2_VREF_OUT +MIC1_VREFO_R 30 LINE1-L(PORT-C-L)
+MIC1_VREFO_L 31 LINE1-VREFO-R 42 INT_SPK_L+
2 1 RING2 23 LINE1-VREFO-L SPK-OUT-L+ 43 INT_SPK_L-
RA5 2.2K_0402_5% 24 LINE2-R(PORT-E-R) SPK-OUT-L- 45 INT_SPK_R+
2 1 SLEEVE LINE2-L(PORT-E-L) SPK-OUT-R+ 44 INT_SPK_R-
RA6 2.2K_0402_5% SPK-OUT-R-
16
MONO-OUT +MIC2_VREF_OUT
2
Close to UA1 pin6 GPIO0/DMIC-DATA DMIC0 <23>
1U_0603_10V4Z
+MIC2_VREF_OUT
29 3 DMIC_CLK_L 1 2 DMIC_CLK
MIC2-VREFO GPIO1/DMIC-CLK DMIC_CLK <23>
1
17 48
@
RING2 EMC@ RA14 33_0402_5%
MIC2-L(PORT-F-L)/RING SPDIF-OUT/GPIO2
CA26
PCH_AZ_CODEC_BITCLK SLEEVE & RING2 trace width require least SLEEVE 18
MIC2-R(PORT-F-R)/SLEEVE
@EMC@ RA17
19
MIC_CAP Place CA29 close to Codec
2
40mil and its length as short as possible. 2 1 37
CBP
1
33_0402_5%
CA25 10U_0603_6.3V6M 35 2 1
1 2 20 CBN CA29 1U_0603_10V6K
+3.3V_RUN_AUDIO NC place close to pin12
@ RA41 0_0402_5%
AUD_NB_MUTE# 47 CA35 2 1 2.2U_0603_6.3V6K 2 1 1 2
<35> AUD_NB_MUTE# PDB SPKR <12>
1U_0603_10V6K
28 CA27 0.1U_0402_25V6 RA12 1K_0402_5%
VREF
2
12 AUD_PC_BEEP 2 1 1 2
PCBEEP BEEP <36>
1
10P_0402_50V8J
@EMC@ CA33
+3.3V_RUN_AUDIO
1 2 27 34 2 1 CA28 0.1U_0402_25V6 RA13 1K_0402_5% DMIC_CLK
LDO1-CAP CPVEE
CA31
RA18 10K_0402_5% 39 CA49 1U_0603_10V6K
@EMC@
LDO2-CAP
1
RA44 100K_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22P_0402_50V8J
7
LDO3-CAP
1
1
1
2
CA51
CA52
CA53
CA30
1 2 4 25
0_0402_5% DVSS AVSS1
2
@ RA40 38
AVSS2
2
49
GND
2
ALC3234-CG_MQFN48_6X6
place close to pin3

Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM.
JD1
Place closely to Pin 13. +MIC1_VREFO_R @ PJP9
+5V_RUN
1 2 +5V_RUN_AUDIO
RB751S40T1G_SOD523-2
+MIC1_VREFO_L
PAD-OPEN1X2m
2
L2N7002WT1G_SC-70-3
@ PJP10
DA4
DA5
+3.3V_RUN
1 2 +3.3V_RUN_AUDIO
1
D
2
QA1
AUD_HP_NB_SENSE <35>
2 1
2 1
0.1U_0402_25V6
4.7K_0402_5%
4.7K_0402_5%
G PAD-OPEN1x1m
1
S
3
CA41
@
RA24
RA25
place at AGND and DGND plane
Add for solve
2
pop noise and 1 2

HP-Out-Right Nokia-MIC
1
detect issue CA43
RA35 @EMC@ MIC1_L 1 2 AUD_HP_OUT_L
0_0402_5%
HP-Out-Left iPhone-MIC
1 2 CA44 4.7U_0603_6.3V6K
MIC1_R 1 2 AUD_HP_OUT_R
RA36 @EMC@ @ PJP6
0_0402_5% 1 2 4.7U_0603_6.3V6K
1 2
RA37 @EMC@ PAD-OPEN1x2m +3.3V_RUN_AUDIO

0_0402_5%
Global Headset
1
RA1
10K_0402_5%
Combo Jack
JHP1
2
7
3
RING2 EMC@ LA10 1 2 BLM15PX330SN1D_2P RING2_R
AUD_HP_OUT_L EMC@ LA2 1 2 AUD_HP_OUT_L1 1
BLM15BD601SN1D_2P
A Normal A
SLEEVE 5 Open
+RTC_CELL AUD_HP_NB_SENSE 6
BLM15BD601SN1D_2P
AUD_HP_OUT_R EMC@ LA3 1 2 AUD_HP_OUT_R1 2
SLEEVE EMC@ LA11 1 2 BLM15PX330SN1D_2P 4
1
100K_0402_5%
SINGA_2SJ3080-003111F
RA21
@EMC@ CA1
@EMC@ CA2
@EMC@ CA3
@EMC@ CA4
EMC@ EMC@ EMC@ CONN@
3
CA12 680P_0402_50V7K
@EMC@
CA13 680P_0402_50V7K
@EMC@
DA1 DA2 DA3
CIS Link OK
1
DMN66D0LDW-7_SOT363-6
680P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
680P_0402_50V7K
1 1 1 1 1 1
2
5 RA2
100K_0402_5%
QA2B
2 2 2 2 2 2
4
2
2 AUD_NB_MUTE# 1 Place CA12 & CA13
1
close to Audio Jack
QA2A
Digital Mic (Goliad MLK no single Mic)

EMI De-pop
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Codec _ALC3235
LA-A972P
2 1
2 1
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP 1.2 MST HUB
LA-A972P
2 1
5 4 3 2 1
+3.3V_TSP
ACES_50398-04041-001 DLW21HN900HQ2L_4P
1 4 3
1 4 3 USBP4- <11>
2 USBP4_D-
2 3 USBP4_D+
3 4 1 2
4 1 2 USBP4+ <11>
5
5 TOUCH_PANEL_INTR# <12> LV27EMC@
6
6 7
7 DMIC0 <21>
8
8 9
9 DMIC_CLK <21>
3
10 +3.3V_RUN
10 11 +3.3V_CAM
3
11
100P_0402_50V8J
@EMC@ CA5
100P_0402_50V8J
@EMC@ CA6
12 USBP5_D-
D 12 13 USBP5_D+ DV4 D
13
1
14 @EMC@
14 CAM_MIC_CBL_DET# <12>
15 pin 15: LOOP_BACK AZC199-02SPR7G_SOT23-3
1
15 16
LED CONN
2
16 17
17 +BL_PWR_SRC
18
18 19 JLED1 CONN@
19 ESD depop location
20 8
20 21 EMC@ LV1 1 2 BIA_PWM GND2 7
21 22 DISP_ON BLM15BB221SN1D_2P~D 6 GND1
22 +5V_ALW
23 5 6
23 <39> BATT_WHITE_LED#
24 4 5
24 <39> BATT_YELLOW_LED#
25 3 4
25 <39> PANEL_HDD_LED#
26 2 3
26 EDP_CPU_HPD <10> <39> BREATH_WHITE_LED#
27 1 2
27 28 1
28 29 ACES_50277-0060N-001
29 LCD_TST <36>
30
30 31
31 +LCDVDD
32
32 33 EDP_CPU_AUX#_C CV1 2 1 0.1U_0402_10V7K
33 EDP_CPU_AUX# <10> 20130822
34 EDP_CPU_AUX_C CV2 2 1 0.1U_0402_10V7K
34 EDP_CPU_AUX <10>
35 EDP_CPU_LANE_P0_C CV3 2 1 0.1U_0402_10V7K
35 EDP_CPU_LANE_P0 <10>
41 36 EDP_CPU_LANE_N0_C CV4 2 1 0.1U_0402_10V7K
G1 36 EDP_CPU_LANE_N0 <10>
42 37 EDP_CPU_LANE_P1_C CV5 2 1 0.1U_0402_10V7K
G2 37 EDP_CPU_LANE_P1 <10>
43 38 EDP_CPU_LANE_N1_C CV6 2 1 0.1U_0402_10V7K
G3 38 EDP_CPU_LANE_N1 <10>
44 39
45 G4 39 40
G5 40 LCD_CBL_DET# <12>
JEDP1
CONN@
C
For Touchscreen C
+BL_PWR_SRC +LCDVDD +3.3V_CAM +3.3V_TSP +3.3V_RUN +3.3V_RUN +3.3V_TSP +3.3V_RUN

QV8
0.1U_0603_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_16V4Z
0.1U_0402_25V6
10K_0402_5%
LP2301ALT1G_SOT23-3
1
1
RV6
@
@
1 3
S
CV7
CV8
CZ1
CZ2
CA7
2
G
2
2
Close to JEDP1.24~27 Close to JEDP1.11,12 Close to JEDP1.33 Close to JEDP1.40 Close to JEDP1.1
L2N7002WT1G_SC-70-3
1
DV1 DV2 D
QV7
2
<12> 3.3V_TS_EN
3 EDP_BIA_PWM 3 G
EDP_BIA_PWM <10> PANEL_BKLEN <10>
S
3
BIA_PWM 1 DISP_ON 1
2 BIA_PWM_EC 2
BIA_PWM_EC <36> PANEL_BKEN_EC <35>
1
4.7K_0402_5%
4.7K_0402_5%
1
BAT54CW_SOT323-3 BAT54CW_SOT323-3
RV1
RV2
2
B B
WebCAM Backlight POWER +BL_PWR_SRC

LCDVDD POWER +LCDVDD
+3.3V_ALW
+PWR_SRC QV1 @ CV9 UV24
2 1 1
+3.3V_CAM +3.3V_RUN 6 VOUT 5
D
4 5 10U_0603_6.3V6M VIN
S
QZ1 2 DV3 2
GND
1000P_0402_50V7K
0.01U_0402_16V7K
LP2301ALT1G_SOT23-3 1 4
VIN
100K_0402_5%
0.1U_0603_50V7K
@
2
G
<36> LCD_VCC_TEST_EN
1
CV10
1 3 AO6405_TSOP6 1 EN_LCDPWR 3
D
EN
1
1
CV11
RV4
CV12
3 AP2821KTR-G1_SOT23-5
<10,36> ENVDD_PCH
2
2
100K_0402_5%
G
2
RV3
2nd source SA00003AR00
2
BAT54CW_SOT323-3
<12> 3.3V_CAM_EN#
PWR_SRC_ON
1
QV2
L2N7002WT1G_SC-70-3
1 2 1 3
D
change back to CCD_OFF at Goliad project RV5 47K_0402_5%
LZ1 EMC@
G
2
1 2 USBP5_D+
<11> USBP5+ 1 2
A A
<36> EN_INVPWR
4 3 USBP5_D-
<11> USBP5- 4 3
DLW21HN900HQ2L_4P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP CONN & Touch screen
LA-A972P
5 4 3 2 1
5 4 3 2 1
+5V_RUN
+VHDMI_VCC
0.1U_0402_16V4Z
<25> HDMI_CLK_AUX HDMI_CLK_AUX 1 2
D RV7 2.2K_0402_5%
D
1
@
CV24
<25> HDMI_DAT_AUX# HDMI_DAT_AUX# 1 2
1
RV9 2.2K_0402_5% +VHDMI_VCC
IN
AP2330W-7_SC59-3
UV10
0.1U_0402_10V7K
10U_0603_6.3V6M
1
CV27
GND
OUT
@ CV30
LV3 EMC@
1 2 TMDS_CON_CLK
<25> HDMI_LANE_P3
2
1 2
3
<25> HDMI_LANE_N3
4
4 3
3 TMDS_CON_CLK#
HDMI connector
DLW21HN900HQ2L_4P
LV6 EMC@
1 2 TMDS_CON_P2 JHDMI1 CONN@
<25> HDMI_LANE_P2 1 2 19
<25> HDMI_HPD 18 HP_DET
4 3 TMDS_CON_N2 17 +5V
<25> HDMI_LANE_N2 4 3 +3.3V_RUN DDC/CEC_GND
HDMI_DAT_AUX# 16
DLW21HN900HQ2L_4P HDMI_CLK_AUX 15 SDA
14 SCL
LV10 EMC@ 2 1 HDMI_CEC 13 Reserved
1 2 TMDS_CON_P1 10K_0402_5% @ RV8 TMDS_CON_CLK# 12 CEC 20
<25> HDMI_LANE_P1 1 2 CK- GND
11 21
TMDS_CON_CLK 10 CK_shield GND 22
4 3 TMDS_CON_N1 TMDS_CON_N0 9 CK+ GND 23
<25> HDMI_LANE_N1 4 3 D0- GND
8
DLW21HN900HQ2L_4P TMDS_CON_P0 7 D0_shield
TMDS_CON_N1 6 D0+
D1-
C <25> HDMI_LANE_P0
1
LV12 EMC@
2 TMDS_CON_P0
TMDS_CON_P1
TMDS_CON_N2
5
4
3
D1_shield
D1+
C
1 2 2 D2-
TMDS_CON_P2 1 D2_shield
4 3 TMDS_CON_N0 D2+
<25> HDMI_LANE_N0 4 3 LCN_AUF05-1922S10-0019
DLW21HN900HQ2L_4P
20130730 DC232002PB0 CIS Link OK
+3.3V_RUN
0.1U_0402_16V4Z
@
1 +VDISPLAY_VCC
CV510
.01U_0402_16V7K
1
UV501
2
1
IN
2 1 mDP_LANE_P3_C
<10> DDI2_LANE_P3
CV509
CV501 0.1U_0402_10V7K
2 1 mDP_LANE_N3_C
B AUX/DDC SW for DDI2 to Mini DP <10> DDI2_LANE_N3

CV502 0.1U_0402_10V7K 2
B
2 1 mDP_LANE_P2_C
GND
<10> DDI2_LANE_P2
OUT
+3.3V_RUN CV503 0.1U_0402_10V7K
2 1 mDP_LANE_N2_C
<10> DDI2_LANE_N2
1 2 CV504 0.1U_0402_10V7K AP2337SA-7_SOT23-3
3
CV511
0.1U_0402_25V6
<10> DDI2_LANE_P1
CV505
2 1 mDP_LANE_P1_C
0.1U_0402_10V7K mDP connector
2 1 mDP_LANE_N1_C
<10> DDI2_LANE_N1
UV502 CV506 0.1U_0402_10V7K
CV512 1 14 JmDP1 CONN@
2 1 SW_mDP_AUX_C 2 BE0 VCC 13 2 1 mDP_LANE_P0_C 20
<10> CPU_DPC_AUX A0 BE3 <10> DDI2_LANE_P0 DP_PWR
CV507 0.1U_0402_10V7K 19
0.1U_0402_10V7K mDP_AUX_C 3 12 2 1 mDP_LANE_N0_C mDP_AUX#_C 18 GND 24
B0 A3 CPU_DPC_CTRLCLK <10> <10> DDI2_LANE_N0 AUX_CH_N GND4
CV508 0.1U_0402_10V7K mDP_LANE_N2_C 17 23
CV513 4 11 mDP_AUX_C 16 LANE2_N GND3 22
2 1 SW_mDP_AUX#_C 5 BE1 B3 10 mDP_LANE_P2_C 15 AUX_CH_P GND2 21
<10> CPU_DPC_AUX# A1 BE2 LANE2_P GND1
0.1U_0402_10V7K 14
mDP_AUX#_C 6 9 13 GND
B1 A2 CPU_DPC_CTRLDAT <10> GND
mDP_LANE_N3_C 12
7 8 mDP_LANE_N1_C 11 LANE3_N
GND B2 mDP_LANE_P3_C 10 LANE1_N
PI3C3125LEX_TSSOP14~D mDP_LANE_P1_C 9 LANE3_P
8 LANE1_P
+5V_RUN +3.3V_RUN 7 GND
DPB_MB_P14 6 GND
mDP_LANE_N0_C 5 CONFIG2
+3.3V_RUN 1 2 mDP_AUX#_C mDP_CA_DET 4 LANE0_N
RV501 100K_0402_5% mDP_LANE_P0_C 3 CONFIG1
LANE0_P
100K_0402_5%
1 2 mDP_AUX_C mDP_HPD 2
HOT-PLUG
1
RV502 100K_0402_5% 1
GND
RV507
1 2 DPB_MB_P14
RV503 5.1M_0402_5% ACON_MAR2E-20K1800
2
G
2 1 mDP_CA_DET
A RV504 1M_0402_5%
A
2
3 1 mDP_HPD 1 2 mDP_HPD
<10> DPC_HPD RV505 100K_0402_5%
mDP_CA_DET#
S
20130730 DC060008GB0 CIS Link OK

QV501
1
D L2N7002WT1G_SC-70-3
mDP_CA_DET 2
G
QV502
L2N7002WT1G_SC-70-3
S
3
mDP_CA_DET function
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
1 mDP BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
0 HDMI
LA-A972P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
1 1
1
CV61
CV62
CV66
CV69
+3.3V_RUN UV7
2
2 2 14 40
1 2 WIGIG_AUX# 28 VDD33 DP_D0p 39 WIGIG_LANE_P0 <30>
PCB DP SWITCH RV555 100K_0402_5% 41
56
VDD33
VDD33
DP_D0n
37
WIGIG_LANE_N0 <30>
1 2 PS8339B_IN_CA_DET VDD33 DP_D1p 36 WIGIG_LANE_P1 <30>

D @ RV68 100K_0402_5% PS8339B_DP_CFG0 44 DP_D1n WIGIG_LANE_N1 <30> D
G12 UMA PS8339+PS8338 1 2 WIGIG_AUX
PS8339B_MODE_SW 45
38
DP_CFG0/SCL_CTL
SW/SDA_CTL DP_D2p
34
33 WIGIG_LANE_P2 <30>
RV554 100K_0402_5% I2C_CTL_EN DP_D2n WIGIG_LANE_N2 <30>
1 2 PS8339B_OUT_CA_DET CV71 1 2 0.1U_0402_25V6 DDI1_LANE_P0_C 3 31
G12 Entry PS8339 RV67 1M_0402_5%
<10>
<10>
DDI1_LANE_P0
DDI1_LANE_N0
CV72 1 2 0.1U_0402_25V6 DDI1_LANE_N0_C 4 IN_D0p
IN_D0n
DP_D3p
DP_D3n
30 WIGIG_LANE_P3
WIGIG_LANE_N3
<30>
<30>
CV73 1 2 0.1U_0402_25V6 DDI1_LANE_P1_C 6 55
<10> DDI1_LANE_P1 IN_D1p DP_AUXp_SCL WIGIG_AUX <30>
CV74 1 2 0.1U_0402_25V6 DDI1_LANE_N1_C 7 54
G14 DSC PS8339+PS8338 <10> DDI1_LANE_N1
CV75 1 2 0.1U_0402_25V6 DDI1_LANE_P2_C 9
IN_D1n DP_AUXn_SDA
DP_HPD
32
WIGIG_AUX# <30>
WIGIG_HPD <30>
<10> DDI1_LANE_P2 IN_D2p
CV76 1 2 0.1U_0402_25V6 DDI1_LANE_N2_C 10
<10> DDI1_LANE_N2 IN_D2n 42 PS8339B_OUT_CA_DET
G14 UMA PS8339 +3.3V_RUN
<10> DDI1_LANE_P3
CV77 1
CV78 1
2 0.1U_0402_25V6
2 0.1U_0402_25V6
DDI1_LANE_P3_C
DDI1_LANE_N3_C
12
13 IN_D3p
DP_CA_DET
29 PS8339B_DP_CFG1
<10> DDI1_LANE_N3 IN_D3n DP_CFG1
CV79 1 2 0.1U_0402_25V6 CPU_DPB_AUX_C 52 19
G14D_En PS8339+PS8338 <10>
<10>
CPU_DPB_AUX
CPU_DPB_AUX#
CV80 1 2 0.1U_0402_25V6 CPU_DPB_AUX#_C 51 IN_AUXp
IN_AUXn
TMDS_CH0p
TMDS_CH0n
18
HDMI_LANE_P0
HDMI_LANE_N0
<24>
<24>
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1
1
<10> CPU_DPB_CTRLCLK CPU_DPB_CTRLCLK 50 22 HDMI_LANE_P1 <24>
CPU_DPB_CTRLDAT 49 IN_DDC_SCL TMDS_CH1p 21
@ RV51
@ RV54
RV55
@ RV56
RV57
@ RV58
@ RV60
G14U_En PS8339
@ RV551
<10> CPU_DPB_CTRLDAT IN_DDC_SDA TMDS_CH1n HDMI_LANE_N1 <24>

PS8339B_IN_CA_DET 11 25 HDMI_LANE_P2 <24>
IN_CA_DET TMDS_CH2p 24 HDMI_LANE_N2 <24>
2
2
PS8339B_TMDS_DDCBUF 5 TMDS_CH2n
<10> DPB_HPD IN_HPD 16 HDMI_LANE_P3 <24>
PS8339B_INPUT_EQ TMDS_CLKp 15
TMDS_CLKn HDMI_LANE_N3 <24>
2.2U_0402_6.3V6M
PS8339B_MODE 1 48 HDMI_CLK_AUX <24>
CEXT TMDS_SCL 47
TMDS_SDA HDMI_DAT_AUX# <24>
1
PS8339B_TMDS_PRE PS8339B_TMDS_DDCBUF 2
TMDS_DDCBUF
CV60
17
TMDS_HPD HDMI_HPD <24>
C PS8339B_TMDS_RT PS8339B_INPUT_EQ 8 C
2
PEQ 23 PS8339B_TMDS_RT
PS8339B_DP_CFG1 27 TMDS_RT 20 PS8339B_TMDS_PRE
REXT TMDS_PRE
1
PS8339B_DP_CFG0 46 26
4.99K_0402_1%
PD GND 35
RV50
PS8339B_MODE_SW PS8339B_MODE 53 GND 43
MODE GND 57
Thermal/GND
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2
1
1
PS8339BQFN56GTR2-A0_QFN56_7X7
@ RV52
@ RV61
RV62
@ RV64
RV63
RV65
RV66
@ RV550
@
2
MODE = L: Control Switching Mode, HDMI ID disable

= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable
TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis
B
TMDS_RT = L: Standard open drain driver B
= H: Open drain driver with termination resistors
TMDS_DDCBUF = L: DDC pass through

= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2

= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable

= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP to VGA & VGA Conn
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_M +3.3V_M_TPM
+3.3V_M_TPM @ PJP11
1 2
PAD-OPEN1x1m
0.1U_0402_25V6
4700P_0402_25V7K
2200P_0402_50V7K
2200P_0402_50V7K
+3.3V_SUS
1
1
@ CZ4
CZ5
CZ6
CZ7
C
UZ1 RZ8
1 2 USH_SMBCLK
2.2K_0402_5%
USH CONN C
2
1 2 USH_SMBDAT JUSH1 CONN@

3 12 RZ9 2.2K_0402_5% 1
10 VCC V_BAT 2 1
VCC <11> USBP6- 2
19 1 2 USH_PWR_STATE# 3
VCC <11> USBP6+ 3
24 1 RZ10 1M_0402_5% 4
VCC GPIO_1 2 5 4
GPIO_2 <36> USH_SMBCLK 5
17 6
GPIO_3 <36> USH_SMBDAT 6
6 7
RZ30 1 2 33_0402_5% SPI_DINTPM 26 GPIO-Express-00 7 <35> BCM5882_ALERT# 8 7
<7> PCH_SPI_DIN RZ29 1 2 33_0402_5% 23 MISO PP/GPIO 9 8
SPI_DOTPM
<7> PCH_SPI_DO MOSI 9
RZ26 1 2 33_0402_5% SPI_CLKTPM 21 +3.3V_SUS 10
<7> PCH_SPI_CLK SPI_CLK 10
@ RZ17 1 2 0_0402_5% PCH_SPI_CS2#_R 22 9 11
<7> PCH_SPI_CS2# SPI_CS# TESTBI 11
16 8 12
<20,30,36,9> PCH_PLTRST#_EC SPI_RST# TESTI 12
20 +3.3V_RUN 13
<12> TPM_PIRQ# PIRQ# 13
+5V_RUN 14
5 +5V_RUN +3.3V_RUN +3.3V_SUS 15 14
NBO_1 13 <9> PLTRST_USH# 16 15
NBO_2 <35> USH_PWR_STATE# 16
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
25 14 17
GND NBO_3 <10,7> CONTACTLESS_DET# 17
18 15 18
GND NBO_4 18
@
11 27 19 21
GND NBO_5 19 GND
1
CZ10
CZ11
@
SPI_CLKTPM 4 28 20 22
GND NBO_6 <10,12> USH_DET# 20 GND
CZ12
33_0402_5%
CONCR_205200FW010
2
2
@EMC@
AT97SC3205_TSSOP28~D
RZ35
1
0.1U_0402_25V6
Close to JUSH1
1
@EMC@
B B
CZ9
2
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH & TPM
LA-A972P
5 4 3 2 1
5 4 3 2 1
Layout Notice : Place bead as

+3.3V_LAN UL1 LAN_TX0+L RL21 1 2 5.6_0402_5% LAN_TX0+L_R
close UL4 as possible
1
1 2 TP_LAN_JTAG_TMS 48 13 LAN_TX0+ 1 2 LAN_TX0+L CL30 EMC@
@ RL1 10K_0402_5% <7> LANCLK_REQ# 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0- 1
EMC@ LL21 2
12NH_0603CS-120EJTS_5% LAN_TX0-L LAN_TX0-L RL22 1 2 5.6_0402_5% 3.3P_0402_50V8J LAN_TX0-L_R
<9> PLTRST_LAN# PE_RST_N MDI_MINUS0
2
1 2 TP_LAN_JTAG_TCK EMC@ LL22 12NH_0603CS-120EJTS_5%
@ RL2 10K_0402_5% 44 17 LAN_TX1+ 1 2 LAN_TX1+L
<7> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
2 1 LANCLK_REQ# 45 18 LAN_TX1- EMC@ 1
LL23 2
12NH_0603CS-120EJTS_5% LAN_TX1-L LAN_TX1+L RL23 1 2 5.6_0402_5% LAN_TX1+L_R
<7> CLK_PCIE_LAN# PE_CLKN MDI_MINUS1
PCIE
1
@ RL4 4.7K_0402_5% 2 1 PCIE_PRX_GLANTX_P3_C EMC@ LL24 12NH_0603CS-120EJTS_5%
MDI
<11> PCIE_PRX_GLANTX_P3
CL1 0.1U_0402_10V7K 38 20 LAN_TX2+ 1 2 LAN_TX2+L CL31 EMC@
2 1 PCIE_PRX_GLANTX_N3_C 39 PETp MDI_PLUS2 21 LAN_TX2- EMC@ 1
LL25 2
12NH_0603CS-120EJTS_5% LAN_TX2-L LAN_TX1-L RL24 1 2 5.6_0402_5% 3.3P_0402_50V8J LAN_TX1-L_R
<11> PCIE_PRX_GLANTX_N3 PETn MDI_MINUS2
2
CL2 0.1U_0402_10V7K EMC@ LL26 12NH_0603CS-120EJTS_5%
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_P3_C 41 23 LAN_TX3+ 1 2 LAN_TX3+L
<11> PCIE_PTX_GLANRX_P3 PERp MDI_PLUS3
CL5 0.1U_0402_10V7K 42 24 LAN_TX3- EMC@ 1
LL27 2
12NH_0603CS-120EJTS_5% LAN_TX3-L LAN_TX2+L RL25 1 2 5.6_0402_5% LAN_TX2+L_R
PERn MDI_MINUS3
1
1 2 PCIE_PTX_GLANRX_N3_C EMC@ LL28 12NH_0603CS-120EJTS_5%
<11> PCIE_PTX_GLANRX_N3
10K_0402_5%
CL6 0.1U_0402_10V7K CL32 EMC@
1
D D
@ RL5
28 6 VCT_LAN_R1 2 1 LAN_TX2-L RL26 1 2 5.6_0402_5% 3.3P_0402_50V8J LAN_TX2-L_R
<7> LAN_SMBCLK SMB_CLK SVR_EN_N
2
SMBUS
31 @ RL3 0_0402_5%
<7> LAN_SMBDATA SMB_DATA 1 +RSVD_VCC3P3_1 RL6 2 1 4.7K_0402_5%
RSVD_VCC3P3_1 +3.3V_LAN
LAN_TX3+L RL27 1 2 5.6_0402_5% LAN_TX3+L_R
1
2 5
<12,36> LAN_WAKE# LANWAKE_N VDD3P3_IN
2
1 2 LAN_DISABLE#_R 3 CL33 EMC@
<12,9> PM_LANPHY_ENABLE LAN_DISABLE_N 3.3P_0402_50V8J
@ RL7 0_0402_5% SMBus Device Address 0xC8 4 +3.3V_LAN_OUT 2 1 +3.3V_LAN LAN_TX3-L RL28 1 2 5.6_0402_5% LAN_TX3-L_R
VDD3P3_4
2
@ RL8 0_0603_5%
<35> LAN_DISABLE#_R
10K_0402_5%
1U_0603_10V6K
15 Pin 6 is SVR_EN in Clarkville
VDD3P3_15
1
@ RL9
LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19
CL7
LOM_SPD100LED_ORG# 27 29
LED1 VDD3P3_29 +0.9V_LAN
LED
LOM_SPD10LED_GRN# 25
LED2
2
47
VDD0P9_47
2
46
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37
@ T89 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
JTAG_TDO
JTAG
+0.9V_LAN TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
XTALO_R 1 2 XTALO 9 40
XTAL_OUT VDD0P9_40
22U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@ RL10 0_0402_5% XTALI 10 22

XTAL_IN VDD0P9_22
1
1 16
VDD0P9_16
1
+0.9V_LAN
CL12
8
VDD0P9_8
CL9
CL10
CL11
CL8
RL11 LAN_TEST_EN 30
TEST_EN LL1
1M_0402_5% Idc_min=500mA
2
2 YL1 RES_BIAS 12 7 REGCTL_PNP10 1 2

RBIAS CTRL0P9 DCR=100mohm
2
3 1 4.7UH_BRC2012T4R7MD_20%
OUT IN
0.1U_0402_10V7K
10U_0603_6.3V6M
49
VSS_EPAD
1
27P_0402_50V8J
27P_0402_50V8J
1K_0402_5%
3.01K_0402_1%
4 2
GND GND
1
CL3
CL4
WGI218LM-QQ89-B0_QFN48_6X6~D
2
2
CL13
RL12
RL13
Note: 25MHZ_18PF_7V25000034
+1.0V_LAN will work at 0.95V to 1.15V CL14 Place CL3, CL4 and LL1 close to UL1
2
1
2
C C
+3.3V_SUS
1
PJP25
PAD-OPEN1x1m
+3.3V_ALW @
UZ8
2
1 14 +3.3V_SUS_UZ8 1 2 +3.3V_LAN
2 VIN1 VOUT1 13 @ CZ41 0.1U_0402_10V7K
VIN1 VOUT1
3 12 1 2
<36,42> SUS_ON ON1 CT1 CZ43 470P_0402_50V7K
4 11
+5V_ALW VBIAS GND
470P_0402_50V7K
0.1U_0402_10V7K
AUX_EN_WOWL 5 10 1 2
<30,35> AUX_EN_WOWL ON2 CT2 CZ42 470P_0402_50V7K
PJP27
CL19
6 9
VIN2 VOUT2
CL18
7 8 +3.3V_WLAN_UZ8 1 2
VIN2 VOUT2 +3.3V_WLAN 10/15 change to
RJ45 LOM circuit
2
15
GPAD PAD-OPEN1x3m SP050006Y00 (S X'FORM_ NS692417 LAN)
0.1U_0402_10V7K
1
TPS22966DPUR_SON14_2X3 @
+3.3V_LAN:20mils
CZ53
@ TL1
1 2 AUX_EN_WOWL
2
RZ38 100K_0402_5% JLOM1 CONN@

LAN_TX3-L_R 1 1:1 24 NB_LAN_TX3-
TD1+ TX1+ LAN_ACTLED_YEL# 1 2 LAN_ACTLED_YEL_R# 10
RL14 150_0402_5% Yellow LED-
9
LAN_TX3+L_R 2 Yellow LED+
TD1- 23 NB_LAN_TX3+ NB_LAN_TX3- 8
TX1- PR4-
+3.3V_LAN NB_LAN_TX3+ 7
B
3 22 Z2805 PR4+ B
@ CL15 TDCT1 TXCT1 NB_LAN_TX1- 6
1 2 PR2-
4 21 Z2807 NB_LAN_TX2- 5
TDCT2 TXCT2 PR3-
0.47U_0603_10V7K
0.47U_0603_10V7K
0.1U_0402_10V7K LAN_TX1-L_R 5 1:1 20 NB_LAN_TX1-

TD2+ TX2+
5
UL2 NB_LAN_TX2+ 4
PR3+
1
LOM_SPD100LED_ORG# 1
P
B
CL16
CL17
4 NB_LAN_TX1+ 3
LOM_SPD10LED_GRN# 2 Y WLAN_LAN_DISBL# <35> PR2+
A
2
2
G
LAN_TX1+L_R 6 19 NB_LAN_TX1+ NB_LAN_TX0- 2

TC7SH08FU_SSOP5 TD2- TX2- PR1- 15
GND
3
NB_LAN_TX0+ 1
PR1+ 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND
RL19 150_0402_5% Green LED-
LAN_TX2-L_R 7 1:1 18 NB_LAN_TX2- LED_100_ORG# 1 2 LED_100_ORG_R# 13
QL1A TD3+ TX3+ RL20 150_0402_5% Orange LED-
DMN66D0LDW-7_SOT363-6 12
LOM_ACTLED_YEL# 1 6 LAN_ACTLED_YEL# Green-Orange LED+
LAN_TX2+L_R 8 rev1
TD3- 17 NB_LAN_TX2+ SANTA_130456-341
TX3-
2

SYS_LED_MASK# 9 16 Z2806
SYS_LED_MASK# <35,39> TDCT3 TXCT3
10 15 Z2808
TDCT4 TXCT4
0.47U_0603_10V7K
0.47U_0603_10V7K
QL1B LAN_TX0-L_R 11 1:1 14 NB_LAN_TX0-

DMN66D0LDW-7_SOT363-6 TD4+ TX4+
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
4
LOM_SPD100LED_ORG# 3 LED_100_ORG# 1 75_0402_1%
1
1
CL20
CL21
LAN_TX0+L_R 12 13 NB_LAN_TX0+
TD4- TX4-
5
SYS_LED_MASK#
NS692417
A QL2A A
RL15 2
RL16 2
RL17 2
RL18 2
LOM_SPD10LED_GRN#1 6 LED_10_GRN#
GND 1 2 EMC@ +GND_CHASSIS

2
CL22 150P_1808_2.5KV8J
SYS_LED_MASK#
CHASSIS use 40mil trace if necessary
QL2B
4 3 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN
5
LA-A972P
5 4 3 2 1
A B C D E
+3.3V_MMI CR3 close to U27.9

CR1 CR2 close to U27.35
+3.3V_MMI
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
CR4 close to U27.42
1
CR6 close to U27.23
CR1
CR2
CR3
2
2
0.1U_0402_25V6
0.1U_0402_25V6
1
1
CR4
CR6
1 1
2
+3.3V_MMI
UR1
+1.2V_LDO
4.7U_0603_6.3V6K
0.1U_0402_25V6
9 12 +AUX_LDO
PE_33VCCAIN
OZ777FJ2LN AUX_LDO_CAP
2
+3.3V_RUN_CARD +1.8V_RUN_CARD
CR7
CR8
27
UHSII_33VCCAIN/NC 25 +SD_IO_LDO
SD_IO_LDO_CAP
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V6K
2
4.7U_0603_6.3V6K
0.1U_0402_25V6
1U_0402_6.3V6K
4.7U_0603_6.3V6K
42
SD_33VCCD
2
CR17
1
CR9
CR13
CR10
CR14
CR15
23
SD_SKT_33VIN 1
CR31
CR34
1
1
13 22
AUX _33VIN SD_SKT_33VOUT +3.3V_RUN_CARD
2
If support RTD3 cold the AUX and MAIN power rail should be
11 24
use different power rail; for RTD3 hot please keep this circuit MAIN_LDO_VIN SD_SKT_18VOUT +1.8V_RUN_CARD
+1.2V_LDO 10
MAIN_LDO_12VOUT
CR31 near UR1.22 CR34 near UR1.24
41
CORE_12VCCD
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
20 SDWP
36 SD_WPI 21 SD/MMCCD#
UHSII_12VCCAIN/NC SD_CD#
2
31
UHSII_12VCCAIN/NC
CR18
CR19
CR21
CR22
28 43 SD/MMCCLK_R RR1 1 EMC@ 2 10_0402_5% SD/MMCCLK
UHSII_12VCCAIN/NC SD_CLK
@EMC@ CR23
45 SD/MMCCMD
1
SD_CMD
5P_0402_50V8C
1
PE_12VCCAIN 39
MMC_D7
1
2 40 2
MMC_D6 44
1 2 PE_REXT 4 MMC_D5 46
2
RR2 191_0402_1% PE_REXT MMC_D4 47 SD/MMCDAT3@EMC@ RR31 2 0_0402_5% SD/MMCDAT3_R
CR24 1 2 0.1U_0402_10V7K PCIE_PTX_MMIRX_P1_C 6 SD_D3 48 SD/MMCDAT2@EMC@ RR41 2 0_0402_5% SD/MMCDAT2_R
<11> PCIE_PTX_MMIRX_P1 PE_RXP SD_D2
CR25 1 2 0.1U_0402_10V7K PCIE_PTX_MMIRX_N1_C 5 37 SD/MMCDAT1
<11> PCIE_PTX_MMIRX_N1 PE_RXM SD_D1 38 SD/MMCDAT0 EMI solution for SD card EMI depop location
CR26 1 2 0.1U_0402_10V7K PCIE_PRX_MMITX_P1_C 7 SD_D0
<11> PCIE_PRX_MMITX_P1 CR27 1 2 0.1U_0402_10V7K PCIE_PRX_MMITX_N1_C 8 PE_TXP 29
<11> PCIE_PRX_MMITX_N1 PE_TXM SD_RCLK_M/NC 30
+3.3V_MMI 2 SD_RCLK_P/NC 32 SD_UHS2_D1P
<7> CLK_PCIE_MMI# 3 PE_REFCLKM SD_D1P/NC 33 SD_UHS2_D1N
<7> CLK_PCIE_MMI PE_REFCLKP SD_D1M/NC 34 SD_UHS2_D0N
SD_D0M/NC
1
100K_0402_5%
15 35 SD_UHS2_D0P
<9> PLTRST_MMI# PE_RST#_GATE# SD_D0P/NC
RR6
MEDIACARD_PWREN 14 26 SD_REXT 1 2
MAIN_LDO_EN SD_REXT/NC RR5 4.7K_0402_1%
16
2
<12> MEDIACARD_IRQ# DEV_WAKE#

17 19
IO_LDOSEL <6,7> MMICLK_REQ# CLKREQ# LED#
IO_LDOSEL 18 49
IO0_LDOSEL GND
100K_0402_5%
1
@ RR8
OZ777FJ2LN_QFN48_6X6
please routing daisy chain

2
1. from UR1.38 (SD_D0) -> UR1.30 (SD_RCLK_P) -> LR3.4

2. From UR1.37 (SD_D1) -> UR1.29 (SD_RCLK_N) -> LR3.1
R231,R297,R306,R315,R333,R337 for EMI solution
+3.3V_MMI
3 3
+3.3V_RUN @ +3.3V_MMI
PJP26
1 2
1 2 MEDIACARD_PWREN
RR15 10K_0402_5%
PAD-OPEN1x1m
CONN@
JSD1
+3.3V_RUN_CARD 4
14 VDD/VDD1
+1.8V_RUN_CARD VDD2
SD/MMCCMD 2
SD/MMCCLK 5 CMD
CLK
SD/MMCCD# 18
CARD DETECT
0.1U_0402_25V6
SDWP 19
WRITE PROTEC
1
1M_0402_5%
1
RR11
SD/MMCDAT0 7
DAT0/RCLK+
CR35
SD/MMCDAT1 8
SD/MMCDAT2_R 9 DAT1/RCLK-
2
SD/MMCDAT3_R 1 DAT2
CD/DAT3
2
SD_UHS2_D0P 11
SD_UHS2_D0N 12 D0+
SD_UHS2_D1P 16 DO-
SD_UHS2_D1N 15 D1+ 20
D1- GND1 21
3 GND2 22
6 VSS1 GND3 23
10 VSS2 GND4 24
13 VSS3 GND5 25
17 VSS4 GND6 26
VSS5 GND7
ALPS_SCDADA0101_NR
4 4
20130726 SP070011L00 CIS Link OK
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader
0.1
A B C D E
5 4 3 2 1
NGFF for UMA NGFF slot A Key A

+3.3V_WLAN
JNGFF1 CONN@
1 2
3 1 2 4
<11> USBP2+ 3 4
5 6 WLAN_LED#
<11> USBP2- 7 5 6
7
8 BT_LED#
9 8 10
1 2 WIGIG_LANE_N3_C 11 9 10 12 WIGIG_AUX#_C 2 1
<25> WIGIG_LANE_N3 11 12 WIGIG_AUX# <25>
CV145 1 2 0.1U_0402_25V6 WIGIG_LANE_P3_C 13 14 WIGIG_AUX_C 0.1U_0402_25V6 2 1 CV150
D <25> WIGIG_LANE_P3 13 14 WIGIG_AUX <25> D
CV146 0.1U_0402_25V6 15 16 0.1U_0402_25V6 CV149
1 2 WIGIG_LANE_N2_C 17 15 16 18 WIGIG_LANE_N1_C 2 1
<25> WIGIG_LANE_N2 17 18 WIGIG_LANE_N1 <25>
CV147 1 2 0.1U_0402_25V6 WIGIG_LANE_P2_C 19 20 WIGIG_LANE_P1_C 0.1U_0402_25V6 2 1 CV152
<25> WIGIG_LANE_P2 19 20 WIGIG_LANE_P1 <25>
CV148 0.1U_0402_25V6 21 22 0.1U_0402_25V6 CV153
23 21 22 24 WIGIG_LANE_N0_C 2 1
<25> WIGIG_HPD 25 23 24 26 2 1 CV156 WIGIG_LANE_N0 <25>
WIGIG_LANE_P0_C 0.1U_0402_25V6
25 26 WIGIG_LANE_P0 <25>
CZ13 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C 27 28 0.1U_0402_25V6 CV157
<11> PCIE_PTX_WLANRX_P4 27 28
CZ14 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C 29 30
<11> PCIE_PTX_WLANRX_N4 29 30 PCH_CL_RST1# <7>
31 32
31 32 PCH_CL_DATA1 <7>
33 34
<11> PCIE_PRX_WLANTX_P4 35 33 34 36 PCH_CL_CLK1 <7>
<11> PCIE_PRX_WLANTX_N4 37 35 36 38
39 37 38 40
<7> CLK_PCIE_WLAN 39 40
41 42 WIGIG_32KHZ
<7> CLK_PCIE_WLAN# 41 42
43 44 PCH_PLTRST#_EC
45 43 44 46 PCH_PLTRST#_EC <20,27,36,9>
BT_RADIO_DIS#_R
<12,7> WLANCLK_REQ# PCIE_WAKE# 47 45 46 48 WLAN_WIGIG60GHZ_DIS#_R
<35> PCIE_WAKE# 49 47 48 50
CZ21 1 2 0.1U_0402_10V7K PCIE_PTX_WIGIGRX_P5_C 51 49 50 52
<11> PCIE_PTX_WIGIGRX_P5 51 52
CZ22 1 2 0.1U_0402_10V7K PCIE_PTX_WIGIGRX_N5_C 53 54
<11> PCIE_PTX_WIGIGRX_N5 53 54
55 56
57 55 56 58 PCH_PLTRST#_EC
<11> PCIE_PRX_WIGIGTX_P5 59 57 58 60
<11> PCIE_PRX_WIGIGTX_N5 59 60 WIGIGCLK_REQ# <12,7>
61 62 PCIE_WAKE#
63 61 62 64
<7> CLK_PCIE_WIGIG 65 63 64 66
<7> CLK_PCIE_WIGIG# 67 65 66
67
69 68
GND GND
+3.3V_ALW
BELLW_80148-3521
1 2
<9> SUSCLK
5
UZ12 @ RZ56 0_0402_5%
1
P
<28,35> AUX_EN_WOWL B 4 1 2
WIGIG_32KHZ_R WIGIG_32KHZ
2 Y RZ57 0_0402_5%
<36> EC_32KHZ_MEC5085 A
G
C TC7SH08FU_SSOP5 C
3
+3.3V_WLAN
0.1U_0402_25V6
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
47P_0402_50V8J
1 2 WLAN_WIGIG60GHZ_DIS#_R
<35> WLAN_WIGIG60GHZ_DIS#
DZ1
1
@ CZ15
RB751S40T1G_SOD523-2 @
CZ20
CZ16
CZ17
CZ18
CZ19
CZ66
2
2
1 2 BT_RADIO_DIS#_R
<35> BT_RADIO_DIS#
DZ2
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type Power Rating TBD
Primary Power Aux Power
0 GND GND GND GND SSD-SATA PWR Voltage
Rail Tolerance
Peak Normal Normal
1 GND HIGH GND GND SSD-PCIE
+3.3V
8 HIGH GND GND GND WWAN

14 HIGH GND HIGH HIGH HCA-PCIE
15 HIGH HIGH HIGH HIGH NA

B
LED control circuit B
3.3V_ALW for LID power

+3.3V_WLAN
JSH1
14
13 GND2
GND1
100K_0402_5%
100K_0402_5%
2
2
RZ14
RZ15
12
+3.3V_ALW 12
11
<36,39> LID_CL# 10 11
10
5
9
9
1
8
7 8 BT_LED# 4 3
7 WIRELESS_LED# <35,39>
6
5 6 QZ2B
5
2
4 DMN66D0LDW-7_SOT363-6
3 4
2 3 WLAN_LED# 1 6
1 2
1 QZ2A
CONCR_205120FW010
CONN@
+3.3V_ALW
0.1U_0402_16V4Z
A A
1
@
C263
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
LA-A972P
5 4 3 2 1
5 4 3 2 1
+5V_USB_CHG_PWR
DI1 EMC@
USB3RN1_D- 1 1 10 9 USB3RN1_D-
LI1 EMC@ JUSB1 CONN@
1 2 USB3RP1_D+ USB3RP1_D+ 2 2 9 8 USB3RP1_D+ 1
<11> USB3RP1 1 2 USBP0_D- 2 VBUS
4 4 D-
USB3TN1_D- 7 7 USB3TN1_D- USBP0_D+ 3
D+
100U_1206_6.3V6M
0.1U_0402_25V6
4 3 USB3RN1_D- 4
<11> USB3RN1 4 3 GND
1
USB3TP1_D+ 5 5 6 6 USB3TP1_D+ USB3RN1_D- 5
SSRX-
CI1
CI3
DLW21HN900HQ2L_4P USB3RP1_D+ 6 10
3 3 7 SSRX+ GND 11
GND GND
2
USB3TN1_D- 8 12
SSTX- GND
2
8 USB3TP1_D+ 9 13
DI2 EMC@ SSTX+ GND
2
D AZC199-02SPR7G_SOT23-3 SANTA_373070-2 D
L05ESDL5V0NA-4_SLP2510P8-10-9
1
LI2 EMC@
2 1 USB3TP1_C 1 2 USB3TP1_D+ 20130730 DC23300C0B0 CIS Link OK
<11> USB3TP1
1
CI5 0.1U_0402_10V7K 1 2 DLW21HN900HQ2L_4P
PS_USBP0_D+ 4 3 USBP0_D+
2 1 USB3TN1_C 4 3 USB3TN1_D- 4 3
<11> USB3TN1 4 3
CI4 0.1U_0402_10V7K
DLW21HN900HQ2L_4P PS_USBP0_D- 1 2 USBP0_D-
1 2
LI3 EMC@
+5V_ALW
+5V_USB_CHG_PWR
UI3
+5V_ALW 1 12
IN OUT
0.1U_0402_25V6
2
1
<11>
<11>
USBP0-
USBP0+
3 DM_OUT
DP_OUT 10 PS_USBP0_D+
PCB USB2 0 USB2 3
DP_IN
CI19
13 11 PS_USBP0_D-
<11> USB_OC0# FAULT# DM_IN
2 ILIM_SEL 4
ILIM_SEL
G12 UMA USB3102 NX3DV221
5 15
<35> USB_PWR_SHR_VBUS_EN EN ILIM_LO 16 RI14 2 1
CI19 near UI3.1
6
ILIM_HI 22.1K_0402_1% G12 Entry NA NA
<35,36> USB_PWR_SHR_EN# 7 CTL1 9
8 CTL2 NC 14
+5V_ALW
CTL3 GND
GNDP
17 G14 DSC USB3102 NX3DV221
TPS2544RTER_WQFN16_3X3
C C
RI13 2 1 ILIM_SEL
10K_0402_5%
G14 UMA USB3102 NX3DV221
G14D_En NA NA
G14U_En NA NA
+USB_RIGHT_PWR
B LI9 EMC@ B
1 2 USB3RN4_D- JUSB2 CONN@
<11> USB3RN4 1 2 1
DI6 EMC@ USBP3_D- 2 VBUS
D-
100U_1206_6.3V6M
0.1U_0402_25V6
4 3 USB3RP4_D+ USB3RN4_D- 1 1 10 9 USB3RN4_D- USBP3_D+ 3
<11> USB3RP4 4 3 D+
4
GND
1
DLW21HN900HQ2L_4P USB3RP4_D+ 2 2 9 8 USB3RP4_D+ USB3RN4_D- 5
SSRX-
CI8
CI10
USB3RP4_D+ 6 10
4 4 SSRX+ GND
USB3TN4_D- 7 7 USB3TN4_D- 7 11
2
USB3TN4_D- 8 GND GND 12
5 5 SSTX- GND
USB3TP4_D+ 6 6 USB3TP4_D+ USB3TP4_D+ 9
SSTX+ GND
13
3
3 3 SANTA_373070-2
3
LI8 EMC@
2 1 USB3TN4_C 1 2 USB3TN4_D- 8 DI3
<11> USB3TN4 1 2
1
CI28 0.1U_0402_10V7K EMC@ 20130730 DC23300C0B0 CIS Link OK
AZC199-02SPR7G_SOT23-3
1
2 1 USB3TP4_C 4 3 USB3TP4_D+ L05ESDL5V0NA-4_SLP2510P8-10-9
<11> USB3TP4 4 3
CI27 0.1U_0402_10V7K
DLW21HN900HQ2L_4P
+5V_ALW +USB_RIGHT_PWR
UI2
1 8
2 GND VOUT 7
3 VIN VOUT 6
VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
4 5
<35> USB_PWR_EN2# EN FLG USB_OC2# <11,12>
@ CI11
LI4 EMC@
CI12
1 2 USBP3_D+ SY6288D10CAC_MSOP8
<11> USBP3+ 1 2
2
4 3 USBP3_D-
<11> USBP3- 4 3
DLW21HN900HQ2L_4P
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0
LA-A972P
5 4 3 2 1
5 4 3 2 1
LI6 EMC@
1 2 USB3RP2_D+ +USB_SIDE_PWR
<11> USB3RP2 1 2
DI4 EMC@ JUSB3 CONN@
4 3 USB3RN2_D- USB3RN2_D- 1 1 10 9 USB3RN2_D- 1
<11> USB3RN2 4 3 VBUS
USBP1_R_D- 2
D-
0.1U_0402_25V6K~D
D DLW21HN900HQ2L_4P USB3RP2_D+ 2 2 9 8 USB3RP2_D+ USBP1_R_D+ 3 D
D+
100U_1206_6.3V6M
1 4
GND
1
USB3TN2_D- 4 4 7 7 USB3TN2_D- USB3RN2_D- 5
StdA-SSRX-
CI14
CI17
LI5 EMC@ USB3RP2_D+ 6 10
2 1 1 2 5 5 StdA-SSRX+ GND
<11> USB3TP2
USB3TP2_C USB3TP2_D+ USB3TP2_D+ 6 6 USB3TP2_D+ 7 11
2
CI13 0.1U_0402_10V7K 1 2 2 USB3TN2_D- 8 GND-DRAIN GND 12
3 3 USB3TP2_D+ 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
2
2 1 USB3TN2_C 4 3 USB3TN2_D-
<11> USB3TN2 4 3
CI16 0.1U_0402_10V7K 8 DI5 EMC@ TAITW_PUBAUE-09FLBS1FF4H0
2
DLW21HN900HQ2L_4P AZC199-02SPR7G_SOT23-3
1
L05ESDL5V0NA-4_SLP2510P8-10-9
1
+5V_ALW +USB_SIDE_PWR
UI1
1 8
2 GND VOUT 7
3 VIN VOUT 6
VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
4 5 USB_OC1# <11,12>
<35> USB_PWR_EN1# EN FLG
1
@ CI6
SY6288D10CAC_MSOP8
CI7
2
2
C C
DLW21HN900HQ2L_4P
4 3 USBP1_R_D+
<11> USBP1+ 4 3
1 2 USBP1_R_D-
<11> USBP1- 1 2
LI7 EMC@
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB SW
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
C C
NFC on USH/B
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NFC
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT E-Dock
LA-A972P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
RPE9
8 1 USB_PWR_SHR_VBUS_EN
7 2 USB_PWR_EN2#
6 3 USB_PWR_EN1#
5 4
USB_PWR_SHR_EN# <31,36>
100K_0804_8P4R_5%
+3.3V_ALW
D 1 2 WLAN_WIGIG60GHZ_DIS# +3.3V_ALW +3.3V_ALW_UE3 D
RE8 100K_0402_5%
1 2 BT_RADIO_DIS# @ PJP14
RE11 100K_0402_5% 1 2
PCIE_WAKE#_R 2 1
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1 2 PROCHOT_GATE PAD-OPEN1x1m 10K_0402_5% RE35
1
@ RE83 100K_0402_5%
1
CE1
CE2
CE3
2
2
PCIE_WAKE# <30>
28
8
UE3
PCIE_WAKE#_R 2 1 1 2
VCC
VCC
PCH_PCIE_WAKE# <36,9>
@ RE275 0_0402_5% 0_0402_5% @ RE274
BC_DAT_ECE1099 32
<36> BC_DAT_ECE1099 33 BC_DAT/SMB_DATA
BC_CLK_ECE1099 Stuff RE275 and no stuff RE274 keep E5 design
<36> BC_CLK_ECE1099 BC_CLK/SMB_CLK
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
9 SMART_DET# PAD~D T32@
GPIO21/KSO01 10
GPIO22/KSO02 USH_PWR_STATE# <27>
39 11
<9> SIO_SLP_WLAN# 40 GPIO10/KSI0 GPIO23/KSO03 12
@ T97 PAD~D EXPRESS_DET# BT_RADIO_DIS#
1 GPIO11/KSI1 GPIO24/KSO04 13 BT_RADIO_DIS# <30>
<28> LAN_DISABLE#_R GPIO12/KSI2 GPIO25/KSO05 WLAN_LAN_DISBL# <28>
2 14 SYS_LED_MASK#
<21> AUD_HP_NB_SENSE GPIO13/KSI3 GPIO26/KSO06 SYS_LED_MASK# <28,39>
3 15
<21> AUD_NB_MUTE# GPIO14/KSI4 GPIO27/KSO07 LED_SATA_DIAG_OUT# <39>
4 16
5 GPIO15/KSI5 GPIO30/KSO08 17 WIRELESS_LED# <30,39>
WLAN_WIGIG60GHZ_DIS#
<23> PANEL_BKEN_EC 6 GPIO16/KSI6 GPIO31/KSO09 18 PCIE_WAKE#_R WLAN_WIGIG60GHZ_DIS# <30>
<28,30> AUX_EN_WOWL USB_DB_DET# 7 GPIO17/KSI7 GPIO32/KSO10 19 VGA_ID
@ T98 PAD~D GPIO20/KSO00 GPIO33/KSO11 20
GPIO34/KSO12 21
C GPIO35/KSO13 22 C
GPIO36/KSO14 23 MASK_SATA_LED#
GPIO37/KSO15 MASK_SATA_LED# <39>
1 2 SMB_ADDR 24
RE87 10K_0402_5% GPIO00/KSO16 25 USB_PWR_SHR_VBUS_EN
GPIO01/KSO17 26 PROCHOT_GATE USB_PWR_SHR_VBUS_EN <31>
GPIO02/KSO18 27
GPIO03/KSO19 29 BCM5882_ALERT# <27>
1 2 SYS_LED_MASK# BC_INT#_ECE1099 34 GPIO04/KSO20 30 USB_PWR_EN1#
<36> BC_INT#_ECE1099 BC_INT#/SMB_INT# GPIO05/KSO21 USB_PWR_EN1# <32>
RE21 10K_0402_5% 31 USB_PWR_EN2#
SMB_ADDR 35 GPIO06/KSO22 36 TOUCH_SCREEN_PD# USB_PWR_EN2# <31>
SMB_ADDR GPIO07 PAD~D T96 @
37
RESERVED
2 1 38
10K_0402_5% RE24 TEST_PIN 41
Thermal Slug(VSS)
ECE1099-FZG_QFN40_6X6~D
+3.3V_ALW
VGA_ID 1 2
100K_0402_5% RE84
VGA_ID 1 2
@ 100K_0402_5% RE85
VGA_ID0
Discrete 0
B UMA 1 B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ECE5048
0.1
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +RTC_CELL
+3.3V_ALW
1 2 +RTC_CELL_VBAT
0.1U_0402_25V6
@ RE32 0_0402_5% +RTC_CELL
1
100K_0402_5%
1 2 BC_DAT_ECE1099
1
CE11
100K_0402_5%
RE36 100K_0402_5%
RE31
RE25
1 2 PBAT_SMBDAT @ CE10
2
RE37 2.2K_0402_5% 1 2
1 2 PBAT_SMBCLK +3.3V_ALW_UE2
2
RE43 2.2K_0402_5% 1U_0402_6.3V6K
2
0.1U_0402_25V6
1U_0402_6.3V6K
POWER_SW_IN# 1 2 LID_CL_SIO# 2 1
POWER_SW#_MB <39,9> LID_CL# <30,39>
1 RE33 10K_0402_5% RE26 10_0402_5%
1U_0402_6.3V6K
1
CE13
CE14
0.047U_0402_16V4Z
+3.3V_ALW_UE2
CE12
2
1
2
CE8
2
1U_0402_6.3V6K
0.1U_0402_25V6
1
1
D D
CE20
CE15
UE2
+3.3V_RUN
2
2 B64 A10
VBAT GPIO021/RC_ID1 AC_DIS <46>
B10 BOARD_ID
GPIO020/RC_ID2 B8 mCARD_PCIE#_SATA @ RE91 1 2 0_0402_5%
1 2 FAN1_PWM +3.3V_ALW +3.3V_ALW_UE2 A22 GPIO014/GPTP-IN7/RC_ID3 B27 LAN_WAKE# mCARD_PCIE#_SATA_R <6,7>
H_VTR GPIO025/UART_CLK B44 LAN_WAKE# <12,28>
RE48 10K_0402_5% HOST_DEBUG_TX
1 2 FAN1_TACH @ PJP15 GPIO120/UART_TX/V2P_COUT_HI1 B46 ME_FWP_EC
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 ME_FWP_EC <6>
RE51 10K_0402_5% 1 2 A58 B26 RUNPWROK
VTR_ADC VCC_PWRGD A25 EN_INVPWR RUNPWROK <9>
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <23>
10U_0603_6.3V6M
0.1U_0402_25V6
PAD-OPEN1x1m B36 SIO_SLP_S3# 1 2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
B3 GPIO101/ECGP_SCLK B37 SIO_SLP_S4# <9>
@ RE280 0_0402_5%
VTR GPIO103/ECGP_MISO SIO_SLP_LAN# <38,9>
1
@CE16
1 2 EN_INVPWR A11 B38
VTR GPIO105/ECGP_MOSI USB_PWR_SHR_EN# <31,35>
CE21
CE17
CE22
CE18
CE23
CE19
RE55 100K_0402_5% A26 A34 PCH_ALW_ON
1 2 RESET_OUT# B35 VTR GPIO102/BCM_C_INT# A35 SIO_SLP_S3# PCH_ALW_ON <38>
SIO_SLP_S3# <9>
2
RE56 10K_0402_5% A41 VTR GPIO104/SLP_S0# A36 PCH_DPWROK RUN_ON_EC 1 2
A52 VTR GPIO106 A40 PCH_DPWROK <9> RUN_ON <36,38>
MSDATA @ RE279 0_0402_5%
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSCLK
GPIO117/MSCLK/V2P_COUT_HI A45 PCH_RSMRST#
GPIO127/A20M B65 FWP# PCH_RSMRST# <37>
SML1_SMBDATA A5 nFWP
<7> SML1_SMBDATA B6 GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
SML1_SMBCLK
<7> SML1_SMBCLK A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 B57
CLK_TP_SIO
<37> CLK_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 B1 BREATH_LED# <39>
DAT_TP_SIO BAT1_LED#
<37> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0 BAT1_LED# <39>
for no-dock : A38 use LCD_TST LCD_TST A38 A55 BAT2_LED#
<23> LCD_TST B41 GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4 A1 BAT2_LED# <39> 1 2
for no-dock : B41 use Free ALW_PWRGD_3V_5V_EC ALW_PWRGD_3V_5V_EC
A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <37,41>
for no-dock : A39 use SLP_ME_CSW_DEV# LCD_VCC_TEST_EN @ RE283 0_0402_5%
<23> LCD_VCC_TEST_EN B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 SIO_SLP_A# <9>
for no-dock : B42 use Free for no-dock : B2 use Free
B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1/32KHZ_OUT A8 EC_32KHZ_MEC5085 <30>
PBAT_SMBDAT
<40> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <9>
PBAT_SMBCLK A56 B9 RUN_ON_EC
<40> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO016/GPTP-IN8 A9 PM_APWROK
A51 GPIO017/GPTP-OUT8 B39 PM_APWROK <9>
JTAG_TDI RESET_OUT# +3.3V_ALW
1 2 B55 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT A44 RESET_OUT# <15,9>
MSDATA JTAG_TDO PCH_PCIE_WAKE#
RE86 10K_0402_5% JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY PCH_PCIE_WAKE# <35,9>
1 2 LCD_TST 1 2 SIO_SLP_S4# JTAG_TMS A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK A54 AC_PRESENT
B47 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2 B58 AC_PRESENT <9>
RE20 100K_0402_5% @ RE282 0_0402_5% JTAG_RST# SIO_PWRBTN# +3.3V_RUN
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <9>
RPE10 RPE3
8 1 RUN_ON FAN1_TACH B22 A3 EXPRESS_SMBDATA EXPRESS_SMBDATA 1 8
7 2 SUS_ON for no-dock : A21 use LID_CL_SIO# LID_CL_SIO# A21 GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO003/I2C1A_DATA B4 EXPRESS_SMBCLK EXPRESS_SMBCLK 2 7
6 3 A_ON SUS_ON_EC B23 GPIO051/FAN_TACH2/GANG _MODE GPIO004/I2C1A_CLK A4 A_ON GPU_SMBDAT 3 6
5 4 PCH_ALW_ON trace width 20 mils PS_ID B24 GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO005/I2C1B_DATA/BCM_B_DAT B5 A_ON <38> GPU_SMBCLK 4 5
1 2 trace width 20 mils <40> PS_ID A23 GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK B7 SIO_EXT_WAKE# <12>
SUS_ON SUS_ON_EC
<28,42> SUS_ON <9> SUSACK# B25 GPIO054/PWM1/GPWM1 GPIO012/I2C1H_DATA/I2C2D_DATA A7 SYS_PWROK <9>
100K_0804_8P4R_5% @ RE281 0_0402_5% <23> BIA_PWM_EC BIA_PWM_EC 2.2K_0804_8P4R_5%
A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 B48 ENVDD_PCH <10,23>
FAN1_PWM GPU_SMBDAT
GPIO056/PWM3/GPWM0 GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK
GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT
GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <46>
CHARGER_SMBCLK
A43 GPIO140/I2C1G_CLK B52 CHARGER_SMBCLK <46>
for no-dock : A43 use BC_CLK_ECE1099 BC_CLK_ECE1099
<35> BC_CLK_ECE1099 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 SIO_SLP_SUS# <9>
for no-dock : B45 use BC_DAT_ECE1099 BC_DAT_ECE1099
<35> BC_DAT_ECE1099 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK PBAT_PRES# <40,46>
for no-dock : A42 use BC_INT#_ECE1099 BC_INT#_ECE1099 A42 B53 USH_SMBDAT +3.3V_ALW
<35> BC_INT#_ECE1099 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <27>
ACAV_IN_NB USH_SMBCLK
C 1 2 A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <27> C
ACAV_IN ACAV_IN_NB SIO_SLP_S5#
@ RE278 0_0402_5% <9> SIO_SLP_S5# BEEP B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 1 2 RPE5
<21> BEEP GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPWR_PRES +3.3V_ALW2
BC_CLK_ECE1117 A20 RE57 1K_0402_5% 1 8 +RTC_CELL
<37> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
100K_0402_5%
BC_DAT_ECE1117 B21 B62 BC_DAT_ECE1117 2 7
<37> BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT/GANG_STROBE BGP0
BC_INT#_ECE1117 A19 A64 ACAV_IN POA_WAKE# 3 6
<37> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OVRD_IN ACAV_IN <46>
RE58
A60 ALWON VCI_IN2# 4 5
A6 VCI_OUT B67 ALWON <41>
SIO_EXT_SMI# POWER_SW_IN#
<12> SIO_EXT_SMI# A27 GPIO011/nSMI VCI_IN0# A63
SIO_RCIN# DOCK_PWR_SW# 100K_0804_8P4R_5%
2
<10,12> SIO_RCIN# IRQ_SERIRQ A28 GPIO061/LPCPD# VCI_IN1# B63 VCI_IN2#
<10,12> IRQ_SERIRQ PCH_PLTRST#_EC B30 SER_IRQ VCI_IN2# B68 POA_WAKE# DOCK_PWR_SW# 2 1
<20,27,30,9> PCH_PLTRST#_EC A29 LRESET# VCI_IN3#
CLK_PCI_MEC Close to UE2 at least 250mils RE62 100K_0402_5%
<7> CLK_PCI_MEC B31 PCI_CLK B51
LPC_LFRAME# +PECI_VREF +1.05V_RUN
<20,7> LPC_LFRAME# A30 LFRAME# VREF_PECI A48 1 2
LPC_LAD0 PECI_EC_R
<20,7> LPC_LAD0 LAD0 PECI_DAT PECI_EC <9>
0.1U_0402_25V6
LPC_LAD1 B32 RE60 43_0402_5% +3.3V_ALW
<20,7> LPC_LAD1 A31 LAD1 B13
LPC_LAD2 REM_DIODE1_N CE24 1 2 2200P_0402_50V7K
<20,7> LPC_LAD2 LAD2 DN1_DP1A/THERM
CE25
LPC_LAD3 B33 A13 REM_DIODE1_P RPE6
<20,7> LPC_LAD3 A32 LAD3 DP1_DN1A/VREF_T B14
CLKRUN# REM_DIODE2_N CE26 1 2 2200P_0402_50V7K THERMATRIP3# 1 8
<10,9> CLKRUN# A33 CLKRUN# DN2_DP2A A14 2 7
SIO_EXT_SCI# REM_DIODE2_P CHARGER_SMBDAT
<12> SIO_EXT_SCI#
2
GPIO100/NEC_SCI DP2_DN2A A15 CHARGER_SMBCLK 3 6
MEC_XTAL1 A61 DN3_DP3A B16 4 5
MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3_DN3A A16 REM_DIODE4_N CE27 1 2 2200P_0402_50V7K
@ RE61 0_0402_5% XTAL2 DN4_DP4A B17 REM_DIODE4_P 10K_8P4R_5%
DP4_DN4A B15 CE24, CE26, CE27 Place near UE2
VIN A17 VSET_5085
VSET A12 PCH_RSMRST# 1 2
VCP I_ADP <46>
B34 THERMATRIP2# 47K_0402_5% RE88
THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# B29 THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 H_PROCHOT#
H_VSS
PROCHOT_IN#/PROCHOT_IO# H_PROCHOT# <45,46,9>
AGND
B61 1 2
V_ISYS0 I_BATT <46>
VSS
A57 RE64 4.7K_0402_5%
EP
V_ISYS1 I_SYS <46>
MEC5085-LZY_DQFN132_11X11
B66
B11
B60
+VR_CAP B12
B54
B18
C1
15mil
Setting for Thermal Design
4.7U_0603_6.3V6K
ACES_50277-0040N-001
6
GND2
1
5
GND1
CE31
+3.3V_ALW Thermal diode mapping 4
2
4 3 FAN1_PWM
3 2 FAN1_TACH
5085 Channel Location 2
1
100K_0402_5%
ESR <2ohms 1
1 +5V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
JFAN1
RE63
10U_0603_6.3V6M
DP1/DN1 CPU
@ CE41
@ CE42
CONN@
1
CLK_PCI_MEC @
32 KHz Clock
2
@EMC@ RE66
CE32
DE1
DP2/DN2 DIMM
1
10_0402_5%
2
B JTAG_RST# B
2
DN2a/DP2a WiGig
1
MEC_XTAL1 1 2 MEC_XTAL2 +3.3V_RUN

2
1U_0402_6.3V6K
4.7P_0402_50V8C
@EMC@ CE34
DP3/DN3 VGA
1
1
@SHORT PADS~D
JTAG1 CONN@
100_0402_1%
22P_0402_50V8J
22P_0402_50V8J
10K_0402_5%
YE1 reserve for DC fan
1
1
@ RE65
32.768KHZ_12.5PF_Q13FC135000040
1
1
CE30
RE67
+3.3V_ALW DP4/DN4 V.R
CE28
CE29
2
+3.3V_ALW
2
Place under CPU
2
100K_0402_5%
2
EMI depop location
1
Place CE35 close to the QE3 as possible
8.2K_0402_5%
RUNPWROK
2
1
RE68
Place close pin A29 REM_DIODE1_P
RE69
3
100P_0402_50V8J
1
2 C
QE2B
@ CE35
2
2
RUN_ON# 5 B
1
E QE3
3
6
MMBT3904WT1G_SC70-3~D THERMATRIP2#
4
REM_DIODE1_N
+1.05V_RUN
QE2A
0.1U_0402_25V6
2
<36,38> RUN_ON
1
+3.3V_ALW
MMBT3904WT1G_SC70-3
C
QE4
DP2/DN2 for SODIMM on QE5, place QE5 close 1 2 2
1
CE36
RE70 2.2K_0402_5% B
to SODIMM and CE37 close to QE5 E
3
49.9_0402_1%
2
1
8
7
6
5
+3.3V_ALW
10K_8P4R_5%
DN2a/DP2a for WiGig on QE7, place QE7 close

RE71
to WiGig/WLAN and CE46 close to QE7

RPE7
REM_DIODE2_P <12> H_THERMTRIP#

1
1
10K_0402_5%
10K_0402_5%
100K_0402_5%
CONN@
2
1
2
3
4
@ RE75
100P_0402_50V8J
JDEG1 MMBT3904WT1G_SC70-3~D
1
RE72
RE73
100P_0402_50V8J
@ CE37
1
E
C
1
1
@ CE46
2 JTAG_TDI 2 2
B
2 3 JTAG_TMS B
3
2
2
4 JTAG_CLK
C
QE7 E QE5
3
4 5 JTAG_TDO MMBT3904WT1G_SC70-3~D
5 6 MSCLK
6 7 MSDATA +3.3V_ALW +3.3V_ALW REM_DIODE2_N
7 8 HOST_DEBUG_TX
8 9
9
130K_0402_5%
10K_0402_5%
10 DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.

10
1
Pin8 5075_TXD for EC Debug

RE79
RE81
pin9 5048_TXD for SBIOS RE79 CE40 REV REM_DIODE4_P VSET_5085 THSEL_STRAP 1 2
11 debug RE78 1K_0402_5%
GND1
100P_0402_50V8J
0.1U_0402_25V6
12
GND2 240K 4700p X00
1
1.58K_0402_1%
2
1
@CE39
C
* 130K 4700p X01
CE38
RE77
ACES_50521-01041-P01 BOARD_ID FWP# 2
A B A
33K 4700p X02 Channel 1
2
4700P_0402_25V7K
E QE6
2
2
Thermal Monitoring Interface Strap Option

10K_0402_5%
MMBT3904WT1G_SC70-3~D
1K 4700p A00
1
@ RE82
+3.3V_RUN HIGH Thermistor Readings

CE40
CONN@ REM_DIODE4_N
JLPDE1 LOW Diode Readings
2
1
1
1 2
2 3 LPC_LAD0
3 4
Rest=1.58K , Tp=96 degree
LPC_LAD1
4 5 LPC_LAD2
11 5 6 LPC_LAD3 BOARD_ID rise time is measured from 5%~68%.
12 G1 6 7 LPC_LFRAME#
G2 7 8 PCH_PLTRST#_EC
8 9
9
10
10 CLK_PCI_LPDEBUG <20,7> DELL CONFIDENTIAL/PROPRIETARY
HB_A531015-SCHR21
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5085
LA-A972P
5 4 3 2 1
5 4 3 2 1
D D
Touch Pad
+3.3V_RUN +3.3V_TP
+3.3V_TP Keyboard
@ PJP16
1 2 CONCR_205160FW010
4.7K_0402_5%
4.7K_0402_5%
1
<11,12> KB_DET# 1
1
PAD-OPEN1x1m 2
2
RZ18
RZ19
3
4 3
5 4
+5V_RUN 5 +3.3V_TP +3.3V_ALW +5V_RUN
+3.3V_ALW 6
2
7 6
DAT_TP_SIO <36> BC_INT#_ECE1117 8 7
<36> DAT_TP_SIO <36> BC_DAT_ECE1117 8
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
9
CLK_TP_SIO 10 9
<36> CLK_TP_SIO <36> BC_CLK_ECE1117 10
1
@ CZ27
@ CZ28
@ CZ29
11
11
@EMC@ CZ30
@EMC@ CZ31
+3.3V_TP 12
12
10P_0402_50V8J
10P_0402_50V8J
DAT_TP_SIO 13
2
CLK_TP_SIO 14 13
14
1
15
16 15
16
2
17
18 GND1
C GND2 Place close to JKBTP1 C
JKBTP1
CONN@
EMI depop location
RSMRST circuit @eDP Cable @USH Board FFC

Part Number Description Part Number Description
+5V_ALW +3.3V_ALW DC02C007P00 H-CONN SET 14A MB-EDP-LED-CAMERA NBX0001KE00 FFC 26P G P0.5 PAD=0.3 47MM MB-USH
+3.3V_ALW
@ CZ34 @eDP TS Cable @KBTP FFC
1
1
33_0402_5%
@ RZ21
10K_0402_5%
@ RZ22
1 2
0.1U_0402_25V6
DC02C007Q00 H-CONN SET 14A MB-EDP-LED-CAMERA-TS NBX0001KD00 FFC 16P G P0.5 PAD=0.3 82MM MB-KBTP
5
@ UZ5
2
<36> PCH_RSMRST# 1 @NFC Board FFC

P
B +5V_ALW_U41 1 B 4 B
VCC O PCH_RSMRST#_Q <9> Part Number
3 RSMRST# 2 Description
RESET# A
G
0.01U_0402_16V7K
2
GND NBX0001KC00 FFC 15P F P0.5 PAD=0.3 40.5MM MB-NFC
@ CZ35
UZ6
3
1
TC7SH08FU_SSOP5~D
RT9818A-44GU3_SC70-3 @FP FFC
2

NBX0001KB00 FFC 8P F P0.5 PAD=0.3 22.5MM MB-FP
<36,41> ALW_PWRGD_3V_5V 1 2
@ RZ51 0_0402_5%
@DC-IN Cable @SIM+Hall/B FFC
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F NBX0001CR00 FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B
@RTC BATT @ Speak

DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
@ FAN
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Keyboard
LA-A972P
5 4 3 2 1
5 4 3 2 1
+1.05V_M
+1.05V_MODPHY +5V_ALW
+1.05V_M QZ6
SI3456DDV-T1-GE3_TSOP6
+1.05V_MODPHY
+1.05V_RUN
Max Rating: 2495 mA
+1.05V_RUN/+3.3V_M source For No-Vpro HW configs
D
6
S
+1.05V_M +1.05V_RUN
2
100K_0402_5%
5 4 1 2
RZ5
2 PJP18 @ NVPRO@ RZ52 0.01_1206_1%
10U_0603_6.3V6M
1 PAD-OPEN1x3m
+3.3V_ALW2
CZ38
2
1
1
100K_0402_5%
D D
2
RZ16
1.05V_MODPHY_EN UZ2 VPRO@
1 14 1 2
+1.05V_M VIN1 VOUT1
2 13 +1.05V_RUN_UZ7 @ CZ24 0.1U_0402_10V7K
VIN1 VOUT1
220P_0402_50V7K
1
2
RUN_ON 3 12 1 2
<36> RUN_ON ON1 CT1
QZ10B
CZ25
VPRO@ CZ49
MPHYP_PWR_EN# 5 4 11 470P_0402_50V7K
2 +5V_ALW VBIAS GND
5 10 1 2
<36> A_ON
4
ON2 CT2
6
VPRO@ CZ23
6 9 470P_0402_50V7K @ PJP13
VIN2 VOUT2
QZ10A
7 8 +3.3V_M_UZ2 1 2
+3.3V_ALW VIN2 VOUT2 +3.3V_M
2
<12> MPHYP_PWR_EN
15
GPAD
1
+1.05V_RUN +1.05V_MODPHY PAD-OPEN1x2m
1
TPS22966DPUR_SON14_2X3 @CZ50
@ PJP36 0.1U_0402_10V7K For No-Vpro HW configs
2
1 2 RUN_ON 1 2
+3.3V_RUN +3.3V_M
NVPRO@ RZ41 0_0402_5%
1 2
PAD-OPEN1x1m A_ON 1 2 NVPRO@ RZ54 0_0603_5%
EN_+V1.05SP <43>
VPRO@ RZ42 0_0402_5%
if support MODPHY off keep DSC solution

MODPHY timing spec 0.7V/us and <65us +3.3V_ALW_PCH/+3.3V_LAN source
C +3.3V_ALW_PCH C
1
PJP19
PAD-OPEN1x1m
+3.3V_ALW @
UZ3
2
1 14 +3.3V_ALW_PCH_UZ3 1 2
2 VIN1 VOUT1 13 @CZ36
@ CZ36 0.1U_0402_10V7K
VIN1 VOUT1
3 12 1 2
<36> PCH_ALW_ON ON1 CT1 CZ37 470P_0402_50V7K
4 11
+5V_ALW VBIAS GND
5 10 1 2
<36,9> SIO_SLP_LAN# ON2 CT2 CZ62 470P_0402_50V7K
6 9 +3.3V_LAN_UZ3 1 2
7 VIN2 VOUT2 8 @CZ63
@ CZ63 0.1U_0402_10V7K
VIN2 VOUT2
15
GPAD PJP20
TPS22966DPUR_SON14_2X3 2 1 +3.3V_LAN
PAD-OPEN1x1m
@
+5V_RUN
B
+3.3V_RUN/+5V_RUN source B
1
PJP21
PAD-OPEN1x3m
+5V_ALW @
UZ9
2
1 14 +5V_RUN_UZ9 1 2
2 VIN1 VOUT1 13 @ CZ44 0.1U_0402_10V7K
VIN1 VOUT1
3 12 1 2
ON1 CT1 CZ45 470P_0402_50V7K
4 11
VBIAS GND
RUN_ON 5 10 1 2
ON2 CT2 CZ46 1000P_0402_50V7K
6 9 @ PJP22
+3.3V_ALW VIN2 VOUT2
7 8 +3.3V_RUN_UZ9 1 2
VIN2 VOUT2 +3.3V_RUN
0.1U_0402_10V7K
15
GPAD PAD-OPEN1x3m
1
TPS22966DPUR_SON14_2X3
CZ47
@
2
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power control
0.1
5 4 3 2 1
5 4 3 2 1
HDD LED solution for White LED Battery LED

+3.3V_ALW
PANEL_HDD_LED# +5V_ALW +5V_ALW

PANEL_HDD_LED# <23>
1
10K_0402_5%
RZ24
3
QZ5B LED7
2
QZ3B QZ3A DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6 DZ3 DMN66D0LDW-7_SOT363-6 4 3 BAT2_LED#_Q 1 2 BATT_WHITE# 1 2
<36> BAT2_LED#
4 3 1 2 1 6 2 RZ25 390_0402_5% W
<6> SATA_ACT#
RB751S40T1G_SOD523-2 BATT_YELLOW# 3 4
5
D D
MASK_BASE_LEDS# Y
2
QZ4
<35> MASK_SATA_LED# DDTA114EUA-7-F_SOT323-3 LTW-295DSKS-5A_YEL-WHITE
1
DZ4
1 2
<35> LED_SATA_DIAG_OUT#
SYS_LED_MASK# 1 2 1 2 BATT_WHITE_LED# <23>
RB751S40T1G_SOD523-2 RZ27 680_0402_5% RZ43 1K_0402_5%
+5V_ALW QZ5A
1 6 BAT1_LED#_Q 1 2 BATT_YELLOW_LED# <23>
<36> BAT1_LED#
RZ28 330_0402_5%
2
QZ14A
QZ14B DMN66D0LDW-7_SOT363-6 MASK_BASE_LEDS#
DMN66D0LDW-7_SOT363-6 1 6 SATA_LED# 2
4 3
1 2
RZ44 390_0402_5%
2
QZ12
5
DDTA114EUA-7-F_SOT323-3
1
LED6
1 2 SATA_LED 2 1
MASK_BASE_LEDS# RZ36 270_0402_5%
LTW-193ZDS5_WHITE
WLAN LED solution for White LED

+3.3V_ALW +5V_ALW
Breath LED
1
100K_0402_5%
C +5V_ALW C
RZ31
QZ7B LED3
DMN66D0LDW-7_SOT363-6 LTW-193ZDS5_WHITE
3
4 3 BREATH_LED#_Q 1 2BREATH_WHITE_LED
BREATH_WHITE_LED_SNIFF 1 2
<36> BREATH_LED#
2
QZ7A RZ32 270_0402_5%

1 6 2 Place LED3 close to SW3
<30,35> WIRELESS_LED#
5
2
QZ9 MASK_BASE_LEDS#
DDTA114EUA-7-F_SOT323-3
1
MASK_BASE_LEDS#
1 2 BREATH_WHITE_LED# BREATH_WHITE_LED# <23>
LED5 RZ34 680_0402_5%
1 2 WLAN_LED 2 1
RZ33 390_0402_5%
LTW-193ZDS5_WHITE
+3.3V_ALW
@ CZ48
1 2
0.1U_0402_25V6
5
1
P
<28,35> SYS_LED_MASK# B 4MASK_BASE_LEDS#

2 O
<30,36> LID_CL# A
G
UZ10
TC7SH08FU_SSOP5~D
3
B B
POWER & INSTANT ON SWITCH

SW2
2 1
<36,9> POWER_SW#_MB
4 3
SKRBAAE010_4P
LED Circuit Control Table
SYS_LED_MASK# LID_CL#
Fiducial Mark Mask All LEDs (Sniffer Function) 0 X

@ FD1
1 Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D Do not Mask LEDs (Lid Opened) 1 1
@ FD2 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H13 @ H14 @ H15 @ H16 @ H19 @ H20 @ H21
1 H_2P3 H_2P5 H_2P5 H_2P8 H_2P8 H_2P8 H_3P4 H_3P4 H_3P4 H_3P4 H_2P1 H_3P0N H_3P0N
A A
FIDUCIAL MARK~D
1
@ FD3
1
FIDUCIAL MARK~D @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H18 @ H17 @ ST1 @ ST2 @ ST3
H_2P5 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 CLIP_C5P1 H_3P3 H_3P3
@ FD4
1 DELL CONFIDENTIAL/PROPRIETARY
1
FIDUCIAL MARK~D
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
LA-A972P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
@ JRTC1
1 3
+COINCELL 2 1 G 4
2 G
D D
TYCO_2-1775293-2~D
2
+RTC_CELL
PD3
1
BAS40CW_SOT323-3 1
PC1
1U_0603_10V4Z
2
1
PD1 EMC@ PD2 EMC@
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@PL1
FBMJ4516HS720NT_2P~D +3.3V_ALW
1 2
3
Primary Battery Connector
EMC@PL2
1
FBMJ4516HS720NT_2P~D
PBATT+_C 1 2 +PBATT
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 PR2
1 100K_0402_5%
1 2
2
PRP2
2 3 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K~D
3 4 PBAT_SMBCLK <37>
PBAT_SMBDAT_C 7 2
4 5 PBAT_SMBDAT <37>
PBAT_PRES#_C 6 3
5 6 PBAT_PRES# <36,48>
1
5 4
PC3
6 7
7 8 100_0804_8P4R_5%
8 9
2
9 10
GND 11
C GND C
@ PBATT1
GND
+3.3V_ALW
@ PR7
2
1 2
0_0402_5%
PR8
2.2K_0402_5%
PL3 EMC@ PR9
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2
S
PS_ID <36>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR10
3
PD5 100K_0402_1%
AZC199-02SPR7G_SOT23-3
1
1
B C B
EMC@
2 PQ3 PR11
B MMST3904-7-F_SOT323-3 10K_0402_1%
1
E
3
2
2
PR12
15K_0402_1%
1
DC_IN+ Source
EMC@ PL4 +DC_IN

FBMJ4516HS720NT_2P
1 2
ACES_50299-0050N-001
1000P_0603_50V7K
PC9 EMC@
10U_0805_25V6K
1
7
PC22 EMC@
4.7K_0805_5%
GND 6
1
GND
1
2
5 -DCIN_JACK
PR16
5 4
4
2
3 +DCIN_JACK
3
2
A 2 A
@
2 1
1
@ PJPDC1 PJP1
1 2
PAD-OPEN 1x3m DELL CONFIDENTIAL/PROPRIETARY

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.1
LA-A902P
5 4 3 2 1
A B C D E
PC105
2200P_0402_50V7K
EMC12UnonD@ +3.3V_RTC_LDO
+3.3V_ALW2
1 1
PR100 PR101
6.49K_0402_1% 15K_0402_1%
1 2 1 2
PR102 PR104
1
10K_0402_1% 10K_0402_1%
4.7U_0603_10V6K
1 2 PR103 1 2
1
PC100
0_0402_5%
2
<36> ALW_PWRGD_3V_5V
1
1
@EMC@PL100 16.9K_0402_1%
1UH +-20% 6.6A 5X5X3 MOLDING +3V5V_PWR_SRC
1 2 +3V5V_PWR_SRC +3.3V_ALW 20K_0402_1%
PR106
2
PR105
2
PJP100
1 2 PU100
10U_0805_25V6K
1
PC102
CS2
VFB2
VREG3
VFB1
CS1
PAD-OPEN 1x3m 100K_0402_1%
2200P_0402_50V7K
21
10U_0805_25V6K
PAD
1
PR107 EN 6
PC101
2
5 PR108 EN2 14
@EMC@ PC105
2
VO1
5
0_0402_5% PR114
2
1 2 PGOOD_3V_5V 7
+PWR_SRC PGOOD 19
200_0402_1%
1 2
2 VCLK 2
4 UG_3V 10 TPS51285BRUKR_QFN20_3X3
PC109 PR110 DRVH2 16 UG_5V 4
PQ100 0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR109 PC110
SIS412DN-T1-GE3_POWERPAK8-5 1 2 BST_3V_C
1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 BST_5V_C
1 2 PQ101
1
2
3
VBST1
3
2
1
SW2 8 SIS412DN-T1-GE3_POWERPAK8-5
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3.3V_ALWP +5V_ALWP
EN1
VIN
2.2UH +-20% 7.8A 7X7X3 MOLDING 3.3UH +-20% 6.3A 7X7X3 MOLDING
1 2 1 2
11
12
13
20
15
5
1
150U_D_6.3VM_R15M
EN
LG_3V LG_5V PR112 @EMC@
150U_D_6.3VM_R15M
@EMC@ PR111
PC113
+ 1
4.7_1206_5% 4.7_1206_5%
2
1SNUB_3V
SNUB_5V
PC115
4 4 +
2
2
PQ102
2
0.1U_0603_25V7K
4.7U_0603_10V6K
SI7716ADN-T1-GE3_POWERPAK8-5 PQ103
@EMC@ PC111
1
2
3
3
2
1
1
1
SI7716ADN-T1-GE3_POWERPAK8-5
PC117
PC118
680P_0603_50V7K
1
2
PC114 @EMC@
2
680P_0603_50V7K
2
+3V5V_PWR_SRC +5V_ALW2
3 3
EN
PR113
3.3 VALWP 0_0402_5%
1 2 PJP101 5 VALWP
TDC: 4.5 A <36> ALWON
+5V_ALWP 1 2
+5V_ALW TDC: 3.5 A
Peak Current: 6.4 A
Peak Current: 5.0 A
℃℃
PAD-OPEN 1x3m
OCP Current: 7.68 A
Cap ESR(@20 ): 18 mohm
Choke DCR(@20 ): 15.5 mohm +3.3V_ALWP
1
PJP102
2
+3.3V_ALW
OCP Current: 6.0 A
Choke DCR(@20 ): 25 mohm
℃℃
PAD-OPEN 1x3m
1U_0603_10V6K
1
PC119
TYP MAX
TYP MAX
H/S Rds(on) :24.0 mohm , 30.0 mohm
2
H/S Rds(on) :24.0 mohm , 30.0 mohm

L/S Rds(on) :13.5 mohm , 16.5 mohm
L/S Rds(on) :13.5 mohm , 16.5 mohm
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A902P
A B C D E
DELL CONFIDE
5 4 3 2 1
PC203
0.675 Volt
TDC 0.7 A
2200P_0402_50V7K
EMC12UnonD@ Peak Current 1.0 A
OCP Current 2.6 A
D +PWR_SRC PJP200 D
1 2 1.35V_B+
BOOT_1.35V_C
PJP201
PR200 2
PAD-OPEN 1x2m~D 1 BOOT_1.35V +VLDOIN_1.35V 1 2 +1.35V_MEN_P
2.2_0603_5%
PAD-OPEN1x1m
+0.675V_P
0.22U_0603_16V7K
DH_1.35V
2200P_0402_50V7K
22U_0805_6.3V6M
10U_0805_25V6K
10U_0805_25V6K
PC204
1
1
SW_1.35V
PC200
PC201
@EMC@ PC203
2
2
5
1
@
PC205
DL_1.35V
16
17
18
19
20
PU200
VLDOIN
BOOT
VTT
PHASE
UGATE
2
21
PAD
4 15 1
+1.35V_MEN_P PQ200 LGATE VTTGND
SIS412DN-T1-GE3_POWERPAK8-5 14 2
PR201
PL200 19.6K_0402_1% PGND VTTSNS +V_DDR_REF
1
2
3
1UH +-20% 11A 7X7X3 MOLDING 1 2 CS_1.35V
1 2 13 3
PC209 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
12 4 +V_DDR_REF
VDDP VTTREF
1
220U_D2_2VY_R17M
1
C C
PR203 @EMC@ PR202
+1.35V_MEN_P
PC207
+ 1 2 VDD_1.35V 11 5
SNUB_1.35V
4.7_1206_5% VDD VDDQ
PGOOD
4
5.1_0603_5%
+5V_ALW
TON
PQ201
2
1
2 PC212
FB sense trace
FB
S5
S3
PC211
SI7716ADN-T1-GE3_POWERPAK8-5 PR204 0.033U_0402_16V7K
1U_0603_10V6K 0_0603_5% when FB pull down to GND
1
2
3
10
6
@EMC@
2
PC208
1
PR205
680P_0603_50V7K
8.06K_0402_1%
2
1.35V_FB 1 2
+5V_ALW
PC213
100P_0402_50V8J
1 2
PR206
1.35V_B+ 1 2
PR207
768K_0402_1%
0_0402_5%
1 2 S5_1.35V
<36,38> SUS_ON
1
@ PC214
PR210 10K_0402_1%
.1U_0402_16V7K
0_0402_5% PR209
2
1 2
<18> 0.675V_DDR_VTT_ON
2
B B
1
1.35 _MEN @ PC215

TDC: 6.6 A .1U_0402_16V7K
2
Peak Current: 9.5 A
℃℃
OCP Current: 11.4 A
Choke DCR(@20 ): 7.4 mohm
+1.35V_MEN_P
TYP MAX FB sense trace

PJP203
H/S Rds(on) : 24.0 mohm , 30.0 mohm 1 2
1 2
L/S Rds(on) : 13.5 mohm , 16.5 mohm JUMP_1x3m
PJP204
PJP202
+1.35V_MEN_P 1
1 2
2
+1.35V_MEM
+0.675V_P 1 2 +0.675V_DDR_VTT
JUMP_1x3m
PAD-OPEN1x1m
A Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P A

S5 L L off off off
S3 L H on on off(Hi-Z) DELL CONFIDENTIAL/PROPRIETARY
S0 H H on on on
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.35V_MEN/+0.675V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
PC300
+1.05V_MEN
TDC: 5.7 A
2200P_0402_50V7K
Peak Current: 8.1 A EMC12UnonD@
D OCP Current: 9.7 A fix by IC
Choke DCR(@20 ): 14.0 mohm ℃ D
EN_+V1.05SP <9,36>
1
1M_0402_1%
PR303
PJP300
2
+1.05V_MP 1 2 +1.05V_M
PAD-OPEN 1x2m~D
@EMC@ PR305 @EMC@ PC301
4.7_1206_5% 680P_0603_50V7K
1 2SNB_1.05V1 2
+PWR_SRC PJP302 PU300
1 2 +V1.05SP_B+ 8 1 PC302 PR312
IN EN
2200P_0402_50V7K
0.1U_0603_25V7K 0_0603_5%
10U_0805_25V6K
C C
PAD-OPEN 1x2m~D 6BST_+V1.05SP
1 2 1
BST_+V1.05SP_C 2 PL301
BS
1
1
@EMC@ PC300
PC303
0.68UH +-20% 7.9A 5X5X3 MOLDING
9
GND LX
10 SW_+V1.05SP 1 2 +1.05V_MP
2
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
7.5K_0402_1%
1
330P_0402_50V7K
1
1
4
PR307
FB_+V1.05SP
FB
PC304
PC305
PC306
PC307
@ PC308
PR313 ILMT_1.05V 3 7
+3.3V_ALW
2
0_0402_5% ILMT BYP
4.7U_0603_6.3V6K
+3.3V_ALW
2
1.05V_M_PWRGD 1 21.05V_MP_PWROK 2 5
4.7U_0603_6.3V6K
PG LDO
1
1K_0402_5%
PC310
<15>
PC309
PR309
SY8208DQNC_QFN10_3X3
PR315
1
2
1 2
+3.3V_ALW
2
@ PR306
2
0_0402_5% 100K_0402_1%
2
ILMT_1.05V
1
1
PR310
@ 10K_0402_1%
PR308
B 0_0402_5% B
2
2
A
DELL CONFIDENTIAL/PROPRIETARY A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN
D TDC: 0.47 A D
Peak Current: 0.67 A
+3.3V_RUN
+5V_ALW
1
PJP400
PAD-OPEN1x1m
1
PC400
2
1U_0402_6.3V6K
2
+1.5V_VIN
1
C 5 C
VCNTL
7 VIN PC401
POK 4.7U_0805_6.3V6K
+3.3V_RUN 4 PJP401
2
VOUT
3 1.5VSP 1 2
PR400
VOUT
+1.5V_RUN
1
1 2 8 2 PAD-OPEN1x1m
EN FB
1
100K_0402_5%
GND
9 PR402 PC403
VIN
1
8.66K_0402_1% 0.01U_0402_25V7K
1
@ PR401 PC402 @EMC@ PU400 PC404
2
2
47K_0402_5% .1U_0402_16V7K APL5930KAI-TRG_SO8 22U_0805_6.3V6M
2
1
2
PR403
10K_0402_1%
2
B B
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5VSP
5 4 3 2 1
5 4 3 2 1
PR522 PC508 PC520
VREF
4700P_0603_50V7K
100K 1% 0402 B25/50 4250K
1
IMON 4.7_1206_5% 680P_0603_50V7K 2200P_0402_50V7K
EMC12UnonD@ EMC12UnonD@ EMC12UnonD@
PH500
316K_0402_1%
PC500
36.5K_0402_1%
1
2 PR504 1
75_0402_1%
681K_0402_1%
@
PR501
75_0402_1%
PR503
PR502
@ PR500
2
2
2
10K_0402_5%
D D
.1U_0402_16V7K
1
OCP-I B-RAMP F-IMAX O-USR
150K_0402_1%
20K_0402_1%
SLEWA
100K_0402_1%
PR505
39K_0402_1%
2 PR506 1
1
PC501
PR509
PR507
PR508
+PWR_SRC
2
1
PJP500
2
39K_0402_5%~N
1 2 +VCC_PWR_SRC
PC520 @EMC@
2200P_0402_50V7K
PR510
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 4x4m 1
100U_D_20VM_R55M
2
1
1
1
PC515
PC516
@ PC517
@ PC518
PC519
+
PR511 @EMC@ PL501
2
+VCC_PWR_SRC 1 2 1 2
2
FBMA-L11-453215800LMA90T_2P 2
10K_0402_5% PR536
1 2
0_0402_5% H_VR_EN <15>
CSP1
16
15
14
13
12
11
10
9
PU500
CSN1
IMON
O-USR
SLEWA
THERM
B-RAMP
F-IMAX
VBAT
OCP-I
SKIP#
+3.3V_RUN 17
CSP1 VR_ON
8 PWM1 PR539
18 7 @ PR513 0_0402_5%
+3.3V_RUN 19 CSN1
CSN2
SKIP#
PWM1
6 1 2 1 2
20 5 75_0402_1% H_VR_READY <15>
21 CSP2 PWM2 4
22 PU3 N/C 3
23 N/C PGOOD 2
24 GFB VDD 1
VFB VDIO @ PR516
GFB
1 2
VFB
+3.3V_RUN
VIDSOUT
1.91K_0402_1%
VR_HOT#
ALERT#
PU501
COMP
C C
DROP
VREF
VCLK
GND
GND
9 +VCC_CORE
V5A
PR519 PC504
8 PGND2
1U_0603_10V6K
1 2 PWM1 PL500
+3.3V_RUN CORE_BOOT_C 1 2 7 PWM
CORE_BOOT 4 CORE_SW 0.15UH_ETQP4LR15AFM_29A_20%
BOOT VSW
25
26
27
28
29
30
31
32
33
TPS51624RSM QFN 32P VCORE IC 1_0603_5% 0.1U_0402_25V6 3

PC503 PGND1 4 1
1 2 CORE_BOOT_R
6 2
PC505
5 BOOT_R VDD
4.7_1206_5%
1SKIP#1
1
1
1000P_0402_50V7K PR517 3 2
@EMC@ PC508 @EMC@ PR522

1 CORE_SNUB
2.2_0603_5% VIN SKIP#
@ PC506 PR521 1 2
1 2 1 2 1 2SKIP#
2
100P_0402_50V8J
4.22K_0402_1% TI recommend 1nF CSD97374CQ4M_SON8_3P5X4P5
PR520
CORE_SW_CSP
0_0402_5%
1 PR523
VR_HOT#
2
VREF
680P_0603_50V7K
10K_0402_5%
2
0.33U_0603_10V7K
1
1 2 1 2 PC507
0_0402_5%
VIDALERT_N
1
1
PR535
2
PC512
VIDSCLK
1U_0603_10V7K
PR534
4.75K_0402_1% 1U_0603_10V7K
1500P_0402_50V7K
PC509
1 2 +5V_RUN
2
+5V_ALW
47P_0402_50V8J
PR526
2
1
PC510
10_0603_1%
PC514
2
PR512
1
2.15K_0402_1%
1 2 CSP1
2
10K +-1% 0402 B25/50 3370K

<9,36,46> H_PROCHOT#
PH501
+1.05V_VCCST
PC513
0.068U_0402_16V7K
PC502
0.068U_0402_16V7K
B B
1
20K_0402_1%
3.01K_0402_1%
1
1
2
1
PR515
PR514
54.9_0402_1%
75_0402_1%
110_0402_1%
PC511
PR529
PR527
PR528
0.1U_0402_25V6
2
2
2
@ PR531
2
0_0402_5% CPU 15W

1 2 VFB CSN1
<15> VIDSCLK <15> VCCSENSE TDC 10 A
<15> VIDALERT_N
from processor PR532 Peak Current 32 A
<15> VIDSOUT 0_0402_5%
1 2 GFB
OCP Current 38.4 A
<17> VSSSENSE
DC Load line -2.0 mV/A
+VCC_PWR_SRC
Choke DCR: 0.66m +-7% ohm

Icc_Dyn_VID1 27 A
PH500 B value: 4250k 1%
PH501 B value: 3370k 1%
1
@ PR518
2M_0402_1%
2
1 2 OCP-I
@ PR524
A 2M_0402_1% A
1
@ PR525
27K_0402_1%
2
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
5 4 3 2 1
A B C D
EMC@ PL700
1UH_PCMB042T-1R0MS_4.5A_20%
SIS496EDNT-T1-GE3 1N POWERPAK1212-8 2 1
PQ710
PQ709
SI7716ADN-T1-GE3_POWERPAK8-5 PR701
1+DC_IN_SS 1 +SDC_IN 0.01_1206_1% +PWR_SRC_AC CHAGER_SRC PC713 PR726 PC721
2 2 PJP700
5 3 3 5 4 1 1 2
+DC_IN
3 2 PAD-OPEN 1x2m~D
4
2200P_0402_50V7K4.7_1206_5% 1000P_0603_50V7K
EMC12UnonD@ EMC12UnonD@ EMC12UnonD@
0.022U_0603_50V7K
1
4.7_0402_1%
1
1
PC731
PR737
PC730
2
0.1U_0402_25V6
CSSN_1
CSSP_1
2
1 1
2
@
4.02K_0402_1%
PR703
DCX124EK-7-F_SC74R-6
1
1 2
PR731
100_0402_1%
2
PR704
3
0_0402_5% PR705
2
@ PQ708B 0_0402_5%
PD704
2 2 1
+PBATT
1
SDMK0340L-7-F_SOD323-2~D
PD705
2 1 PC701 PC702
+DC_IN
1
1U_0603_25V6K 0.1U_0402_25V6
1
PR708
SDMK0340L-7-F_SOD323-2~D 1 2 1 2 1 2
+DC_IN 10_1206_5%
1
GNDA_CHG PC703
AC_DIS <36>
DCX124EK-7-F_SC74R-6 5 PR730 0.1U_0402_25V6
294K_0402_1%
@ PQ708A PQ711 4.02K_0402_1%
2
1
2
1M_0402_1%
G
DMN65D8LW-7_SOT323-3 GNDA_CHG PC710
1
1 2
PR710
PC709 PU700 BQ24770_REGN
+PWR_SRC
3 1
PR709
1U_0805_25V6K
ACN
ACDRV
ACP
6
2 1 +DCIN 28 1U_0603_10V6K
D
VCC
BQ24770_REGN
Near PL701
2
PR711 3 24
1
49.9K_0402_1% CMSRC REGN PR712
2 1 6 2.2_0603_5%
AC Det ACDET 25 1 2 CHG_BTS_C
2200P_0402_50V7K
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
CHG_BTS
PC711 BTST
Max:16.82V 11
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
PC712
10U_0805_25V6K
10U_0805_25V6K
0.047U_0603_25V7K~D
SDA
1
CHARGER_SMBCLK 2 1
Typ :16.54V
1
12 26
@EMC@ PC713
PC714
PC715
PC716
PC717
0.1U_0402_25V6 CHG_UGATE
CHARGER_SMBDAT
Min :16.26V SCL HIDRV
1
1
PC704
PC705
PC706
@ PC707
PC708
2
pull up 10K in HW side (R827 R828) PR713 GNDA_CHG @ PT1 PAD~D 1 2 5
2
100K_0402_1% PR714 0_0402_5% ACOK 27 CHG_SW
<36> CHARGER_SMBDAT
2
7 PHASE @ @
IADP
2
<36> CHARGER_SMBCLK 2
2
@ PT2 PAD~D 8 23 CHG_LGATE

IDCHG LODRV
<36,46> ACAV_IN PR716 0_0402_5% 9
PMON
1
1 2 PR717 0_0402_5%
<36> I_ADP
PR715
154K_0402_1%
PR718
1
0_0402_5%
2
1 2 10
/PROCHOT GND
22 +PWR_SRC
<36> I_BATT
2
PR720 0_0402_5% PL701
PR799 +VCHGR
1 2 PR721
G1
D1
2
<36> I_SYS 13 21 1 2
100P_0402_50V8J
100P_0402_50V8J
BQ24770_REGN 2.2UH +-20% 12A 10X10X4 MOLDING 0.01_1206_1%

CMPIN NC
2 14 10K_0402_1% 7 2 1 4 1
20K_0402_1%
AON6970_DFN5X6D-8-7
CMPOUT D2/S1
2
20
PC718
PC719
PR788
GNDA_CHG
PQ704
1 BQ24770_REGN
SRP 3 2
15 19
PC722 @EMC@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
G2
S2
S2
S2
1
/BATPRES SRN
2
PR722 PR726
1
CHG_SNUB
GNDA_CHG 4.02K_0402_1% 4.7_1206_5%
1
16 18 1 2 @EMC@
CELL /BATDRV
PC723
PC724
@ PC725
<9,36,45,46> H_PROCHOT#
29 17 1 2
2
PWPD BAT
1U_0603_25V6K
PR725 PR723
@
1K_0402_1% BQ24777RUYR WQFN 28P CHARGER 10_0603_1% PC726 PC727 PC728
2
PC729
PR728 0_0402_5% 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
1 2 GNDA_CHG PC721 @EMC@ 1 2 1 2 1 2
<36,40> PBAT_PRES#
2
2
1000P_0603_50V7K
1
1
PJP701
2
+PBATT
GNDA_CHG GNDA_CHG
1
GNDA_CHG
@ PR729 Maximum charging current is 7.2A PAD-OPEN1x1m
154K_0402_1% GNDA_CHG
2
GNDA_CHG BATDRV#
3 3
PD703
PDS5100H-13_POWERDI5-3
3
1
2
+VCHGR
PQ701
SI4835DDY-T1-E3_SO8
1 8
2 7 +PBATT
3 6
5
4
BATDRV#
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
A B C D
5 4 3 2 1
+VCC_CORE
Based on _RF Cheng. Hill
D
1 1 1 1 1
鄭鄭鄭(11257) for PT 20131107 D
PC900 PC901 PC902 PC903 PC904
962
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2
1 1 1 1 1
PC105 @ PC106
PC913 PC914 PC915 PC916 PC917 @
22U_0805_6.3V6M 22U_0805_6.3V6M 2.2U_0805_10V6K 2.2U_0805_10V6K 22U_0805_6.3V6M
2 2 2 2 2
2200P_0402_50V7K 0.1U_0402_25V6
220U 2.5V Y D2 ESR9M H1.9 SX
1 EMC14UnonD@
PC966
+
PC203 @ PC206
2200P_0402_50V7K 0.1U_0402_25V6
C EMC14UnonD@ C
PC300 @ PC311
2200P_0402_50V7K 0.1U_0402_25V6
EMC14UnonD@
PR522 PC508
4.7_1206_5% 680P_0603_50V7K
EMC14UnonD@ EMC14UnonD@
PC520 @ PC521
B
2200P_0402_50V7K 0.1U_0402_25V6 B
EMC14UnonD@
PC713 @ PC732
2200P_0402_50V7K 0.1U_0402_25V6
EMC14UnonD@
PR726 PC721
4.7_1206_5% 680P_0603_50V7K
EMC14UnonD@ EMC14UnonD@
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR DECOUPLING
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
Remove PC923, PC924, PC925, PC926, PC927, PC928, PC929, PC930, PC931,
1 47 VCC_CORE 10/8 Compal To prevent acoustic noise issue PC940, PC941, PC943, PC946, PC947, PC948 X01
Add PC966
2 42 1.35V_MEN 10/8 RICHTEK To prevent IC damage Add PR204 X01
3 46 Charger 10/8 Compal Fine tune divider voltage Change PR715, PR729 to 154k X01
Change PR307 to 7.5k

X01
Change PR310, PR102, PR104, PR403 to 10k
+1.05V_M
4 41,43,44 Change PR100 to 6.49k
+1.5V_RUN 10/22 Compal To improve the ability of anti-noise Change PR101 to 15k
+3V/+5V
C
Change PR402 to 8.66k C
5 X01
45 VCC_CORE 10/31 Compal Fine tune IMON Add PR518, PR524, PR525
6
ALL ALL 10/31 Compal RF request Pop PR522,PC508, PR726, PC721, PC713, PL501, PC520 X01
7 46 Charger 12/05 Compal Has the same behavior with dock circuit Add PQ711 X01
8
46 Charger 12/05 Compal To add 2nd source Remove PQ702 Add PQ709, PQ710 X01
9 46 Charger 12/05 Compal To reduce leakage current Remove PD701 Add PD704, PD705 X01
B B
10 46 Charger 3/03 Compal To set OVP level Remove PR729 X02
11 46 Charger 3/03 Compal To set IC function Remove PC720 Add PR788, PR799 X02
12 40 DCIN 3/03 Compal For ME change request Change PBATT1 X02
13 40 DCIN 3/03 Compal For EMC change request Add PD5 PC20 PC21 PC22 Remove PC11 X02
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR P.I.R (1/1)
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-A902P
5 4 3 2 1
5 4 3 2 1

Request
D D
1 6 HW 2013/10/8 COMPAL Follow intel reference circuit. Add CC100, RC300 on CPU pin AC4, net name is PM_TEST_RST 0.2(X01)
2 27 HW 2013/10/8 COMPAL Dell drop POA function. Change JUSH1 from 26 pin to 20 pin, pin define follow E5 0.2(X01)
remove POA_WAKE# off page symbol

3 36 HW 2013/10/8 COMPAL Dell drop POA function. 0.2(X01)
remove POA_ON/OFF#,make UE2.B62 to be NC pin
4 22 HW 2013/10/9 COMPAL 0.2(X01)
C C
5 24 HW 2013/10/9 COMPAL correct HDMI schematic error. swap HDMI LANE0 & LANE2 BUS 0.2(X01)
Change LI1,LI2,LI3,LI4,LI5,LI6,LI7,LI8,LI9,LV3,LV6,LV10,LV12,LV27
6 23 HW 2013/10/9 COMPAL Follow EMC suggestion From SM070003K00 (S COM FI_ CHILISIN CMMI21T-900Y-N) 0.2(X01)
To SM070003Y00 (S COM FI_ MURATA DLW21HN900HQ2L)
reserved for S3 within 2s , system shutdown

7 9 HW 2013/10/9 COMPAL add RC26, reserved RC27. 0.2(X01)
issue debug.
8 36 HW 2013/10/9 COMPAL board ID change. RE79 change to 130K 0.2(X01)
9 24 HW 2013/10/9 COMPAL SATA ciruit issue Swap mSATA P & N 0.2(X01)
pop RE56 and change from 8.2K to 10K , it's RESET_OUT# pull down
B 10 36 HW 2013/10/14 COMPAL follow intel latest design guide. 0.2(X01) B
resistor
11 7 HW 2013/10/16 COMPAL RF requirement. add CC14, CC15 and move CC12, CC13 to behind the resistor (RC72) 0.2(X01)
change all ESD diode CPN

change DI2, DI3, DI5, DV4 from SCA00001100(S ZEN ROW PJDLC05C 3P C/A
SOT23) to SC600001600(S DIO ROW AZC199-02S.R7G C/C SOT23 ESD)
change DI1,DI6,DI4 from SC300002800(S DIO(BR) TVWDF1004AD0 DFN ESD)
12 20,23,31,32 HW 2013/10/17 COMPAL follow ESD recommend list. to SC300002C00(S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD) 0.2(X01)
change DA1,DA2,DA3,DA6,DA7 from SCA00001L00(S ZEN ROW L30ESDL5V0C3-2
C/A SOT23 ESD) to SCA00002900(S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23
ESD)
13 38 HW 2013/10/17 COMPAL power doesn't split VPRO & NPRO BOM. add RZ41, RZ42, reserve it for VPRO & NVPRO option. 0.2(X01)
14 39 HW 2013/10/17 COMPAL SSI design will cause LED behavior error. QL1 Pin2,5 & QL2 Pin2 change from MASK_BASE_LEDS# to SYS_LED_MASK# 0.2(X01)
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/3)
5 4 3 2 1
5 4 3 2 1

Request
D D
15 20 HW 2013/10/17 COMPAL To solve Line-on HDD dirty shut down issue. UZ8 Pin2 change from +3.3V_ALW to 3.3V_RUN 0.2(X01)
Add back SUS_ON, change control pin from SUS_ON to SIO_SLP_S4#

1. UZ8.3 from SIO_SLP_S4# to SUS_ON
16 28, 36, 38 HW 2013/10/17 COMPAL follow Dell requirement. 2. UE2.B23 → SUS_ON_EC , RPE10.2 → SUS_ON 0.2(X01)
3. add RE282, RE281, RE280, RE279
4. UE2.B9 → RUN_ON_EC
17 12 HW 2013/10/24 COMPAL 0.2(X01)
18 6 HW 2013/10/24 COMPAL debug usage. add RC301 0.2(X01)
reserve it to prevent PCH_PLTRST# floating

19 9 HW 2013/10/28 COMPAL add RC304, 100K pull down, on PCH_PLTRST#_EC 0.2(X01)
when power on
1 CC1 &CC2 change from 18PF to 3PF

C C
6, 7, 22, 2 CC8 & CC11 change from 18PF to 15PF
20 HW 2013/10/23 COMPAL follow xtal vender suggest 0.2(X01)
28 3 CL13 & CL14 change from 33PF to 27PF
4 RV81 change from 0 ohm to 2.2K & CV113 change to 18PF
it's designed for E5 Goliad, E6 GMLK doesn't

21 23 HW 2013/10/29 COMPAL remove RZ1 0.2(X01)
need.
22 30 HW 2013/10/29 COMPAL 0.2(X01)
23 12 HW 2013/10/29 COMPAL To solve backdrive issue. Change TPM_PIRQ# pull up ( RC247) to +3.3V_RUN from +3.3V_ALW_PCH 0.2(X01)
24 30 HW 2013/10/30 COMPAL Dell doesn't support MODPHY. add PJP36, depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38 0.2(X01)
25 7 HW 2013/11/2 COMPAL SMBUS Pull High Add RN3&RN4 pull high to +3.3V_RUN for DDR_XDP_WAN_SMBDAT/SMBCLK 0.2(X01)
26 21 HW 2013/11/2 COMPAL EMC request. Add RA42, RA43. 0.2(X01)

B B
follow vender suggestion. It's for 15KV add CA12, CA13

27 21 HW 2013/11/05 COMPAL 0.2(X01)
ESD fail issue. change DA1, DA2, DA3, DA4 from GNDA to GND
GPIO 14 is sus power well, it has risk to

28 12 HW 2013/11/05 COMPAL move TPM_PIRQ# from PCH_GPIO14 to PCH_GPIO17, add T21 on PCH_GPIO14 0.2(X01)
cause back drive.
39 21 HW 2013/12/17 COMPAL 0.3(X01)
40 22 HW 2013/12/17 COMPAL 0.3(X01)
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
29 22 HW 2013/12/17 COMPAL 0.3(X01)
1.POP RE88,UZ6,RE51 0.3(X01)

30 22 HW 2013/12/17 COMPAL Base on Pre-PT RSMRST EA result
2. remove QZ12,RZ48,RZ49,RZ50
31 22 HW 2013/12/17 COMPAL
0.3(X01)
32 7 HW 2013/12/27 COMPAL Intel recommend Change RC33, RC34 from 1k to 499 ohm 0.3(X01)
C C
B B
A A
Title
5 4 3 2 1

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A B C D E

CONN@ : Connector Component

eDP CONN Dual Lane eDP1.3

HDMI CONN HDMI

W25Q32BVSSIQ LID switch

WLAN/BT/ Discrete TPM PAGE 27

+5V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M SATA 1 JMINI3

USB PORT# DESTINATION

USB_PWR_SHR_EN# USB_PWR_EN1# USB_PWR_EN2#

+3.3V_SUS +3.3V_M +3.3V_LAN +LCDVDD +3.3V_RUN +5V_RUN +5V_USB_CHG_PWR +USB_SIDE_PWR +USB_RIGHT_PWR

+0.675V_DDR_VTT +3.3V_WLAN +3.3V_ALW_PCH

UMA SATA port SATA0 SATA1 PCB SATA2/PCIE6 L1 SATA3/PCIE6 L0

Service Mode Switch:

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

Compal Electronics, Inc.

LPC_LAD0 AU14 AN2

RC29 1K_0402_5% +3.3V_SPI

VPRO@ SPI_DIN32 2 7 SPI_PCH_DO3_32

SPI_PCH_CLK 2 7 SPI_CLK32 GND DI/IO0

D UC1C BDW_ULT_DDR3L UC1D BDW_ULT_DDR3L D

SYSTEM POWER MANAGEMENT

SUSACK# AK2 AW7 DSWODVREN JAPS1

2 BPM#1 H61 XDP_OBS2_R PAD~D T10 @ 51_0402_5%

DDR3 COMPENSATION SIGNALS

121_0402_1% 2 1 RC131 SM_RCOMP1

100_0402_1% 2 1 RC132 SM_RCOMP2 DELL CONFIDENTIAL/PROPRIETARY

C54 C45 EDP_CPU_LANE_N0

DPB_HPD 100K_0402_5% 2 1 RC142

PCIE for UMA

PCIE_PRX_WIGIGTX_N5 F10 AN8 USBP0-

PCB PCIE1 PCIE2 PCIE3 PCIE4 PCIE5 PCIE6

G14D_En SD card NA LOM WLAN GPU WIGIG

RPC7 BDW-ULT-DDR3L_BGA1168 2.2K_0804_8P4R_5%

2 1 PCH_GPIO59 +3.3V_RUN +3.3V_RUN

CFG STRAPS for CPU

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

Package Daisy Chain:

+1.05V_RUN +VCCIO_OUT +VCC_CORE +1.35V_MEM

@EMC@ CC85 22U_0603_6.3V6M

H_VR_EN F60 F52

H_VR_READY C59 F56

P62 PWR_DEBUG VCC G29

RSVD VCC G57

CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU

CC48,CC49, CC50 place near AG10

N8 HSIO RTC AH11

CC63 place near AC9 AC9 AG8

AE20 RSVD AC20 +3.3V_ALW

CC97 place near AH10

intel DG Rev 1.2 , page 500

Reminder below power rail need isolation for layout refer

CC80 place near AH10 CC82 place near A20

S0 Iccmax = 114mA S0 Iccmax = 31mA

UC1N BDW_ULT_DDR3L UC1O BDW_ULT_DDR3L

A11 AJ35 AP22 AV59

153 154 DDR_A_DQS2 1 3 1 2 M_ODT0

155 156 RD10 66.5_0402_1%

20130730 SP07000LT00 CIS Link OK

CD44 DDR_B_D59 67 68 DDR_B_D63

DDR_B_MA1 97 98 DDR_B_MA0 RD23 2_0402_1%

DDR_B_DQS4 171 172

DDR_B_D39 177 178