Cascode Cell Analysis for Ultra-broadband GaAs MMIC Component

Design Applications
Priya Shinghal1, Christopher I. Duff,1 Robin Sloan1 and Steve Cochran2
1
School of EEE, MACS Research Group, The University of Manchester, Manchester, UK
2
Agilent Technologies, Santa Rosa, CA, USA

Abstract — Analysis and comparison of MMIC cascode cells is
presented. The cascode employs the WIN Foundry PP10-10
0.1μm gate length, 2 mil AlGaAs/InGaAs pHEMT process in
common-source and common-gate configurations. On-wafer s-
parameter measurements are performed in the frequency range
of 0.045 GHz – 110 GHz for cascode and device pull-out data.
Comparison of measured data is made with s-parameter
simulation data obtained using the WIN Process Design Kit
(PDK) in common-source & common-gate device configurations
and Electromagnetic (EM) simulated data for the passives
surrounding the cascode devices. The comparison of simulated &
measured s-parameters investigates a 3 dB difference in gain and
differing return losses. This work highlights the need for high
frequency empirical device models for cascode cells, in particular
a common-gate device model extraction including higher
frequency parasitics, for implementation in mm-wave cascode
designs.
Index Terms — Cascode, Common gate, Common source,
MMIC, pHEMT, Ultra-broadband
model for its passives in order to diagnose the evident
discrepancy between simulated and measured results. The
analysis is applicable to other foundry processes as well.
II. DEVICE DESCRIPTION AND FABRICATION
MMIC cascode sections with gate peripheries of 2x25 μm,
2x20 μm, 2x15 μm and 2x12 μm have been fabricated on the
2 mil AlGaAs/InGaAs PP10-10 0.1 μm gate length process by
WIN Semiconductors Ltd., Taiwan, Fig. 1. The CSFET
pHEMT is a microstrip device with substrate backvia to
ground, while the CGFET pHEMT is a CPW structure,
allowing a non-commoned source. The fabrication process is
described in [4] and supports capacitor-on-via fabrication
enabling reduced parasitic inductance compared with
conventional MIM capacitor to ground connections.

I. INTRODUCTION
Ultra-broadband instrumentation and high bit rate optical
communication systems require the development of
components with wideband characteristics, achieved using
Monolithic Microwave Integrated Circuits (MMICs).
Cascode Field Effect Transistors (FETs) are widely used in
design of travelling wave amplifiers, mixers, power amplifiers
and phase shifters for such applications [1 – 2]. Hence, it is
important to understand the model & behavior of the cascode
cell itself for accurate circuit design. The cascode cell consists Fig. 1. Fabricated 2x25 μm conventional cascode cell
of a common source (CS) FET connected in series with a
common gate (CG) FET. Most MMIC designs using a
cascode topology rely on the accuracy of foundry device III. MEASUREMENTS & SIMULATION
models. The CG device models usually derive their s- The device pullouts and cascode cell sections have been
parameters from the empirical model of the CS device [3]. It is measured on-wafer over the frequency band of 0.045 GHz –
shown that this can lead to inaccuracies in the design of 110 GHz using the Agilent 8510 XF Vector Network
circuits employing the cascode topology, evident as a Analyzer and Cascade Microtech probe station at the
discrepancy between the measured and simulated results. millimeter-wave laboratory, The University of Manchester. In-
Thus, a need arises for development of accurate models for house on-wafer calibration standards have been defined and
CG devices themselves. employed for LRRM calibration within Cascade Microtech’s
This work aims at highlighting this requirement by showing WinCAL. Multi-bias s-parameter measurements performed
the extent to which the simulation of cascode cells based on using Agilent’s IC-CAP allow data export to Agilent’s
foundry models for the active devices and an EM model for Advanced Design System (ADS) for comparison with
the interconnecting passives agrees with the measured data simulated data. Electromagnetic (EM) simulation is performed
from 0.045 GHz - 110 GHz. An analysis is presented which using Agilent’s MOMENTUM 2.5 D solver. Plots for
compares various implementations of modeled and measured simulation and measurement are discussed in section IV.
CSFET and CGFET with data in a cascode cell, using an EM

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 IV. ANALYSIS

A. Model and Measurement-Based Cascode

The quiescent bias point of the cascode cell is VDD = 3.5 V,

VG (CS) = -0.2 V, VG (CG) = 0 V to achieve a quiescent IDS =
13.17 mA. At this bias, simulation using Agilent ADS [5]
determines a voltage at the connection between the CS device
drain and CG device source of 0.4 V. Fig. 2 shows the
interconnection between the devices, which has been
electromagnetically (EM) simulated using Agilent
Momentum.

Fig. 4. Measured vs. simulated input and output return losses for
2x25 μm cascade

Input return losses (I/P RL Simulated & I/P RL Measured )

compare well only up-to mid-band, while output return losses
(O/P RL Simulated & O/P RL Measured) do not compare
Fig. 2. Simulation set up for 2x25 μm cascode in ADS well, requiring more work to achieve good agreement . The
measured output return loss shows a negative resistance
The microstrip CSFET and CPW CGFET devices are inserted component typical of cascode configurations [6]. The modeled
into the cascode cell model using either on-wafer measured data does not exhibit this effect, highlighting a need for
pullout s2p device data or the WIN PDK EEHEMT1-based modifications.
nonlinear device model (although operated under a small-
signal regime). For this analysis, a 2x25 μm cascode cell is
employed, as pullouts for this device size were placed on-
wafer. The measured and simulated s-parameters for the cell
are shown in Figs 3 and 4. It is observed that, although S21
follows a similar trend over frequency, the measured small-
signal gain is up to 3 dB higher in magnitude than simulated,
which can be attributed to the sensitivity of CSFET model to
DC bias voltage near knee region.

Fig. 5. Small-signal gain (dB) for illustrations a, b, c, d (Table I)

The graphs shown in Figs. 5 – 8 illustrate the following

comparative analysis with reference to Table I.

Table I. Data label descriptions for Figs. 5 – 8.

Identifier Description
a On-wafer measured cascode cell
b Simulated cascode cell employing measured
CSFET + CGFET pullout s-parameter data
c As (b) but with CSFET foundry PDK model
Fig. 3. Measured vs. simulated gain (dB) of 2x25 μm cascode d As (b) but with CGFET foundry PDK model +
EM simulated passives in cascode configuration

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Fig. 6. Input return losses for illustrations a, b, c & d.
Fig. 7. Output return losses for illustrations a, b, c & d..
It should be noted that, to validate its accuracy, the
measured CGFET device data alone was compared with
measured CSFET data, transformed according to [3].
It can be observed that the measured cascode cell s-
parameter data (a) compares reasonably well with the
simulated data employing the measured CSFET and CGFET
pullout s-parameter data (b), although an increased phase shift
is evident in Fig. 6. Traces (c) and (d) show that the empirical
HEMT model requires further work for data fitting at higher
frequencies.
The work described in [7] demonstrates the successful
implementation of the WIN PDK for the microstrip CSFET in
the design of an E-band LNA and PA and hence confirms the
validity of the CSFET model up to 90 GHz in these
applications. However, the CGFET configuration demands
accurate description of a different device configuration and as
such, a CGFET device model extraction should yield
improved simulation results. Comparison of measured pullout
and PDK simulated CGFET data (trace d) shows that the
measured increase in gain up to the high-frequency roll-off is
not predicted by the model. The device input and output
impedances also require CGFET model parameter fitting, to
yield improvements in their description and ultimately that of
the cascode lineup.
Fig. 8. Reverse isolation (dB) for illustrations a, b, c & d
Fig. 8 shows that the modeled data predicts better reverse
isolation at frequencies above 70 GHz as compared to
measured data for the cascode cell. This again highlights
required device model improvements for mm-wave designs.
B. Conventional and Flipped Cascode Cells
The interconnection between the CSFET and CGFET
requires careful design, as this has a large impact upon
amplifier gain and stability [8]. The Conventional Cascode
configuration (Fig. 9 (a)) connects the CSFET drain and
CGFET source. An alternative Flipped Cascode configuration
(Fig. 9(b)) swaps the CGFET input and output ports,
potentially allowing less metallisation parasitics to be
introduced around the device. The flipped configuration has
the advantage of a compact, simple layout, providing more
room for the common gate grounding circuit.
Fig. 9. ( a ) Conventional Cascode and ( b ) Flipped Cascode
However, contrary to the design intentions, a comparison
of the measured gains of Fig. 10 for these two
implementations shows a higher value with a higher cut-off
frequency for the conventional as compared to the flipped
configuration. Input return losses (I/P_RL_C & I/P_RL_F)
match fairly well but the output return losses (O/P_RL_C &
O/P_RL_F) of Fig. 11 do not. Thus, the output impedance
changes for the cascode in these two implementations due to
978-1-4799-2501-8/13/$31.00 ©2013 IEEE
the difference in layout and extrinsic parasitic network of the
CGFET. Thus, a requirement arises to incorporate these
effects either within the empirical device model or by EM
based extrinsic network modeling. Note that modifications to
the PDK device artwork must be accounted for by
modification to the extrinsic device description, through de-
embedding techniques.
Fig. 10. Gain (dB) for conventional and flipped cascodes
Fig. 11. Input and output return losses for conventional and flipped
cascodes
Davide Resca Et al, [9] have described the EM based
modeling for cascode cells and have validated its accuracy up
to 40 GHz. Future work will extend the current EM based
modeling work up to 110 GHz, including CGFET model
modifications and verification.
V. CONCLUSION & FUTURE WORK
A comparative analysis of MMIC AlGaAs/InGaAs cascode
cells fabricated on the WIN PP10-10 0.1 μm process is
presented. On-wafer measurements of fabricated cascode cells
and common-source and common-gate pHEMT device
pullouts have been performed from 0.045 GHz – 110 GHz and
compared with various combinations of modeled and
measured data. Measured data for a 2x25 μm cascode cell,
when compared with simulated data based on foundry design
kit models for CSFET & CGFET devices, with an EM
interconnect model, show discrepancy but compares
reasonably well with the same simulation employing
measured device data for the CSFET & CGFET. Conversion
of CSFET to CGFET data has been performed to validate the
measurements. However, differences to the measured cascode
data remain. This highlights a need for an accurate CGFET
empirical device model for accurate prediction of cascode
performance. Conventional and flipped configurations of the
cascode are also proposed and their measured s-parameters
presented. The two differ in the way that input RF signal is fed
to the CGFET in the cascode cell. This changes the extrinsic
parasitic network due to the different placement of metal
around the device. Thus, the two configurations have to be
treated differently, highlighting the need for EM simulated
models for accurate prediction of performance.
In view of the analysis presented, the development of
scalable measurement based device models for cascodes up to
110 GHz is proposed for future work for design of a DC – 110
GHz traveling wave amplifier MMIC.
ACKNOWLEDGEMENT
The Authors wish to acknowledge WIN Semiconductors
Ltd., Taiwan, for fabrication of the proposed cascode cells and
Agilent Technologies, Santa Rosa, CA, for support with wafer
fabrication costs and measurements. Also, Schlumberger
Foundation – FFTF initiative for financial PhD support.
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