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Fujitsu MB90F387S

16-bit MCU
I/O Configuration and Functions
I/O Port Function

• The I/O ports enable the port data register (PDR)


to output data to the I/O pins from the CPU and
fetch signals input to the I/O pins. These also
enable the port direction register (DDR) to set a
direction for the I/ O pins in unit of bits.
I/O Port Function
• The following shows the function of each port, and the resources that it
also serves as:

• Port 1: Serves as both general-purpose I/O port and PPG timer


output, or input capture input

• Port 2: Serves as both general-purpose I/O port and reload timer I/O,
or external interrupt input

• Port 3: Serves as both general-purpose I/O port or A/D converter


start trigger pin

• Port 4: Serves as both general-purpose I/O port and UART1 I/O or


CAN controller transmit/receive pin

• Port 5: Serves as both general-purpose I/O port and analog input pin
• Port 2: Serves as both general-purpose I/O port and reload timer I/O, or external interrupt input
• Port 3: Serves as both general-purpose I/O port or A/D converter start trigger pin

I/O Port Summary


• Port 4: Serves as both general-purpose I/O port and UART1 I/O or CAN controller transmit/receive pin
• Port 5: Serves as both general-purpose I/O port and analog input pin

Table 4.1-1 List of Each Port Functions

Port Output
Pin Name Input Type Function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Name Type

General-
P10/IN0 to
CMOS purpose I/O P17 P16 P15 P14 P13 P12 P11 P10
P13/IN3
port
Port 1
CMOS
P14/PPG0 to
high Resource PPG3 PPG2 PPG1 PPG0 IN3 IN2 IN1 IN0
P17/PPG3
current
General-
P20/TIN0 to purpose I/O P27 P26 P25 P24 P23 P22 P21 P20
Port 2 port
P27/INT7
CMOS
(hysteresis) Resource INT7 INT6 INT5 INT4 TOT1 TIN1 TOT0 TIN0
General-
P30 to p33 P36* / P35* /
purpose I/O P37 P34 P33 P32 P31 P30
Port 3 P35/X0A to X1A X0A
port
P37/ADTG
Resource ADTG − − − − − − −
CMOS General-
P40/SIN1 to purpose I/O − − − P44 P43 P42 P41 P40
Port 4 port
P44/RX
Resource − − − RX TX SOT1 SCK1 SIN1
General-
Analog/ purpose I/O P57 P56 P55 P54 P53 P52 P51 P50
P50/AN0 to port
Port 5 CMOS
P57/AN7
(hysteresis) Analog
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
input pin
*: If the low-speed oscillation pin is selected (for MB90387 or MB90F387), P35 and P36 pins cannot be used.
Analog Input (Port 5)

• Port 5 also serve as analog input pins. When


using these ports as general-purpose ports,
always set each bit of the analog input enable
register (ADER) corresponding to each pin of
the ports to 0. ADER bit is 1 at a reset.
he registers related to I/O port setting are listed as follows.

I/O Port Registers


Registers of I/O Ports
Table 4.2-1 "Registers of Each Port" lists the registers of each port.

Table 4.2-1 Registers of Each Port

Register Name Read/Write Address Reset Value

Port 1 data register (PDR1) R/W 000001H XXXXXXXXB

Port 2 data register (PDR2) R/W 000002H XXXXXXXXB

Port 3 data register (PDR3) R/W 000003H XXXXXXXXB

Port 4 data register (PDR4) R/W 000004H XXXXXXXXB

Port 5 data register (PDR5) R/W 000005H XXXXXXXXB

Port 1 direction register (DDR1) R/W 000011H 00000000B

Port 2 direction register (DDR2) R/W 000012H 00000000B

Port 3 direction register (DDR3) R/W 000013H 000X0000B

Port 4 direction register (DDR4) R/W 000014H XXX00000B

Port 5 direction register (DDR5) R/W 000015H 00000000B

Analog input enable register (ADER) R/W 00001BH 11111111B

R/W: Read/Write
X: Undefined value
Port 1
• Port 1 consists of the following three elements:

• General-purpose I/O port, resource or


alternate function I/O pin (P10/IN0 to P17/
PPG3)

• Port 1 data register (PDR1)

• Port 1 direction register (DDR1)


resources.
• When using port 1 as the input pin of the resource, set the pin corresponding to the resource in the

Port 1 Pin Assignments


DDR1 as an input port.
• When using port 1 as the output of the resource, set the output of the corresponding resource to
"enabled". Port 1 functions as the output pin of the resource regardless of the settings of the DDR1
Table 4.3-1 "Pin Assignment of Port 1" shows the pin assignment of port 1.

Table 4.3-1 Pin Assignment of Port 1

I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output

P10/IN0 P10 IN0


P11/IN1 P11 IN1 Input capture
CMOS D
P12/IN2 P12 IN2 input

P13/IN3 P13 General- IN3 CMOS


Port 1 purpose I/O
P14/PPG0 P14 PPG0 (hysteresis)
port
P15/PPG1 P15 PPG1 PPG timer CMOS
output high current G
P16/PPG2 P16 PPG2
P17/PPG3 P17 PPG3

For the circuit type, see Section 1.7 "I/O Circuit".


CHAPTER 4 I/O PORT

Port 1 Block Diagram


■ Block Diagram of Port 1 Pins (in Single Chip Mode)

Figure 4.3-1 Block Diagram of Port 1 Pins

Resource input Resource output

Port data register (PDR) Resource output enable

PDR read
Internal data bus

Output latch P ch

PDR write
Pin
Port direction register (DDR)

Direction latch N ch

DDR write

Standby control (SPL = 1)


DDR read

Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

■ Registers for Port 1 (in Single Chip Mode)


• The registers for port 1 are PDR1 and DDR1.
• The bits composing each register correspond to the pins of port 1 one-to-one.
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

egisters for Port 1 (in Single Chip Mode)

Port 1 Related Registers


• The registers for port 1 are PDR1 and DDR1.
• The bits composing each register correspond to the pins of port 1 one-to-one.
Table 4.3-2 "Correspondence between Registers and Pins for Port 1" shows the correspondence between
the registers and pins of port 1.

Table 4.3-2 Correspondence between Registers and Pins for Port 1

Port
Bits of Related Registers and Corresponding Pins
Name

PDR1, DDR1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 1
Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10

DDR bit value: ‘0’ port direction is input


‘1’ port direction is output
Port 2
• Port 2 consists of the following four elements:

• General-purpose I/O port, resource I/O pin


(P20/TIN0 to P27/INT7)

• Port 2 data register (PDR2)

• Port 2 direction register (DDR2)

• High address control register (HACR)


I/O port.
• Since port 2 serves as resource pin, when used as a resource pin port 2 cannot be used as general-
purpose I/O port.
• When using port 2 as the input pin of the resource, set the pin corresponding to the resource in the

Port 2 Pin Assignments


DDR2 as an input port.
• When using port 2 as the output of the resource, set the output of the corresponding resource to
"enabled". Port 2 functions as the output pin of the resource regardless of the settings of the DDR2.
Table 4.4-1 "Pin Assignment of Port 2" shows the pin assignment for port 2.

Table 4.4-1 Pin Assignment of Port 2

I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output

P20/TIN0 P20 TIN0 16-bit reload timer 0 input


P21/TOT0 P21 TOT0 16-pit reload timer 0 output
P22/TIN1 P22 TIN1 16-bit reload timer 1 input
P23/TOT1 P23 General- TOT1 16-bit reload timer 1 output CMOS
Port 2 purpose I/O CMOS D
P24/INT4 P24 INT4 (hysteresis)
port
P25/INT5 P25 INT5
External interrupt input
P26/INT6 P26 INT6
P27/INT7 P27 INT7

For the circuit type, see Section 1.7 "I/O Circuit".

166
CHAPTER 4 I/O PORT

Port 2 Block Diagram


■ Block Diagram of Pins of Port 2 (General-purpose I/O Port)

Figure 4.4-1 Block Diagram of Pins of Port 2

Resource input Resource output

Port data register (PDR) Resource output enable

PDR read
Internal data bus

Output latch P ch

PDR write
Pin
Port direction register (DDR)

Direction latch N ch

DDR write

Standby control (SPL = 1)


DDR read

Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

■ Registers for Port 2


• The registers for port 2 are PDR2 and DDR2.
• The bits composing each register correspond to the pins of port 2 one-to-one.
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

egisters for Port 2

Port 2 Related Registers


• The registers for port 2 are PDR2 and DDR2.
• The bits composing each register correspond to the pins of port 2 one-to-one.
Table 4.4-2 "Correspondence between Registers and Pins for Port 2" shows the correspondence between
the registers and pins of port 2.

Table 4.4-2 Correspondence between Registers and Pins for Port 2

Port Bits of Related Registers and Corresponding Pins


Name

PDR2, DDR2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 2
Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20

DDR bit value: ‘0’ port direction is input


‘1’ port direction is output
Port 3

• Port 3 consists of the following three elements:

• General-purpose I/O port, resource output pin


(P30 to P33, P35*/X0A, P36*/X1A, P37/ADTG)

• Port 3 data register (PDR3)

• Port 3 direction register (DDR3)


• Use port 3 by switching between the resource pin and the general-purpose I/O port.
• Since port 3 serves as a resource pin, when used as a resource pin, port 3 cannot be used as general-
purpose I/O port.

Port 3 Pin Assignments


• When using port 3 as the resource I/O pin, set the pin corresponding to the resource in the DDR3 as an
input port.

Table 4.5-1 "Pin Assignment of Port 3" shows the pin assignment of port 3.

Table 4.5-1 Pin Assignment of Port 3

I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output

P30 P30 − −
P31 P31 − −
D
P32 P32 − −
P33 P33 General-purpose I/O − − CMOS
Port 3 CMOS
port (hysteresis)
P35/X0A P35* − − D/A
P36/X1A P36* − − D/A
External trigger input
P37/ADTG P37 ADTG D
for A/D converter
*: If the low-speed oscillation pin is selected (for MB90387 or MB90F387), P35 and P36 pins cannot be used.

For the circuit type, see Section 1.7 "I/O Circuit".

171
CHAPTER 4 I/O PORT

Port 3 Block Diagram


■ Block Diagram of Pins of Port 3

Figure 4.5-1 Block Diagram of Pins of Port 3

Resource input Resource output

Port data register (PDR) Resource output enable

PDR read
Internal data bus

Output latch P ch

PDR write
Pin
Port direction register (DDR)

Direction latch N ch

DDR write

Standby control (SPL = 1)


DDR read

Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

■ Registers for Port 3


• The registers for port 3 are PDR3 and DDR3.
• The bits composing each register correspond to the pins of port 3 one-to-one.
Table 4.5-2 "Correspondence between Registers and Pins for Port 3" shows the correspondence between
egisters for Port 3
• The registers for port 3 are PDR3 and DDR3.

Port 3 Related Registers


• The bits composing each register correspond to the pins of port 3 one-to-one.
Table 4.5-2 "Correspondence between Registers and Pins for Port 3" shows the correspondence between
the registers and pins of port 3.

Table 4.5-2 Correspondence between Registers and Pins for Port 3

Port
Bits of Related Registers and Corresponding Pin
Name

PDR3, DDR3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Port 3
Corresponding pin P37 P36* P35* − P33 P32 P31 P30

*: There are no P35 and P36 pins in MB90387 and MB90F387.

DDR bit value: ‘0’ port direction is input


‘1’ port direction is output
Port 4

• Port 4 consists of the following three elements:

• General-purpose I/O port, resource I/O pin


(P40/SIN1 to P44/RX)

• Port 4 data register (PDR4)

• Port 4 direction register (DDR4)


• Use port 4 by switching between the resource pin and the general-purpose I/O port.
• Since port 4 serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
resource.
• When using port 4 as the input pin of the resource, set the pin corresponding to the resource in the

Port 4 Pin Assignments


DDR4 as an input port.
• When using port 4 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 4 functions as the output pin of the resource regardless of the settings of the DDR4.
Table 4.6-1 "Pin Assignment of Port 4" shows the pin assignment of port 4.

Table 4.6-1 Pin Assignment of Port 4

I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output

UART1 serial
P40/SIN1 P40 SIN1
data input

UART1 serial
P41/SCK1 P41 SCK1
clock I/O

UART1 serial
P42/SOT1 P42 General- SOT1
data output CMOS
Port 4 purpose I/O CMOS D
(hysteresis)
port CAN
P43/TX P43 TX controller
send output

CAN
P44/RX P44 RX controller
receive input

For the circuit type, see Section 1.7 "I/O Circuit".

176
CHAPTER 4 I/O PORT

Port 4 Block Diagram


■ Block Diagram of Pins of Port 4

Figure 4.6-1 Block Diagram of Pins of Port 4

Resource input Resource output

Port data register (PDR) Resource output enable

PDR read
Internal data bus

Output latch P ch

PDR write
Pin
Port direction register (DDR)

Direction latch N ch

DDR write

Standby control (SPL = 1)


DDR read

Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

■ Registers for Port 4


• The registers for port 4 are PDR4 and DDR4.
egisters for Port 4

Port 4 Related Registers


• The registers for port 4 are PDR4 and DDR4.
• The bits composing each register correspond to the pins of port 4 one-to-one.
Table 4.6-2 "Correspondence between Registers and Pins for Port 4" shows the correspondence between
the registers and pins of port 4.

Table 4.6-2 Correspondence between Registers and Pins for Port 4

Port Bits of Related Registers and Corresponding Pins


Name

PDR4, DDR4 − − − bit 4 bit 3 bit 2 bit 1 bit 0


Port 4
Corresponding pin − − − P44 P43 P42 P41 P40

DDR bit value: ‘0’ port direction is input


‘1’ port direction is output
Port 5
• Port 5 consists of the following four elements:

• General-purpose I/O port, analog input pins


(P50/AN0 to P57AN7)

• Port 5 data register (PDR5)

• Port 5 direction register (DDR5)

• Analog input enable register (ADER)


• Use port 5 by switching between the analog input pin and the general-purpose I/O port.
• Since port 5 serves as an analog input pin, it cannot be used as a general-purpose I/O port when used as
an analog input pin.
• When using port 5 as an analog input pin, set the pin corresponding to the analog input in the DDR5 as

Port 5 Pin Assignments


an input port.
• When using port 5 as a general-purpose I/O port, do not input any analog signal.

Table 4.7-1 "Pins Assignment of Port 5" shows the pin assignment of port 5.

Table 4.7-1 Pins Assignment of Port 5

I/O Type
Port Circuit
Pin Name Port Function Resource
Name Type
Input Output

P50/AN0 P50 AN0 Analog input channel 0

P51/AN1 P51 AN1 Analog input channel 1

P52/AN2 P52 AN2 Analog input channel 2

P53/AN3 P53 General- AN3 Analog input channel 3 CMOS


Port 5 purpose (hysteresis/ CMOS E
P54/AN4 P54 I/O port AN4 Analog input channel 4 analog input)
P55/AN5 P55 AN5 Analog input channel 5

P56/AN6 P56 AN6 Analog input channel 6


P57/AN7 P57 AN7 Analog input channel 7

For the circuit type, see Section 1.7 "I/O Circuit".

181
CHAPTER 4 I/O PORT

Port 5 Block Diagram


■ Block Diagram of Pins of Port 5

Figure 4.7-1 Block Diagram of Pins of Port 5

Analog input
ADER

PDR (port data register)


Internal data bus

PDR read
Output latch
P ch
PDR write
Pin
DDR (port direction register)

Direction latch N ch
DDR write

Standby control (SPL = 1)


DDR read

Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and timer mode (SPL = 1)

■ Registers for Port 5


• The registers for port 5 are PDR5, DDR5, and ADER.
• The ADER sets input of an analog signal to the analog input pin to "enabled" or "disabled".
• The bits composing each register correspond to the pins of port 5 one-to-one.
egisters for Port 5
• The registers for port 5 are PDR5, DDR5, and ADER.
• The ADER sets input of an analog signal to the analog input pin to "enabled" or "disabled".

Port 5 Related Registers


• The bits composing each register correspond to the pins of port 5 one-to-one.
Table 4.7-2 "Correspondence between Registers and Pins for Port 5" shows the correspondence between
the registers and pins of port 1.

Table 4.7-2 Correspondence between Registers and Pins for Port 5

Port
Bits of Related Registers and Corresponding Pins
Name

PDR5, DDR5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Port 5 ADER ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

Corresponding pin P57 P56 P55 P54 P53 P52 P51 P50

DDR bit value: ‘0’ port direction is input


‘1’ port direction is output
ADER bit value: ‘0’ port is digital I/O
‘1’ port is output analog input
Exercise

• Configure the I/O ports based on the schematic


diagram.

• Draw the flowchart for a two digit counter that


will count up when SW1 is pressed otherwise will
count down when SW2 is pressed.