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ETEE 3285
Topic 13: Load Analysis
1
Objective
To understand hardware constraints on embedded systems
Define:
Noise Margins
Load Currents and Fanout
Capacitive Loads
Transmission Line Effects and Characteristics
and Ground Bounce
Look at TTL & CMOS Static (DC) and Dynamic (AC)
Characteristics
Look at interfacing TTL and CMOS
Perform a detailed Load Analysis
2
Citation:
Arnold, Ken, (2004), Embedded Controller Hardware Design, 1st edition, Newnes
is used extensively in this presentation
4
Skill
A worst-case design takes into account all available
information regarding the components to be used
A detailed analysis will provide documented proof that
the design will work reliably
It is much better to design using worst-case design rules
rather than attempt to correct problems later
Worst-case design efforts result in direct cost and time
savings
5
Definitions
Before we proceed with an analysis we need to consider:
A few conventions used
A few definitions
6
Voltage Levels
VOH-MIN: Minimum Output High Voltage
VOL-MAX: Maximum Output Low Voltage
VDD
VOH-MIN
VIH-MIN
VIL-
VOL-MAX MAX
Gnd
7
Noise Margins
NMHIGH High-Level Noise Margin
NMLOW Low-Level Noise Margin
VDD
VOH-MIN
NMHIGH=VOH-MIN-VIH-MIN
VIH-MIN
VIL-MAX
NMLOW=VIL-MAX-VOL-MAX
VOL-MAX
Gnd
8
High Currents
Currents leaving A IOH B
a device are
considered
positive (IOH)
9
High Fanout
B B B B
A
IOH IIH
+
V ? B B B B
- IIH
Vo
B B B B
IIH
IIH B B B B
When Gate A is producing a logic “1” output, and is driving too many “Gate
Bs,” IOH increases, causing the output voltage to drop (because the voltage
across R is increasing). This will cause Vo to drop, possibly below an
identifiable Logic “1” (2v).
10
10
Low Currents
A B Currents leaving
IIL a device are
considered
positive (IIL)
11
Low Fanout
B B B B
A
IIH
B B B B
IIH
Vo
B B B B
+
V ? IIH
- IOL
IIH B B B B
When Gate A is producing a logic “0” output, and is driving too many “Gate
Bs,” IOL increases, causing the output voltage to increase (because the
voltage across D is increasing). This will cause Vo to rise, possibly above an
identifiable Logic “0” (0.8v).
12
Capacitive Loads
The capacitive load is defined as the parallel combination
of all the input capacitances of the driven gates, plus
stray capacitances in the wiring and traces on the board
CL, is the driving device’s test load capacitance used by
the manufacturer for specifying the AC characteristics
This specification is usually listed in the test conditions or
notes for the timing specifications of the chip
You may have to hunt a little bit for it
13
Capacitive Loads
All the AC characteristics will be valid as specified if the
sum of the load capacitances (including the stray wiring
capacitance) is less than the specified CL
CL > actual Cload = Cin1 + Cin2 + … + Cwiring
If the actual CL is greater than specified CL, then the
clock needs to be slowed down
Additional capacitances will increase the rise and fall times of the signal
line in question
V o for CL > actual Cload
VDD
Gnd
0 Time
14
Typical Capacitive Loads
Input capacitance is often difficult to find
May not be listed in the data sheet
May be defined as a characteristic common to all members of a
given logic family
A ball-park figure for input capacitance is 1 to 5 pF
Load capacitance is usually in the range of 50 to 150 pF
A ball-park figure for wiring capacitance is 1 to 2 pF per
inch of wire for a typical printed circuit trace
15
Actual Capacitive Loads
Of course, actual values can vary quite a bit
Actual wiring capacitive load values depend on:
The physical dimensions of the trace
Proximity to surrounding signals
Distance from a ground plane
The dielectric constant of the circuit board material.
16
CMOS DC Characteristics
A common design problem involves calculating how
many LS-TTL loads a CMOS output can drive
We’ll use the example as found in the Arnold book
CMOS Parameters
LS-TTL DC Characteristics
LS-TTL Parameters
18
Capacitive Load Analysis
The AC parameters would not be the limiting factor in this
case
The CMOS output is specified with a CL of 150 pF
Each LSTTL input is only 10 pF
10 loads would present 100 pF
stray wiring capacitance would be less than 50 pF
Presents an AC load of less than the 150 pF CMOS IC’s output
load handling capability
But ………How many additional CMOS loads could be added?
19
How many additional CMOS?
A DC (static) and an AC (dynamic) answer
From a DC point of view
All the CMOS output sink current (IOL)is used up
So - no loads could be added
However, there is negligible current in a CMOS input
The DC sink current is not the practical limit
The real limitation is the capacitive loading (AC)
The test load was specified as 150 pF (CL)
CL on the CMOS gate output would be 100 pF (ten LS-TTL loads of 10 pF each)
CMOS capacitive loading was specified at CL =150 pF
50 pF left over to drive the additional CMOS loads
CMOS Cin is 25 pF
remaining CL /Cin of additional CMOS inputs = 50 pF/25 pF = 2
20
What about stray capacitance?
Practically speaking
The wiring capacitance on a PC board will generally
be in the 2–3 pF per inch range
Allowing 25 pF for wiring capacitance would allow
one CMOS load in addition to the 10 LSTTL loads
21
What if we had only CMOS loads?
The input capacitance of the CMOS gate is 25 pF
If all loads were CMOS
CL/Cin = 150 pF / 25 pF = 6 CMOS loads
For a worst-case design:
We must also allow for the wiring capacitance
Leaving 25 pF for the wiring capacitance
We should only have 5 CMOS loads
Any more capacitive load would likely result in poor timing
Excessive capacitance can also make ground
bounce worse:
The change in on-chip ground voltage due to rapid current
spikes caused by charging/discharging load capacitance
22
Transmission Line Effects
When using high-speed logic and the rise and fall times
are of the same order as the propagation of the signal,
transmission line effects become significant.
When a signal transition propagates down a wire, it will
be reflected back if the signal is not absorbed at the
destination end.
At lower speeds, the effect can be ignored
With the fastest processors now in use, most engineers
will need to consider whether the effects will have a
negative impact on their designs
Take appropriate action if necessary.
23
Transmission Line Characteristics
There are several characteristics of digital transmission
lines that must be addressed:
signal transition time vs. clock rate
mutual inductance and capacitance (crosstalk)
physical layout effects
impedance estimates
strip line vs. micro strip
effects of unmatched impedances
termination and other alternatives
series termination vs. parallel termination
DC vs. AC termination techniques
24
Ground Bounce
An effect of high-speed signal transitions
Ground bounce occurs when a large peak current flows
through the ground pin of a chip due to one or more
logic outputs changing state and discharging their load
capacitances simultaneously
While the parasitic inductance of the ground pin may
not seem very significant (in the nano-henry range)
Fast transients can cause large voltages to appear across the
ground pin (the parasitic inductance)
25
VL: Voltage across the inductance
The voltage across an inductor is equal to the
inductance times the rate of change of current through
the inductor:
V = L * di/dt, where
V = instantaneous voltage across the inductor (volts)
L = Inductance (henry)
di/dt = Rate of change of current (amperes/sec)
and current i = Q/t (amperes = coulombs per second)
So:
V = L * C * (delta V) / (delta t) 2 approximately, or
V = L * C * (Voh-Vol) / (Tr)2 using the output voltage and rise time
26
In-Class Exercise:
A CMOS output driving a 100 pF load with a rise time of
2 nS would induce what voltage across a typical 1 nH
inductance of the chip’s ground lead:
V = L * C * (Voh-Vol) / (Tr)2
≈ 4.5v ≈ 0.5v
27
In-Class Exercise:
A CMOS output driving a 100 pF load with a rise time of
2 nS would induce what voltage across a typical 1 nH
inductance of the chip’s ground lead:
V = L * C * (Voh-Vol) / (Tr)2
28
In-Class Exercise:
A CMOS output driving a 100 pF load with a rise time of
2 nS would induce what voltage across a typical 1 nH
inductance of the chip’s ground lead:
V = L * C * (Voh-Vol) / (Tr)2
29
Ground Pins
This is why high-speed logic devices may have multiple,
short ground pins, and may only be available in small,
surface mounted packages
Exact ground lead inductances are difficult or
impossible to measure
The longer the lead, the greater the inductance
So:
Avoid making embedded systems faster then necessary
Use very short ground and power wires
High speed PC boards should:
Use separate inner layers for ground and power planes
Use very short wires
30
Interfacing Logic Families
The three most common logic families are:
TTL: transistor-transistor logic
NMOS: n-channel metal oxide semiconductor field effect
transistor logic
CMOS: complementary MOS logic
All have versions with TTL compatible inputs
CMOS has become the most common
Lower power consumption:
good for battery operated mobile devices
Relatively high circuit density
31
TTL/CMOS Noise Margins
TTL
CMOS
32
CMOS driving TTL
TTL
33
TTL driving CMOS Interfacing
TTL
CMOS
34
TTL driving CMOS Interfacing
TTL
35
Interfacing
There are several ways to handle this:
Use High speed CMOS TTL compatible: 74HCTxx
Can be driven directly by devices having TTL output voltage levels
Use TTL to CMOS level shifters
36
Level Shifters
Level shifters are available for converting logic levels
from one family to another
3 volt to and from 5 volt CMOS
5 volt TTL to +/- V ECL (emitter-coupled logic)
5 volt levels to +/-12 volt RS-232 signals
There are also special ICs for driving output loads
requiring either a high voltage or high current output,
Light, motor or relay
AC interfaces
Solid-state relays
Optical-isolators
37
Optical Isolators
Provide a barrier to transient voltages that can be on
the order of thousands of volts
Barrier is transparent: allows light to pass
Insulated to prevent current flowing across the
boundary
38
High Voltage Outputs
High voltage outputs can also be controlled safely by
using the microcontroller’s output to turn on the LED
that turns the output switch on
In this case:
An SCR (silicon-controlled rectifier) or
TRIAC (an AC version of the SCR) is used
Rather than a transistor
Referred to as solid-state relays (SSR),
39
Load Analysis Example
An LS-TTL gate is to be used to drive one LS-TTL input
and one CMOS input
An interface must be made which will guarantee the
CMOS input voltage requirement will be met with the
same noise margin as a standard LSTTL input
Specifications for the LS-TTL and CMOS gates are
shown on the next page
40
LS-TTL and CMOS Specs
41
LS-TTL and CMOS Specs
42
Rmin
The lowest resistor value that will work is the value which will
source enough current so the LS-TTL output is just able to sink the
resistor current plus the additional LS-TTL load when the signal is
low and still meets the maximum output low voltage specification:
43
Rmin
The lowest resistor value that will work is the value which will
+ source enough current so the LS-TTL output is just able to sink the
V
- resistor current plus the additional LS-TTL load when the signal is
low and still meets the maximum output low voltage specification:
The voltage across the resistor is Vcc – V OL max for the LS-TTL
input, or 5 – 0.4 = 4.6 volts.
44
Rmin
The lowest resistor value that will work is the value which will
source enough current so the LS-TTL output is just able to sink the
resistor current plus the additional LS-TTL load when the signal is
low and still meets the maximum output low voltage specification:
The voltage across the resistor is Vcc – V OL max for the LS-TTL
input, or 5 – 0.4 = 4.6 volts.
45
Rmin Equation
The lowest resistor value that will work is the value which will
source enough current so the LS-TTL output is just able to sink the
resistor current plus the additional LS-TTL load when the signal is
low and still meets the maximum output low voltage specification:
The voltage across the resistor is Vcc – V OL max for the LS-TTL
input, or 5 – 0.4 = 4.6 volts.
47
Rmax Equation
The maximum acceptable value, Rmax, is determined by the
+ minimum output high voltage that will guarantee a CMOS high input
V
- plus noise margin. The resistor must be able to supply the LS-TTL
maximum input high current and not have too large a voltage drop
across it.
48
Rmax Equation
The maximum acceptable value, Rmax, is determined by the
+ minimum output high voltage that will guarantee a CMOS high input
V
- plus noise margin. The resistor must be able to supply the LS-TTL
maximum input high current and not have too large a voltage drop
across it.
49
R Value
The maximum acceptable value, Rmax, is determined by the
+ minimum output high voltage that will guarantee a CMOS high input
V
- plus noise margin. The resistor must be able to supply the LS-TTL
maximum input high current and not have too large a voltage drop
across it.
50
RC Time Constant
Another limit relates to the rise time of the signal under load, due to the
+ R-C time constant of the pull-up resistor charging the load capacitance,
V
- CL. The effect of this time constant on the selection of the resistor is:
51
Rmax due to RC
Another limit relates to the rise time of the signal under load, due to the
+ R-C time constant of the pull-up resistor charging the load capacitance,
V
- CL. The effect of this time constant on the selection of the resistor is:
R = T / CL
where T is the rise time and CL is the total load capacitance
52
Rmax due to RC
Another limit relates to the rise time of the signal under load, due to the
+ R-C time constant of the pull-up resistor charging the load capacitance,
V
- CL. The effect of this time constant on the selection of the resistor is:
R = T / CL
where T is the rise time and CL is the total load capacitance
If the circuit above had a rise time of T = 50 nS and CL = 20 pF, then the
maximum R value would be:
53
Better Choice
Another limit relates to the rise time of the signal under load, due to the
+ R-C time constant of the pull-up resistor charging the load capacitance,
V
- CL. The effect of this time constant on the selection of the resistor is:
R = T / CL
where T is the rise time and CL is the total load capacitance
If the circuit above had a rise time of T = 50 nS and CL = 20 pF, then the
maximum R value would be:
So a better choice might be
a standard 2.2 kΩ pull-up Rmax = 50 nS / 20 pF = 2.5 kΩ maximum to maintain the 50 nS rise time.
resistor.
54
Summary
To understand hardware constraints on embedded systems
Defined:
Timing Conventions
Noise Margins
Load Currents and Fanout
Capacitive Loads
Transmission Line Effects and Characteristics
and Ground Bounce
Looked at TTL & CMOS Static (DC) and Dynamic (AC)
Characteristics
Looked at interfacing TTL and CMOS
Performed a detailed Load Analysis
55