IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO.
1, JANUARY 2003
Full-CMOS 2-GHz WCDMA Direct Conversion
Transmitter and Receiver
Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park,
Kyeongho Lee, Deog-Kyoon Jeong, and Wonchan Kim
Abstract—This paper presents a full-CMOS transmitter and
receiver for 2.0-GHz wide-band code division multiple access with
direct conversion mixers and a dc-offset cancellation scheme. The
direct conversion scheme combined with a multiphase sampling
fractional- prescaler alleviates the problems of the direct
conversion transmitter and receiver. Digital gain control is merged
into the baseband filters and variable-gain amplifiers to optimize
the linearity of the system, reduce the noise, and improve the
sensitivity. Variable-gain amplifiers with dc-offset cancellation
loop eliminate the dc-offset in each stage. The chip implemented
in 0.35- m CMOS technology shows the experimental results
of 6 dBm maximum output power with 38-dB adjacent channel
power rejection ratio at 1.92 MHz, 50-dB dynamic range, and
363-mW power consumption in the transmitter. The receiver
shows 115.4 dBm sensitivity, a 4.0-dB noise figure, and a
dynamic range of 80-dB with 396-mW power consumption.
Index Terms—Adjacent channel power rejection ratio (ACPR),
dc-offset, direct conversion, fractional- prescaler, mixer,
receiver, transmitter, wide-band code-division multiple access
(WCDMA).
I. INTRODUCTION
R ECENTLY, CMOS RF integration has been widely
explored in the wireless communication area to save
cost, power, and chip area. The direct conversion architecture,
rather than a more conventional super-heterodyne, has been
an attractive choice for single-chip integration because of its
many advantages. However, the direct conversion architec-
ture has several fundamental problems to solve in achieving
performance comparable to a super-heterodyne counterpart.
The dc-offset problem caused by local oscillator (LO) leakage
is the most serious one. The multiphase reduced frequency
conversion scheme was proposed as one of the candidates
to solve the dc-offset problem and to alleviate difficulty in
obtaining the required phase noise level [1]. The multiphase
reduced frequency conversion scheme is incorporated in the
design of a single-chip wide-band code division multiple access
(WCDMA) transmitter and a receiver and their experimental
results indicate conformity to the required commercial 2.0-GHz
WCDMA specification.
Manuscript received February 19, 2002; revised July 17, 2002.
K.-Y. Lee is with the Inter-University Semiconductor Research Center
(ISRC), Seoul National University, Seoul 151-742, Korea (e-mail:
kylee@griffin.snu.ac.kr).
S.-W. Lee, J.-W. Lee, and K. Lee are with GCT Semiconductor, Inc., San
Jose, CA 95131 USA.
Y. Koo, H.-K. Huh, H.-Y. Nam, D.-K. Jeong, and W. Kim are with the School
of Electrical Engineering, Seoul National University, Seoul 151-742, Korea.
Digital Object Identifier 10.1109/JSSC.2002.806280
0018-9200/03$17.00 © 2003 IEEE
43
This paper is organized as follows. In Section II, the proposed
direct conversion architecture is described and its problems and
proposed solutions are discussed. Section III describes various
building blocks and circuits used to build the chip. Section IV
shows experimental results from a 0.35- m CMOS implemen-
tation, and Section V concludes the paper.
II. SYSTEM ARCHITECTURE
The block diagram of the transmitter using the multiphase
reduced frequency conversion architecture is shown in Fig. 1.
The transmitter is composed of a 10-b digital-to-analog con-
verter (DAC), a baseband filter with a tuning circuit, a vari-
able-gain amplifier (VGA), a quadrature upconverter, a pream-
plifier, and a frequency synthesizer. The 10-b DAC receives 10-b
data from the baseband modem and operates at 32.768 mega
samples per second (Msps) performing four-time oversampling.
The baseband filter is tuned to a 3.84-MHz cutoff frequency by
the tuning circuit. The variable-gain amplifier is controlled dig-
itally by the baseband modem. The high-pass filter (HPF) sup-
press the dc-offset due to baseband circuits. The quadrature up-
converter which is composed of two six-phase mixers receives
650-MHz-band 12-phase LO signals (LO[0:11]) from the fre-
quency synthesizer and receives I/Q baseband signals from the
VGAs. The quadrature upconverter offers the same function-
ality as the conventional one receiving a single-phase 2.0-GHz
LO signal. The converter generates a 2.0-GHz modulated signal
and sends its output to the preamplifier. The frequency synthe-
sizer is composed of a 12-phase VCO, a fractional- prescaler,
a charge-pump, and a phase frequency detector. It generates a
set of 700-MHz 12-phase LO signals (LO[0:11]) for the selected
channel frequency. LO and (LO ) signals are separated
by in time. A fractional- architecture is used
to obtain a bandwidth large enough for fast lock time and low
phase noise. A multiphase voltage-controlled oscillator (VCO)
with a low center frequency is easier to design to meet the per-
formance requirement of a high carrier frequency application.
Fig. 2 shows the architecture of the receiver which uses the
same multiphase reduced frequency conversion architecture.
The receiver is composed of a CMOS low-noise amplifier
(LNA), a quadrature downconverter, a frequency synthesizer,
a VGA, a baseband filter with a tuning circuit, and two 6-b
ADCs operating at the 32.768-Msps sampling rate. The 6-b
analog-to-digital converters (ADCs) give enough precision
headroom for efficient digital signal processing. The frequency
synthesizer, like the one in the transmitter, generates 12-phase
LO signals (LO[0:11]) for different channel frequencies. The
44
Fig. 1. Transmitter architecture.
Fig. 2. Receiver architecture.
quadrature downconverter which is composed of two six-phase
mixers receives 700-MHz 12-phase LO signals. The baseband
structure is composed of five stages of VGAs, two third-order
active-RC elliptic filters, a fifth-order elliptic filter,
and a fifth-order elliptic equalizer.
Fig. 3 shows the circuit diagram and explains how the
dc-offset is suppressed in the multiphase reduced frequency
direct conversion receiver architecture. In the conventional
architecture, the VCO frequency is equal to the carrier fre-
quency. As a result, LO leakage terms , , and
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
caused by the power/ground fluctuation and layout coupling,
can generate a large amount of dc-offset on the output node
of the downconversion mixer. However, in the multiphase
reduced frequency conversion receiver architecture, the VCO
frequency is far below the carrier frequency. As a result,
the main power of LO leakage is not located at the carrier
frequency and the amount of dc-offset can be reduced. As
shown in Fig. 3, the amount of dc-offset which appears as
in the multiphase reduced
, frequency architecture, when high-frequency components
LEE et al.: FULL-CMOS 2-GHZ WCDMA DIRECT CONVERSION TRANSMITTER AND RECEIVER
Fig. 3. DC-offset suppression in multiphase reduced frequency conversion receiver architecture.
are filtered, is significantly less than that of the conventional
architecture, . control blocks in parallel with resonator loads use 20 PMOS
III. BUILDING BLOCKS
In the transmitter RF parts, the upconversion mixer and the
preamplifier convert and amplify the signal from the baseband
block. The LNA and the quadrature mixers amplify and con-
vert the signal for the baseband block in the receiver. Baseband
blocks include quadrature paths for filtering and controlled gain
in a merged manner. The digitally controllable analog front-end
allows flexibility in the overall radio system design [2]. The
tradeoff between noise and linearity in the baseband signal pro-
cessing has been optimized using a merged filtering and con-
trolled gain scheme before upconversion in the transmitter and
after the downconversion in the receiver.
A. RF Blocks
1) Upconversion Mixer and Preamplifier: Fig. 4 shows
the circuit diagram of the quadrature upconverter using two
six-phase double-balanced mixers, one for the I-channel and
the other for the Q-channel. The baseband I and Q signals are
upconverted to RF differential signals, RF_out and RF_outb,
by the quadrature mixer performing single-sideband modu-
lation. The level of input signals from the baseband block,
Mixer_In_I, Mixer_Inb_I, Mixer_In_Q, and Mixer_Inb_Q, is
about 12 dBm and the common-mode dc level is 1.6 V. The
total dc current consumed in this block is 13 mA. The total
gain control range is 20 dB and the gain step is 1 dB. The
resonator load consists of , , , , and resistors. Gain
control is done by changing the resistance between VDD_INT
45
and RF_out and between VDD_INT and RF_outb. The gain
transistors used as programmable resistors which respond to
20-level gain control signals. The I and Q mixers are designed
to have high IIP3 in order not to degrade the adjacent channel
power rejection ratio (ACPR). Since direct upconversion is
used, side-band suppression is less important. This simplifies
RF filtering and thus helps to reduce off-chip components.
Nonetheless, great care has been taken to reduce I/Q LO signal
mismatches. The baseband I and Q signals and LO signals
are closely matched to suppress the carrier leakage below the
specification. The dc-offset which causes the carrier leakage is
also removed by a dc-offset correction circuit and a high-pass
filter (HPF).
Fig. 5 shows the gain-controlled pre-amplifier which drives
an external power amplifier. Because the output of the pream-
plifier is open-drain, the preamplifier requires an external RF
choke as a load. An external inductor with high Q is used as
a load. The preamplifier is designed to have high IIP3 to mini-
mize the spurious components in the transmitter output and thus
achieve high ACPR. The input signal level of Txin coming from
the upconversion mixer is 8 dBm. The total gain control range
is 34 dB with the gain step of 1 dB. Gain is controlled by pre-am-
plifier gain control signals (Pre-amp gain ctrl1—Pre-amp gain
ctrl34) from the Tx gain control block. The total dc current is
58 mA and the maximum output level is 6 dBm. To reduce gain
step variation and improve linearity, gain control is allocated
evenly between the upconversion mixer and the preamplifier.
That is, to increase the overall gain, the preamplifier and upcon-
version mixer gains are increased alternately until that of the
upconversion mixer is saturated.
46
Fig. 4. Upconversion mixer.
Fig. 5. Preamplifier.
2) LNA and Downconversion Mixer: The LNA plays a key
role in determining the SNR of the overall system. Although
high gain is desirable for better sensitivity under weak signal
conditions, it is not desirable under strong signal conditions be-
cause of intermodulation. In particular, in WCDMA applica-
tions, a high peak-to-average power ratio (PAR) requires an
LNA with high linearity. The intermodulated signal is also re-
garded as a noise and thus its level should be kept small so as not
to degrade the SNR. The LNA has a gain-control function to op-
timize both the noise and linearity under any signal conditions.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
Fig. 6 shows the circuit diagram of the LNA. The relationship
between and gain is described by
Gain
(1)
The LNA has a gain control step of 2 dB and the total gain
is 22 dB. This fine control of the LNA gain is advantageous
since the design margin for the following stages becomes re-
laxed. The LNA requires an external matching circuit composed
of and . Since the noise figure is quite sensitive to the
input matching circuit and loss in the input trace, the LNA input
matching should be carefully optimized for both desired noise
figure and gain. However, since sensitivity is generally more
critical, the noise matching is preferred over the gain matching.
The LNA gain is controlled by the baseband modem according
to the RF input signal power to simultaneously meet the noise
and linearity requirements of the system. The LNA in Fig. 6 uses
bond wire inductance for matching and cascode transistor
to isolate the resonator load from the input. The on-chip
resonator load consists of a 1.95-nH inductor and a 2.5-pF
capacitor . Because the LC load bandwidth has very narrow
bandwidth, they are de-Qed with a 300- parallel resistor
to achieve over the 600-MHz bandwidth with negligible degra-
dation in noise performance. Two 60-MHz frequency bands at
LEE et al.: FULL-CMOS 2-GHZ WCDMA DIRECT CONVERSION TRANSMITTER AND RECEIVER
Fig. 6. LNA.
190-MHz duplex separation can be covered with this arrange-
ment and process variations have only a minor effect on the
low-Q resonator load [2]. The ac-coupling circuit composed
of and blocks the low-frequency noise and distortion
from the RF section and the LO inputs of the mixers. Hence
the low-frequency leakage into the mixer output comes mainly
from internal sources.
The output of the LNA is downconverted to baseband I and Q
signals by the quadrature mixer. The baseband signal is filtered
and amplified at the baseband rather than at the intermediate fre-
quency. This eliminates the need for an external image rejection
filter and the channel selection filter such as a bandpass SAW
filter. The image rejection filter and the costly SAW filter are re-
placed with an on-chip low-pass filter. The 12-phase quadrature
downconverter shown in Fig. 7 is composed of two six-phase
single balanced mixers, one for the I-channel and the other for
the Q-channel. Quadrature differential signals, I_out, I_outb,
Q_out, and Q_outb, are passed to the baseband through the HPF.
In a direct conversion receiver, most of the filtering is done after
downconversion and thus the mixer should have high linearity.
The low noise figure is also important in the mixer design since
the overall noise figure is raised if the mixer noise is too high.
The I and Q mixers are designed to have high IIP3 so as not to
degrade SNR. The conversion gain is 7.6 dB and IIP3 is 4 dB. To
prevent output common-mode deviation, common-mode feed-
back formed by PMOS transistors – and resistors –
are added. The dc-offset problem in the direct conversion ar-
chitecture is alleviated by the dc-offset correction method and
careful LO distribution. The NMOS input devices M and M
are designed to have high linearity and sufficient gain with the
total mixer core current of 3.7 mA. On the other hand, the sizes
of the transistors used for commutating switches should be op-
timized to reduce the critical flicker noise.
B. Baseband Blocks
1) Receiver: The receiver baseband architecture is shown in
Fig. 8. It is composed of a five-stage VGAs, two third-order ac-
tive-RC elliptic filters, a elliptic filter, and a
equalizer. The active-RC filter implementation offers high lin-
earity and insensitivity to parasitic effects. The merged filtering
and controlled gain stages optimize the noise and linearity per-
formance of an active-RC filter and minimize the number of
amplifiers in the baseband circuitry. The 114-dB gain control
range can be adjusted digitally in 0.5-dB steps. The gain range
47
Fig. 7. Downconversion mixer.
and step size of each stage are shown in Fig. 8. The VGAs are
merged with the filters. Power detectors detect the power levels
of the output of the VGA and compare them with the reference
level. The gain control block receives the power detect signals
(PD) and sets the gain control signals with the help of the base-
band modem. Fine gain control is achieved with a resolution of
0.5 dB. The gain step of each VGA stage is 2 dB except for the
final stage.
a) Power detector and variable gain amplifier: Fig. 9
shows the power detector circuit. The I channel signal is
represented as and the Q channel signal
is represented as . The power detector
circuit squares the I and Q channel signals, I_out, I_outb,
Q_out, and Q_outb and adds the two terms with the output
being its amplitude , regardless of the phase and time. Its
output is compared with the reference level and the resulting
PD signal is sent to the gain control block.
Accurate gain control is important in designing WCDMA
systems. The receiver chain has the specified required dynamic
range of greater than 80 dB. The actual gain or system gain is
more than 140 dB to cover all signal conditions. The gain control
loop is carefully designed to achieve high adjacent channel se-
lectivity (ACS) and adequate SNR. At the maximum gain of the
baseband VGAs, SNR is a very important design issue. The cir-
cuits have complex gain distribution to achieve enough overall
SNR under any signaling conditions. Although the gain distri-
bution is quite complex, the actual gain control is very simply
48 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003

Fig. 8. Receiver baseband architecture.

Fig. 9. Power detector.

done by the baseband modem and the built-in gain control al- The proper mode can be selected by the baseband modem with
gorithm. Because the gain is controlled in a discrete manner, a three-wire serial interface. Fig. 10 shows the VGA with the
a new interface optimized for the digital gain control is used. dc-offset correction circuit. Gain is determined by the ratio
LEE et al.: FULL-CMOS 2-GHZ WCDMA DIRECT CONVERSION TRANSMITTER AND RECEIVER
Fig. 10. VGA.
of and , so is composed of resistors and switches to
be programmable. The switch control signals ctrl[1: ] are con-
trolled by the gain control block based on the power detect sig-
nals. The number of switch and resistor sets is determined by
the gain control step and the total gain. The variable-gain ampli-
fier is merged with the dc-offset cancellation circuits. To prevent
saturation of the signal, the dc-offset compensation loop filters
out the dc component in the input and compensates the internal
offset of the VGAs. The dc-offset canceling circuit does not re-
quire any external components and occupies a small area. The
dc-offset between and is detected and stored at
and as and , respectively. The latter signals are
added back to and to nullify the dc-offset. However,
if the dc-offset corner frequency is too large, it seriously de-
grades the spectral efficiency, so the high-pass pole is located at
1 kHz with the highest gain setting and moves toward the lower
frequency when the baseband gain is decreased. DC-offset up to
300 mV at the input of the baseband circuitry can be tolerated
over all gain settings.
b) Filter: The complex baseband filters carry out channel
selection and image-free operation. Because it is easier to de-
sign low-pass filters (LPFs) than bandpass filters (BPFs), the
direct conversion receivers can meet the strict requirements for
adjacent channel selection and image rejection compared with
super-heterodyne receivers. The baseband filter provides supe-
rior performance in the presence of strong adjacent interferers.
To meet the stringent requirements of both the gain setting and
49
ACS, the filter stages are optimally distributed. In WCDMA,
a highly linear baseband circuit is needed for high PAR. Thus,
the channel filter circuits must have high linearity and low noise
performance. The outputs of the baseband filter are connected to
the ADCs. The I/Q signals are differential and fully balanced for
high linearity and high common-mode rejection ratio (CMRR).
Design of an analog channel filter is always a compromise be-
tween adjacent channel rejection and intersymbol interference.
The two third-order active-RC and fifth-order elliptic
filters offer sufficient attenuation at the adjacent channel and
less than 105-ns group delay variation at the passband edge,
which can be equalized digitally at the baseband modem.
Fig. 11 shows the circuit diagram of a third-order active-RC
elliptic filter. To reduce the noise contribution, filters are com-
posed of two-stage active-RC filters, a one-stage filter,
and an equalizer. Resistors and capacitors usually vary by about
15 because of process variation, and, accordingly, the cutoff
frequency can vary. To tune the cutoff frequency, variable ca-
pacitors – are used and they are controlled by the tuning
block. The on-chip tuning circuits for frequency response are
needed for the active-RC and filters. The variable ca-
pacitor consists of a main capacitor and tuning capacitors
– . The tuning capacitors are controlled by the signals
[ ] from the tuning circuit. When the cutoff frequency
is too high, the total capacitance value is increased, and vice
versa. The reference for the tuning comes from an accurate
external clock. When tuning is done discretely, it requires a
50 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003

active-RC elliptic filters, and a one-stage VGA. The input

level from the DAC is 0 dBm. The level shifter attenuates the
signal level to 5 dBm to improve the linearity of the upcon-
version mixer and filter noise. The transmitter filter is rather
simple compared to the receiver filter. The cutoff frequency
is maximized within the attenuation specification in order to
meet the group delay requirement easily. Gains of the first
stage and second stage filters are 0 and 7 dBm, respectively.
Therefore, input to the upconversion mixer is 12 dBm. The
VGA receives the 18-level control signal, Gain1(1:18), for gain
control. Its gain range is 36 dB with the gain step of 2 dB.

C. Frequency Synthesizer
The transmitter and receiver incorporate a frequency synthe-
Fig. 11. Active-RC third-order elliptic filter. sizer to support all carrier signal generation with the specified
channel spacing. The channel spacing is 5 MHz and the raster
frequency is 200 kHz. The reference clock frequency can be any
multiple of 200 kHz. Thus, the industry standard 13-, 19.2-. and
19.8-MHz crystal oscillators can be used. This flexibility is in-
tended for the future multimode design of the circuit. All the
information needed to set the channel frequency is provided by
the baseband modem with a programmable three-wire serial in-
terface and is used by the prescaler. The loop filter is also inte-
grated in the circuit to minimize the coupling from the external
noise sources. The included prescaler can operate either in in-
teger- or fractional- mode. The operating mode can be set
by the serial interface. While the integer- mode shows poten-
tially lower spur levels, the fractional- mode offers lower rms
phase error because of the larger loop bandwidth. Since the total
integrated phase error measured in the desired channel band-
width affects the SNR, it should be far below the specification.
The high spur and high phase noise outside the desired channel
also degrade the SNR because of the mixing. The bandwidth of
Fig. 12. Active-RC third-order elliptic filter tuning circuit. the frequency synthesizer is designed to be 20 kHz. The on-chip
VCO is used to minimize the overall system size and noise cou-
pling. The integrated RF oscillator provides a low phase noise
number of capacitors and switches. The proposed tuning cir-
characteristics compatible with an off-chip VCO. The operating
cuit for the active-RC elliptic filter is shown in Fig. 12. Tuning
range of the VCO is internally trimmed by a dedicated coarse
is done in two steps. First, coarse tuning capacitors are selected
tuning algorithm whenever it is activated, and thus no manual
by tuning [ ]. The tuning controls are determined on
trimming is needed. This automatic tuning enables the exact and
power-up depending on which coarse reference range falls
stable LO signal generation against process variation during the
into. Second, after coarse_lock is asserted, the cutoff frequency
manufacturing stage and environmental variation during the op-
is tuned finely. is compared with the reference ranges and
eration. The coarse tuning function of the VCO is fast and ac-
the fine_bias voltage from the fine-tuning block determines the
curate and helps to achieve a fast lock.
bias voltage of the op-amp. Thus, with the two-step tuning, the
number of capacitances can be greatly reduced. In Fig. 12,
is the exact replica of in Fig. 11. When clk0 and clk1 are both IV. EXPERIMENTAL RESULTS
high, node X and are equal to . When clk0 is changed The transmitter and the receiver have been implemented sep-
to low and clk1 remains high, changes according to arately using a 0.35- m 1-poly 5-metal CMOS process. Fig. 14
shows the chip microphotographs. The chip area of both trans-
(2) mitter and receiver is 4.0 mm 5.0 mm. The bond wires are
used for input matching, and several bonding pads are used for
In (2), is determined by an exact external reference clock. If supply and ground to keep the parasitic inductance to an accept-
is too large, goes low, causing to be reduced. On able level. The transmitter is characterized at the output of the
the other hand, if is too small, goes high, causing pre-amplifier and the receiver is characterized at the output of
to be increased. the 6-b ADC for the 4.096-Mcps channel. The received data bits
2) Transmitter: The transmitter baseband structure is shown are captured from the ADC with a logic analyzer and analyzed
in Fig. 13. It is composed of a level shifter, two third-order in the frequency domain with a fast Fourier transform (FFT) [2].
LEE et al.: FULL-CMOS 2-GHZ WCDMA DIRECT CONVERSION TRANSMITTER AND RECEIVER
Fig. 13. Transmitter baseband architecture.
(a)
(b)
Fig. 14. Chip microphotograph. (a) Transmitter. (b) Receiver.
The frequency range covered by the transmitter is from 1920
to 1980 MHz. Fig. 15 shows the measured LO phase noise,
indicating 100 dBc/Hz at a 1-kHz offset and 115 dBc/Hz at
a 1-MHz offset with 720 MHz center frequency. The rms jitter
51
Fig. 15. LO phase noise and rms jitter.
is 0.47 . Fig. 16(a) shows the 10-b DAC output spectrum and
Fig. 16(b) shows the output of the VGA in the transmitter when
the external 80 dBm signal is applied to the DAC output. The
resolution bandwidth is 100 kHz. The gain control range of the
transmitter VGA is about 35 dB. Fig. 17(a) shows the output
spectrum of the transmitter preamplifier and the upconversion
mixer. The dynamic range of the preamplifier and transmitter
VGA are 15 and 35 dB, respectively, which results in a 50-dB
overall transmitter dynamic range. The additional variable gain
power amplifier has a 25-dB dynamic range. Hence, the overall
dynamic range including the external power amplifier and the
implemented transmitter is 75 dB. The maximum output power
of the preamplifier is 6 dBm. As Fig. 17(a) shows, the ACPR of
the transmitter output is 38 dB at 1.92 MHz.
The RF input frequency range of the receiver is from 2110
to 2170 MHz. Measurement results show that overall noise
figure of the receiver is 4.0 dB and its dynamic range is 80 dB.
Fig. 17(b) shows the output CDMA spectrum measured at the
output of the I/Q channel selection filter when a 30-dBm
CDMA signal of 4 MHz bandwidth at 2140 MHz is applied.
The measured SNR is 40 dB and the I/Q gain mismatch is
0.9 dB. The measured IIP3, IIP2, and 1-dB compression of the
receiver are 9 dBm, 40 dBm, and 25 dBm, respectively.
The LO-to-RF isolation is better than 66 dB at all frequencies.
I/Q phase and amplitude imbalance of less than 1 and 0.9 dB
52
(a)
(b)
Fig. 16. Transmitter. (a) DAC output spectrum. (b) VGA output spectrum.
TABLE I
MEASURED PERFORMANCE OF TRANSMITTER AND RECEIVER
meets the requirements of the receiver. The sensitivity can be
calculated for the receiver from the thermal noise floor at the
RF band, receiver noise figure, processing gain at the desired
bit rate, and the minimum required SNR for a given bit error
rate. When QPSK signals are detected, 6.7 dB SNR is required
for 10 BER [2]. The measured sensitivity is, therefore,
115.4 dBm. The power dissipation of the transmitter and the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
(a)
(b)
Fig. 17. (a) Transmitter preamplifier output spectrum. (b) Receiver I/Q
channel output spectrum.
receiver are 363 and 396 mW, respectively. Table I summarizes
the measured performance of the transmitter and the receiver.
V. CONCLUSION
In this paper, we presented a prototype full-CMOS trans-
mitter and receiver based on the direct conversion architecture
for use in a complete 2.0-GHz WCDMA RF system with an ad-
ditional power amplifier for third-generation cellular commu-
nications. The use of external components are limited to input
matching and supply decoupling for RF and ground stabiliza-
tion. A multiphase reduced frequency mixer and the dc-offset
cancellation technique are used in the direct conversion archi-
tecture to solve the problems associated with the direct conver-
sion. Gain control is merged into the baseband filters and VGAs
to optimize the linearity of the system, reduce the noise, and im-
prove the sensitivity. VGAs with a dc-offset cancellation loop
eliminate the dc-offset in each stage. An overall dynamic range
of 50 dB in the transmitter, an overall noise figure of 4.0 dB, and
a dynamic range of 80 dB in the receiver are measured.
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wide dynamic range active filters,” IEEE J. Solid-State Circuits, vol. 33,
pp. 2219–2231, Dec. 1998.
Kang-Yoon Lee was born in Jeongup, Korea, in
1972. He received the B.S. and M.S. degrees from
Seoul National University, Seoul, Korea, in 1996
and 1998, respectively. He is currently working
toward the Ph.D. degree in electrical engineering at
the same university.
His research interests include high-speed serial bus
for data communications and RF circuit and system
design for wireless communication.
Seung-Wook Lee was born in Seoul, Korea, in 1971.
He received the B.S. and M.S. degrees in electronics
engineering from Seoul National University, Seoul,
Korea, in 1995 and 1997, respectively. He is currently
working toward the Ph.D. degree in electrical engi-
neering at the same university.
His research interests include CMOS RF circuit
design and high-speed communication interface.
Mr. Lee is the winner of the bronze prize of the
IC design contest held by the Federation of Korean
Industries in 1995.
Yido Koo was born in Seoul, Korea, in 1973. He re-
ceived the B.S. and M.S. degrees from Seoul National
University, Seoul, Korea, in 1996 and 1998, respec-
tively. He is currently working toward the Ph.D. de-
gree at the same university.
His research interests include RF building blocks
and systems for wireless communication and high
speed interface for data communications. Currently,
he is developing a low-noise frequency synthesizer
for CDMA and GSM applications.
Hyoung-Ki Huh was born in Seoul, Korea. He
received the B.S. and M.S. degrees in electrical
engineering from Seoul National University, Seoul,
Korea, in 1998 and 2001, respectively. He is cur-
rently working toward the Ph.D. degree in electrical
engineering at the same university.
His research interests are in the area of RF cir-
cuits and systems with emphasis on the fractional fre-
quency synthesizer.
Hee-Young Nam received the B.S. degree from the Korea Advanced Institute
of Science and Technology, Taejeon, in 1998 and the M.S. degree from Seoul
National University, Seoul, Korea, in 2001, both in electrical engineering.
Her research interests are in the area of RF circuits and systems.
53
Jeong-Woo Lee received the B.S. and M.S. degrees
in electronics engineering and the Ph.D. degree in
electrical engineering from Seoul National Univer-
sity, Seoul, Korea, in 1994, 1996, and 2000, respec-
tively.
He is currently a Manager with the WCDMA team
of GCT Semiconductor Inc., San Jose, CA. His cur-
rent research interests include CMOS transceiver cir-
cuitry for highly integrated radio applications.
Joonbae Park received the B.S. and M.S. degrees
in electronics engineering and the Ph.D. degree in
electrical engineering from Seoul National Univer-
sity, Seoul, Korea, in 1993, 1995, and 2000, respec-
tively.
In 1998, he joined GCT Semiconductor Inc., San
Jose, CA, as Director of the Analog Division. He is
currently involved in the development of CMOS RF
chip sets for WLL, WCDMA, and wireless LAN. His
other research interests include data converters and
high-speed communication interfaces.
Dr. Park received the Best Paper Award of VLSI Design’99, Goa, India.
Kyeongho Lee was born in Seoul, Korea, in 1969. He
received the B.S., M.S., and Ph.D. degrees in elec-
tronics engineering from Seoul National University,
Seoul, Korea, in 1993, 1995, and 2000, respectively.
He was with Silicon Image, Inc., Sunnyvale, CA,
as a Member of Technical Staff, where he worked on
CMOS high-bandwidth low-EMI transceivers. He is
currently with GCT Semiconductor Inc., San Jose,
CA, as a Chief Executive Officer. His research in-
terests include various CMOS high-speed circuits for
wire/wireless communication systems and integrated
CMOS RF systems.
Deog-Kyoon Jeong received the B.S. and M.S. de-
grees in electronics engineering from Seoul National
University, Seoul, Korea, in 1981 and 1984, respec-
tively, and the Ph.D. degree in electrical engineering
and computer sciences from the University of Cali-
fornia, Berkeley, in 1989.
From 1989 to 1991, he was with Texas Instruments
Inc., Dallas, TX, where he was a Member of Tech-
nical Staff and worked on the modeling and design
of BiCMOS gates and the single-chip implementa-
tion of the SPARC architecture. He joined the faculty
of the Department of Electronics Engineering and Inter-University Semicon-
ductor Research Center, Seoul National University, as an Assistant Professor in
1991. He is currently a Professor of the School of Electrical Engineering, Seoul
National University. His main research interests include high-speed I/O circuits,
VLSI systems design, microprocessor architectures, and memory systems.
Wonchan Kim was born in Seoul, Korea, on De-
cember 11, 1945. He received the B.S. degree in elec-
tronics engineering from Seoul National University,
Korea, in 1972 and the Dip.-Ing. and Dr.-Ing. De-
grees in electrical engineering from the Technische
Hochschule Aachen, Germany, in 1976 and 1981, re-
spectively.
In 1972, he was with Fairchild Semiconductor
Korea as a Process Engineer. From 1976 to 1982, he
was with the Institut fur Theoretische Electrotecnik
RWTH Aachen. Since 1982, he has been with the
School of Electrical Engineering, Seoul National University, where he is cur-
rently a Professor. His research interests include development of semiconductor
devices and design of analog/digital circuits.