11. Registers & Counters 11.1.

Registers
 Objectives  A register is a memory device that can be used to
This section deals with some simple and useful sequential store more than one bit of information.
circuits. Its objectives are to:  A register is usually realized as several flip-flops with
 Introduce registers as multi-bit storage devices. common control signals that control the movement of
 Introduce counters by adding logic to registers data to and from the register.
implementing the functional capability to increment and/or  Common refers to the property that the control signals
decrement their contents. apply to all flip-flops in the same way
 Define shift registers and show how they can be used to
 A register is a generalization of a flip-flop. Where a flip-
implement counters that use the one-hot code. flop stores one bit, a register stores several bits
 Reading Assignment  The main operations on a register are the same as for any
 Counters: Chapter 7, Sections 7.8 through 7.11 in Brown & storage devices, namely
Vranesic.  Load or Store: Put new data into the register
 Verilog
description of counters: Chapter 7, Sections 7.13 in  Read: Retrieve the data stored in the register (usually without
Brown & Vranesic. changing the stored data

Elec 326 11.1 Registers & Counters Elec 326 11.2 Registers & Counters

D0 D Q Q0
 Control Signals module reg1 (STO, CLR, D, Q);
Q parameter n = 16;
 When they are asserted, they initiate an action in the CLR
register input STO, CLR;
input [n-1:0] D;
 Asynchronous Control Signals cause the action to take output [n-1:0] Q;
D1 D Q Q1
place immediately reg [n-1:0] Q;
 Synchronous Control Signals must be asserted during a Q
CLR always @(posedge STO or negedge CLR)
clock assertion to have an effect
if (CLR ==0) Q <= 0;
 Examples else Q <= D;
 On the following three registers, which control signals are Dn-1 D Q Qn-1 endmodule
asynchronous and which are synchronous? How are the
control signals asserted? STO Q
CLR

CLR

Elec 326 11.3 Registers & Counters Elec 326 11.4 Registers & Counters

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 D0 J Q Q0 D Q Q0
D0
K Q Q

D1 J Q Q1
D Q Q1
K Q D1
Q

D n-1 J Q Qn-1
K Q
D Q Qn-1
LD Dn-1
Q
LD
CLR
CLK CLR
OE CLK
OE

Elec 326 11.5 Registers & Counters Elec 326 11.6 Registers & Counters

 Verilog description of previous two registers 11.2. Counters

module reg2 (CLK, CLR, LD, OE, D, Q);  A counter is a register capable of incrementing and/or
parameter n = 4; decrementing its contents
input CLK, CLR, LD, OE;
input [n-1:0] D;
output [n-1:0] Q;
reg [n-1:0] IQ, Q;
Q ← Q plus n
integer k; Q ← Q minus n
always @(posedge CLK)
if (CLR) IQ <= 0;  The definition of "plus" and "minus" depend on the way
else if (LD) IQ <= D; the register contents encode the integers
always @(OE)  Binary Counters: Encode the integers with the binary
if (OE) Q = IQ; number code
else Q = 'bz;

endmodule

Elec 326 11.7 Registers & Counters Elec 326 11.8 Registers & Counters

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 Example: 3-bit binary counter:  Example: 3-bit binary up/down counter
000 0 1
001 000 001 00 0 1 11 0 01
0 1
010 00 1 0 00 0 10
001 010 1 2
plus 01 0 0 01 0 11
011 010 011 2 3 01 1 0 10 1 00
100 011 100 3 4 10 0 0 11 1 01
1 0 1 minus 100 101 4 5 10 1 1 00 1 10
110 101 110 5 6 11 0 1 01 1 11
111 110 111 6 7 11 1 1 10 0 00
000 111 000 7 0 TransistionTable
•
•
Transistion Table State Table
•

Count Sequence  Example: Binary mod 6 counter

000 001
001 010 0 1 2
010 011
011 100
100 101
101 000 5 4 3
 What does the counter count? 110 xxx
 The output signals are just the state variables 111 xxx State Diagram
Transistion Table
Elec 326 11.9 Registers & Counters Elec 326 11.10 Registers & Counters

 Design of a Binary Up Counter

1 J Q

K Q

J Q

K Q

J Q

K Q

J Q

K Q

CK
 Qi toggles on every clock cycle where Qj = 1, for i > j ≥ 0 Binary Up Counter

Elec 326 11.11 Registers & Counters Elec 326 11.12 Registers & Counters

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 Design of a Binary Down Counter

 Qi toggles on every clock cycle where Qj = 0, for i > j ≥ 0

Binary Down Counter

Elec 326 11.13 Registers & Counters Elec 326 11.14 Registers & Counters

 Synchronous, Series-Carry Binary Counter  Synchronous, Parallel-Carry Binary Counter

1 J Q J Q J Q J Q 1 J Q J Q J Q J Q
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
K Q K Q K Q K Q K Q K Q K Q K Q

CK CK

Q=14 Q=15 Q=0

Q=14 Q=15 Q=0 TW
TW
CK
CK
Q3 Q3

Q2 Q2
Q1 Q1
tPFF tPFF
Q0 = JK1 Q0 = JK1
tPG tPG
JK2 JK2
tPG tPG
JK3 JK3
tsu tsu

TW ≥ tPFF + (n-2)tPG + tsu (for n≥2) TW ≥ tPFF + tPG + tsu (for n≥3)

Elec 326 11.15 Registers & Counters Elec 326 11.16 Registers & Counters

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  Verilog description of the 74x163
 Asynchronous Counters
1 J Q 1 J Q 1 J Q 1 J Q module V74x163 (CLK, CLR_L, LD_L, ENP, ENT, D, Q, RCO);
CK input CLK, CLR_L, LD_L, ENP, ENT;
1 K Q 1 K Q 1 K Q 1 K Q
input [3:0] D;
 Typical MSI counter chip output RCO;
74LS163
output [3:0] Q;
reg [3:0] Q;
CLR
LD QA reg RCO;
ENP QB
ENT QC
A QD always @(posedge CLK)
B
C RCO if (CLR_L == 0) Q <= 4'b0000;
D
else if (LD_L == 0) Q <= D;
 LD and CLR are synchronous else if (ENT & ENP) Q <= Q +1;
 LD asserted during the rising edge of the clock loads the register from
always @(Q or ENT)
ABCD.
if (Q == 15 && ENT == 1) RCO = 1;
 CLR asserted during the rising edge of the clock clears the counter else RCO = 0;
 CLR overrides LD
 LD overrides EN endmodule
 RCO = QD•QC • QB • QA • ENT, used for cascading chips

Elec 326 11.17 Registers & Counters Elec 326 11.18 Registers & Counters

 Verilog description of an up/down counter  Verilog description of mod-n counters

module updowncount (R, Clock, L, E, up_down, Q);
module upmodn (Ck, Q); module dwnmodn (Ck, Q);
parameter n = 8;
parameter n = 6; parameter n = 5;
input [n-1:0] R;
input Ck; input Ck;
input Clock, L, E, up_down;
output [3:0] Q; output [3:0] Q;
output [n-1:0] Q;
reg [3:0] Q; reg [3:0] Q;
reg [n-1:0] Q;
integer direction;
always @(posedge Ck) always @(posedge Ck)
if (Q == n) if (Q == 0)
always @(posedge Clock)
Q <= 0; Q <= n;
begin
else else
if (up_down) direction = 1;
Q <= Q + 1; Q <= Q -1;
else direction = -1;
endmodule
if (L) Q <= R;
- Q + direction; endmodule
else if (E) Q <=
end

endmodule

Elec 326 11.19 Registers & Counters Elec 326 11.20 Registers & Counters

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 Design of Mod n Counters  Decoding Binary Counter States
 Mod 6 Up Counter 74LS163 Y0 /S0
CK

Y1 /S1 Q0
CLK Y2 /S2
CLR QA A Q1
CK QB Y3 /S3
1 LD QA B
QC Y4 /S4 Q2
Q0 1 ENP QB C
Y5 /S5
1 ENT QC /S6 /S0
Q1 Y6
A QD Y7 /S7
B /S1
Q2 C RCO
/CLR D /S2
0 1 2 3 4 5 0 1 2

 Mod 5 Down Counter

 The decoding spikes are hazzards that can not be designed
out
74LS169
CK CLK  The following circuit will mask the decoding spikes, at the
0 U/D
Q0 LD QA cost of delaying the outputs one clock cycle.
0 ENP QB
Q1 0 ENT QC
0 A QD Y0
Q2 0 B Y1
/LD 1 C RCO
0 QA A Y2
4 3 2 1 0 4 3 2 D Y3
QB B REG
QC C Y4
Y5
Y6
Y7
CLK

Elec 326 11.21 Registers & Counters Elec 326 11.22 Registers & Counters

11.3. Shift Registers  Example: 74LS194

CLR S1 S0 Action QA* QB* QC* QD*

S1 QD
S0 QC 0 0 hold QA QB QC QD
LIN QB
D QA 0 1 shift right RIN QA QB QC
B
C
1 0 shift left QB QC QD LIN
A
RIN
1 1 load A B C D
 How would you add a control signal to control when the
shift register shifted?
 How would you add parallel input capability and why  Shift left is from A to D
would you want to?  Shift right is from D to A
 What kind of control signals are needed?  CLR is asynchronous
 Is the shift register drawn above a left shifter or a right
shifter?
 How would you make a shift register that could shift either
left or right and what control signals would you need?

Elec 326 11.23 Registers & Counters Elec 326 11.24 Registers & Counters

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 Verilog Description Of A Shift Register  Ring Counters
module shift4 (D, LD, LI, Ck, Q);
input [3:0] D;
input LD, LI, Ck;
output [3:0] Q;
reg [3:0] Q;

always @(posedge Ck)

if (LD)
Q <= D;
else
begin
Q[0] <= Q[1];
Q[1] <= Q[2];
Q[2] <= Q[3];
Q[3] <= LI;
end

endmodule

Elec 326 11.25 Registers & Counters Elec 326 11.26 Registers & Counters

 Self-Correcting Ring Counter  Johnson counter, switch-tail counter, moebius counter

Elec 326 11.27 Registers & Counters Elec 326 11.28 Registers & Counters

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 Self-Correcting Johnson Counter 11.4. Design with MSI Components (Counters)
 Approach
 The state diagram of a counter is essentially a cycle.
 Whenever a state diagram is close to a cycle, with only a
few other edges, it can be realized using a counter by
adding logic to take care of the transitions that are not in
 Odd Length Johnson Counter the cycle.
 The following control inputs on counters are useful:
 ENABLE: Asserted to cause the counter to count in its natural
0000 1000 1100 1110
count sequence. Deasserted to cause the counter to hold its current
state.
 CLEAR: Used to realize a count sequence that is not a power of
0001 0011 0111
two and for initialization.
 LOAD: Used to modify the natural count sequence by forcing the
 This counter is also self-correcting counter to a given state.

Elec 326 11.29 Registers & Counters Elec 326 11.30 Registers & Counters

 Example: X'
Y
0 6

X Z

1 Y' 5 Y'•Z' Assert ENABLE when

1 1
Y•Z'
2 3
Z 1
Z'
Assert ENABLE when
The counter is in state 0 and X = 1,
The counter is in state 1,
The counter is in state 2 and Z = 1,
The counter is in state 3,
The counter is in state 4, or
The counter is in state 5 and Z =1.
The counter is in state 0 and X = 1,
The counter is in state 1,
The counter is in state 2 and Z = 1,
The counter is in state 3,
4 The counter is in state 4, or
The counter is in state 5 and Z =1.
Assert CLEAR when
The circuit is to be initialized, or
The counter is in state 6 and Y = 1.
Assert LOAD when
The counter is in state 5 and Y,Z = 1,0 (Load 100)
The counter is in state 6 and Y = 0 (Load 011)

Assert CLEAR when

The circuit is to be initialized, or
The counter is in state 6 and Y = 1.
Assert LOAD when
The counter is in state 5 and Y,Z = 1,0 (Load 100)
The counter is in state 6 and Y = 0 (Load 011)

Elec 326 11.31 Registers & Counters Elec 326 11.32 Registers & Counters

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 Example:
11.5. Tips & Tricks
X0' X1'•X2' X3' X4' X5' X6•x7'
 Don't use asynchronous counters, especially if the
INIT 0
X0
1
X1
2
X3
3
X4
4
X5
5
X7
6
clock period is close to the flip-flop propagation
delay.
X1'•X2
X6•X7'  Don't build mod n counters from binary counters with
1 asynchronous clears.
 Comment: A state table for this diagram would have 7 rows and 256
columns

CLEAR = (Q=1)•X1'•X2 + INIT 11.6. Pitfalls

LOAD = (Q=5)•X6•X7' + (Q=6)
 Detecting the wrong state for resetting a mod n
A = (Q=6)
counter.
B = (Q=5 )
C= 0
ENABLE = (Q=0)•X0 + (Q=1)•X1 + (Q=2)•X3 + (Q=3)•X4
+ (Q=4)•X5 + (Q=5)•X7

Elec 326 11.33 Registers & Counters Elec 326 11.34 Registers & Counters

11.7. Review
 Register control signals and assertions.
 Binary counters and their operations.
 Reset, Load, Output Enable.
 Counter timing; maximum clock frequency.
 Mod-n counters
 Synchronous vs. asynchronous load and reset signals.
 Shift registers and shift register counters.
 Ring counters, Johnson counters, etc
 Self-correcting counters
 Counter realization of sequential circuits

Elec 326 11.35 Registers & Counters