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5.1 Introduction

The principle of operation of the MOS field-effect transistor, or MOSFET, is

relatively easy to understand. Indeed, the patents for what we would now call a field-
effect transistor, were issued to Lilienfeld [5.1] and Heil [5.2] in the 1930’s. Shockley
and his team were actively exploring means of making a field-effect transistor in the
1940’s when they invented the bipolar junction transistor. Despite the conceptual
simplicity of the MOSFET – it is basically a voltage-controlled resistor where resistance
value can be controlled by the gate field or voltage, the development of a working
MOSFET by Kahng and Atalla [5.3] and others had to wait till 1960 for silicon
technology to be sufficiently advanced to produce high-quality Si/SiO2 interfaces.

In this chapter, we look at the physics of operation of the long-channel MOSFET,

that is, the transistor with a channel length L greater than about 1 µm. For the long
channel transistor, we can make the important “gradual channel approximation” which
allows us to decouple the 2-D equations describing the transistor into two 1-D equations,
which can be solved analytically. Early derivations of the characteristics of MOSFETs
are due to various workers such as Ihantola and Moll [5.4], Hofstein and Heiman [5.5]
and Sah [5.6]. For transistors with channel lengths less than about 1 µm, the gradual
channel approximation is not valid, and a variety of “short channel effects” have to be
taken into account. These will be discussed in the next chapter.

5.2 Simplified I-V models of the MOSFET

The MOS transistor structure is shown schematically in Fig 5.1. The device
shown here is an n-channel MOSFET, in which current flows between source and drain
due to electrons. The fundamental principle of the MOSFET is as follows: when a gate
voltage VGS is applied to the gate (with respect to the source and substrate which are both
grounded), an inversion layer is induced at the Si/SiO2 surface if VGS > VT. The inversion
layer, called the channel, connects up the source and drain. If a positive voltage VDS is
applied to the drain, electrons flow through the channel, entering at the source end and
leaving at the drain end (hence the names). This current ID can be modulated by changing
VGS which changes the number of electrons in the inversion layer. Hence a change in the
input voltage VGS can cause a change in the output current ID, thereby producing
transistor action. Similarly if VGS is switched to 0 V or to a high voltage (> VT), the
channel can be turned off or on, producing switching action.

In this section, we will derive some simple I-V characteristics of the MOSFET,
assuming that the device essentially acts as a (variable) resistor between source and drain,
and only drift or ohmic currents need to be calculated. This condition will be relaxed in
the next section, where diffusion currents are included.

Fig. 5.1 Schematic structure of an n-channel MOSFET. L and W are the length and width respectively of

Note that the MOSFET is a 4-terminal device, with the gate (G), source (S), drain
(D), and substrate or body (B) as the four terminals. Each terminal can have an
independent voltage applied to it, usually measured with respect to the source, which is at
ground. At present, we will consider the body also to be at ground, or VBS = 0 V.

Note also that the MOSFET is basically a two-dimensional device. The gate
voltage VGS produces a field in the vertical (x) direction, which induces charge in the
silicon, including charge in the inversion layer. The voltage VDS produces a field in the
lateral (y) direction, and current flows (predominantly) in the y direction. Strictly
speaking, we must solve the 2-D Poisson and continuity equations to evaluate the I-V
characteristics of the device. These are analytically intractable. We therefore resort to the
gradual channel approximation described below.

To find the current flowing in the MOS transistor, we need to know the charge in
the inversion layer. This charge, QI(y) (per cm2) is a function of position along the
channel, since the potential varies going from source to drain. We assume that QI(y) can
be found at any point y by solving the Poisson equation only in the x direction, that is
treating the gate-oxide-silicon system in the channel region very much like a MOS
capacitor. This is tantamount to assuming that vertical electric field Ex is much larger
than the horizontal electric field Ey, so that the solution of the 1-D Poisson equation is
adequate. This gradual channel approximation (the voltage varies only gradually along
the channel) is quite valid for long channel MOSFETs since Ey is small. Having found
QI(y), it is now possible to solve the continuity equation in one dimension along the y
direction to find the current. Thus the gradual channel approximation allows us to
decouple the 2-D equations into two separate 1-D equations which can be solved.

The applied drain voltage VDS produces a varying potential V(y) along the
channel, going from 0 V at the source to VDS at the drain. This potential tends to reverse
bias the channel (n) to substrate (p) junction. The band diagram for the MOSFET along
the x direction is different from that of a MOS capacitor. In the latter case, the quasi-
fermi levels in the silicon coincide and can be represented as the fermi level (see Section
2.3). For the MOSFET, as in the case of a reverse-biased n-p junction, the quasi-fermi
levels are separated by the applied voltage, which is V(y) at any point y along the channel.
This is shown in Fig. 5.2. Since there is almost no current flowing in the vertical (x)
direction, we can assume that the gradient of the quasi-fermi levels [5.7] in that direction
is zero, and therefore the quasi-fermi levels are almost flat. Of course, this is not quite
true, and the electron level εfn gradually creeps upwards and merges with εfp deep in the
bulk, which is, for all practical purposes, at equilibrium.

Fig. 5.2 Band diagram along the x direction at any point y for a MOSFET. At the source end, V(y) = 0,
and the two quasi-fermi levels coincide. At the drain end, the quasi-fermi levels are separated by qVDS.

In the case of a MOS capacitor, the surface band bending necessary to produce
inversion is about 2φB (Section 2.2). For the nMOSFET, the conduction band must come
close enough to εfn, so that the surface potential ψs required to achieve inversion is

ψs(y) = 2φB + V(y) . (5.1)

At the source, the surface potential is ψs(0) = 2φB, and at the drain it is ψs(L) = 2φB + VDS.

We now make use of the gradual channel approximation to calculate QI(y). We
invoke equations very similar to the MOS capacitor equations, assuming we are
considering a 1-D case. The inversion charge QI(y) is

QI(y) = QS(y) – QD(y) , (5.2)

where QS(y) and QD(y) are the position-dependent total semiconductor charge and
depletion layer charge respectively. As in the case of the MOS capacitor (Eq. (2.10)), the
semiconductor charge is given (assuming VFB = 0V) by :

QS(y) = – Cox(VGB – ψs(y)) . (5.3)

Note that in this equation, we must measure the gate voltage with respect to the body, as
we do in the MOS capacitor; however since we are currently assuming the body and
source both to be grounded, we can replace VGB by VGS. The negative sign in Eq. (5.3)
simply refers to the fact that the charge in the semiconductor for an n-channel MOSFET
is negative.

The depletion layer charge QD(y) can be written, using the depletion
approximation, as

QD(y) = – q NA xd(y)

= – 2ε s qN A [V ( y ) + 2φ B ] , (5.4)

where xd(y) is the depletion width. Note that QD(y) and xd(y) are functions of y, increasing
from source to drain due to the increasing bias along the channel. Using Eqs. (5.1) to
(5.4), we can write

QI(y) = – Cox {VGS − V ( y ) − 2φ B } + 2ε s qN A (V ( y ) + 2φ B ) (5.5)

We are now ready to solve the continuity equation in the y direction to find the
current, using Eq. (5.5). The steady state 1-D continuity equation for electrons (ignoring
generation and recombination) is simply

Jn = 0
or Jn = constant (5.6)

In this section, we assume that the current flowing is primarily a drift current, due to the
electric field Ey caused by the applied drain voltage VDS. This is quite valid in strong
inversion. As a consequence, Eq. (5.6) can be written as

Jn = qμn n(y) Ey(y) = constant (5.7)

We can integrate this over x and z (the dimension corresponding to the width W) to get
the drain current ID :


ID = – q Wμn ∫ n( y) E ( y ) dx ,
y (5.8)

where we have assumed that μn is independent of x. The negative sign in Eq. (5.8) arises
because Jn refers to current flowing in the positive y direction, and ID is conventionally
measured as flowing into the drain terminal (see Fig. 5.1).

Since Ey is independent of x (εfn and εfp do not change with x near the interface),
and using

QI (y) = – q ∫ n( x, y ) dx,

and Ey = – (∂V ( y ) ∂y ) ,

⎛ ∂V ⎞
we get : ID = – W μn QI (y) ⎜⎜ ⎟⎟ (5.9)
⎝ ∂y ⎠

Since ID like Jn is constant along y we can integrate Eq.(5.9) from y = 0 to L to get

∫ [{V ]

ID = + μn (W L )C ox GS − V − 2φ B } − γ V + 2φ B dV , (5.10)

where γ = 2ε s qN A C ox is called the “body-effect” factor, and has units of V1/2. In

deriving this equation, we had assumed in Eq. (5.3) that the flat-band voltage VFB = 0. If
this is not so, all we need to do is replace VGB (or VGS) by VGB – VFB or VGS – VFB.

5.2.1 The “Text-Book” Model Output drain characteristics of the MOSFET

Although Eq.(5.10) can be integrated analytically, (see section 5.2.2), we first

make a further approximation which results in what is often called the “text-book”model
for the drain characteristics of the MOSFET.

We assume that the depletion charge QD(y) is not a function of y, but rather is
constant at the value near the source, namely

QD(y) = constant = – 2ε s qN A (2φ B ) (5.11)

By making the assumption that QD (and hence the depletion width) is a constant, we can
eliminate the troublesome square-root term in Eq. (5.10), which now becomes :


ID = μn Cox (W L) ∫ {V
GS − VT − V }dV , (5.12)

where we have used VT = 2φB + γ 2φ B . This equation is easily integrated to give

⎧ 1 2 ⎫
ID = μ Cox (W L ) ⎨(VGS − VT )VDS − VDS ⎬. (5.13)
⎩ 2 ⎭

This is the well-known “text-book” equation relating the drain current ID to the gate and
drain voltages. Note that besides achieving a simple equation, we have also been able to
combine terms together to get the physically important threshold voltage VT.

Eq.(5.13) shows that at low drain voltages, the MOSFET behaves like a linear
resistor of resistance 1 / μC ox (W L )(VGS − VT ). The resistance can be varied by changing
VGS. As VDS increases, ID dose not increase linearly, but starts falling off. The reason for
this is that as VDS increases, there is less charge QI near the drain, and as a consequence
the resistance starts increasing. ID reaches a peak at VDS = (VGS − VT), and according to
Eq.(5.13), IDS should decrease beyond this value of VDS. In reality, the current ID does not
decrease but remains constant at the peak value IDsat beyond VDsat = (VGS − VT):

(VGS − VT )2
IDsat = μC ox (W L ) , (VDS > VDsat ) (5.14)
The region for VDS<VDsat is known as the triode or linear region, and for VDS>VDsat as the
saturation region, as shown in Fig.5.3.

Fig. 5.3 Ideal MOSFET characteristics showing triode and saturation regions

At the onset of saturation, the inversion charge QI at the drain is zero. This can be
seen by fact that at the drain end, the voltage across the MOS system is VGD = VGS − VDS
= VT. This is just enough to reach the onset of inversion when the charge QI is zero. This
condition is called “pinch-off”. For VDS > VDsat, the current hardly increases at all. The
extra voltage VDS − VDsat drops across a small depletion region near the drain. The current
is still determined by the resistance of the un-pinched-off part of the channel (the
depletion region provides no resistance since the electrons speed across it aided by a large
accelerating electric field, similar to what happens in a reverse-biased pn junction). This
resistance is almost the same as that at VDS = VDsat since the length of the inversion layer
L′ is only slightly smaller that the channel length L (see Fig. 5.4), and the voltage drop
across it is also the same, VDsat. The output current does increase slightly in saturation as
L′ decreases with increasing VDS. This effect is called channel-length modulation (CLM),
and is discussed in more detail in Chapter 6.

Fig.5.4 Schematic representation of a MOSFET in saturation showing the pinched-off (depletion) region

In summary, some of the salient features of the output drain characteristics of the
MOSFET are : (1) the drain current ID starts to flow in substantial measure for VGS > VT
(for VGS < VT, we have the subthreshold regime, which is discussed later in Sec.5.5). (2)
For very small VDS, ID is linear with VDS. (3) In saturation, the current increases
quadratically with VGS – VT. (4) The locus of points separating the triode and saturation
regions is a parabola. (5) In saturation, the output current increases slightly because of
channel length modulation. Body Effect

The substrate or body in a MOSFET may not always be at the same voltage as the
source, that is, VSB ≠ 0 V. We often encounter devices in which the source-body junction
is reverse biased (VSB positive for an n-channel transistor). In this case, we cannot use VGB
= VGS in Eq.(5.3), as we did previously. Rather, we use VGB = VGS + VSB. Furthermore,
the separation of the quasi-fermi levels in the silicon is now V(y) + VSB, because of the
additional reverse bias appearing because of the bulk voltage. As a consequence, Eq.(5.5)
now becomes, continuing with the assumption that QD (and xd) are independent of y :

QI(y) = − Cox{VGS + VSB – V(y) − VSB − 2φB} + 2ε s qN A (VSB + 2φ b ) (5.15)

We can now go through the calculation of the drain current as in Sec., and the
result is still Eq.(5.13). The only difference is that we now replace the threshold voltage
VT by

2ε S qN A (VSB + 2φ B )
VT′ = 2φB + . (5.16)

In the above equation, VT′ is the threshold voltage including the “body effect” that is,
when the body is at a different voltage from the source. Also, we have ignored VFB; if VFB
≠ 0, it can just be added to the RHS of Eq.(5.16). It can be seen that VT′ > VT because of
the larger depletion region caused by reverse source-body bias. The gate voltage as to
support a larger depletion charge, and so a higher voltage has to be applied to the gate
(with respect to the source) to produce the onset the inversion.

This increase in threshold voltage due to body bias has important consequences in
many MOS circuits. The increase in the threshold voltage is given by

ΔVT = VT′ − VT = γ {V SB }
+ 2φ B − 2φ B . (5.17)

Sometimes, if VSB >> 2φB, Eq.(5.17) is approximated by ΔVT ≈ γ VSB . Variation of Potential along the Channel

We can now get some insight into the operation of the MOSFET by considering
how the potential V(y) varies along the channel form source to drain [5.8]. For very small
applied drain voltages, the MOSFET has a uniform channel and the voltage V(y)
increases linearly with y from 0 V at y = 0 (source) to VDS at y = L (drain).

For larger values of VDS we can integrate Eq.(5.9) with the appropriate value of ID
and QI(y). This gives

y V ( y)

D dy = ∫ Wμ C {V
n ox GS − VT − V }dV , (5.18)

where we have used QI(y) = − Cox{VGS −VT − V(y)}. Eq (5.18) is similar to Eq.(5.12),
except that we now integrate upto V(y) instead of VDS. This gives

y = (VGS − VT) V − . (5.19)
Wμ n C ox 2

Solving the quadratic equation for V(y), and using ID given by Eq.(5.13), we get,

V(y) = (VGS − VT) − (VGS − VT )2 − ⎛⎜ y ⎞⎟2VDS ⎛⎜VGS − VT −
V DS ⎞
⎟ . (5.20)
⎝ L⎠ ⎝ 2 ⎠

V(y) is plotted in Fig.5.5a. For VDS small, Eq.(5.20) reduces to V(y) = (y/L)VDS as
expected. The electric field E(y) = − (∂V/∂y) is almost constant along the channel for
small VDS, and increases along the channel for larger VDS. For VDS = VDsat = VG − VT, the
electric field becomes infinite at y = L. This is understandable because QI(L) = 0 at
pinch-off, and E must become very large to maintain a constant current ID. Eq. (5.20)
only holds in the triode region (VDS < VGS – VT). As VDS increases beyond VGS – VT,
Eq.(5.20) describes the variation only upto the pinch-off point (with L replaced by L′),
and beyond this is the depletion region with a voltage drop across it, as shown in

Fig. 5.5 (a) Plot of V along the channel as a function of y for increasing VDS in the triode region. For low
VDS, the variation is almost linear. (b) Plot of V as a function of y in saturation (VDS > VGS – VT).

5.2.2 The 3/2-power model

We do not need to use the assumption that the depletion width is constant along
the channel, as in Eq. (5.11). Rather, we can solve Eq.(5.10) directly. This gives the
following 3/2 power model for the drain current of the MOSFET [5.9]:

V ⎞
2 ⎠
[3 3 ⎫

ID = μnCox(W/L) ⎨⎜VGS − 2φ B − DS ⎟VDS − γ (VDS + 2φ B ) 2 − (2φ B ) 2 ⎬ (5.21)

This equation is again valid in the triode region and is more accurate than Eq.(5.13). It
has certain disadvantages however: the appearance of the 3/2 power terms which makes
further analytical calculations cumbersome, and the absence of the physically intuitive VT
term in the equation. Furthermore, this model is numerically expensive when used in
circuit simulation, because of the 3/2 power. It can be verified easily that for VDS small,
the second term within the braces of Eq.(5.21) becomes to γ(2φB)1/2VDS , so that Eq.(5.21)
reduces to Eq.(5.13),as expected.

5.2.3 The linearized depletion charge model

We can make a compromise between accuracy of Eq.(5.21) and the simplicity of

Eq.(5.13). The depletion charge QD along the channel varies with V as given by Eq.(5.4).
This is shown in Fig. 5.6. The constant depletion charge assumption used in section 5.2.1
is shown by the dashed line.

Fig. 5.6 Variation of − QD ( normalized to (2εsqNA)1/2) with channel potential V

A better assumption would be a linear approximation of QD(V):

– QD(V) = – QD(0) + KV . (5.22)

A possible choice of K would be the slope of Q(V) at V = 0. This slope is, from Eq.(5.4),

dQD ε qN
=− s A , (5.23)
dV 4φ B
so we can use

ε S qN A
− QD(V) = + 2ε s qN A 2φ B + V. (5.24)
4φ B

This approximation is shown in Fig.5.6 by the dotted line. Using Eq.(5.24) for QD(V),
Eq.(5.10) now becomes

γ (2φ B )1
( L) ∫ ⎡⎢{V ⎤

ID = μC OX W GS − V − 2φ B } − + δV ⎥dV , (5.25)
0 ⎣ C OX ⎦

ε s qN A
4φ B
where δ= . (5.26)
C ox

The integration of Eq.(5.26) proceeds very similarly to that of Eq.(5.12) to yield [5.10]:

⎧ 2 ⎫
ID = μC OX (W L )⎨(VGS − VT )VDS − (1 + δ )VDS
⎬. (5.27)
⎩ 2 ⎭

Eq.(5.27) is the compromise equation we are looking for, providing better accuracy than
the text-book model at very small additional complexity. We will sometimes call it the
“modified text-book” model.

We can attempt to get some physical insight into δ. The capacitance per cm2 of
the depletion region near the source end is given by CDO = εs/xdo where the depletion
width xdo = 2ε S (2φ B ) / qN A , or

ε s qN A
CDO = . (5.28)
4φ B

We can therefore write:

δ= (5.29)

The smaller the doping and CDO, the lesser is the depletion charge, and the closer is
Eq.(5.27) to Eq.(5.13). Note that δ can also be written as γ 2 2φ B . It is not surprising
that the body effect factor γ which describes how the depletion width varies with
(substrate) bias is connected with δ. Typical values of δ are 0.2 to 0.9.

It can be seen from Fig.5.6 that our choice of K is not the best. A better option is
to choose a straight line whose slope is somewhat less than the value at V = 0, say 0.5 to
0.8 times the slope at V = 0. This will result in a straight line (shown as dash-dot line in
Fig.5.6), which is a good linear fit over most of the range. In this case,

δ≈d (5.30)

where d is about 0.5 to 0.8.

Fig 5.7 shows the output characteristics for a MOSFET for two values of VGS
showing the difference between the various models. It can be seen that for low values of
VDS, there is hardly any difference in the characteristics. At larger VDS values, the text
book model always overestimates the current, since it assumes that QD is at its minimum
(source) value, thereby overestimating QI and hence ID.

Fig 5.7: Comparison of “text book” model with “modified text book” model for two gate voltages. The text
book model always overestimates the current.

In the modified text book model, pinch-off occurs at a value V Dsat which can be
found by evaluating the voltage VDS at which the ID reaches a maximum IDsat :

' VGS − VT
V Dsat = (5.31)
1+ δ

( L)(V2 (1−+Vδ ))
I Dsat = μC OX W GS T

' '
Both V Dsat and I Dsat are less than their text-book model counterparts. Qualitatively, we
would expect that pinch-off should occur at VGD = VT' where VT' is larger than VT (or
VTO) because of body effect. This implies that V Dsat should be less than VGS – VT, as
indicated in Eq.(5.31).

In the presence of body bias, Eq.(5.27) is changed in two aspects. Firstly, as in the
case of the text-book model, VT is replaced by VT' (Eq.5.17). Secondly the correct value
to use for δ is not given by Eq.(5.26) but rather by

ε s qN A
δ = C OX (5.33)
2(2φ B + VSB )

This follows because the correct equation for QD to use in the derivation for the slope is

QD = − 2ε S qN A (V ( y ) + VSB + 2φ B ). (5.34)

Note, however, that Eq.(5.29) is still correct, since in the presence of body bias CDO is
given by ε s qN A 2(2φ B + VSB ). .

The modified text-book model, representing as it does a good compromise between

accuracy and simplicity, is widely used. We will have occasion to encounter it again in
later chapters when we look at short channel effects, MOSFET modeling and SOI

The three simple models described in this section describe reasonably well the
characteristics of transistor under strong inversion conditions, that is, when the transistor
can be considered to be on. For VGS < VT , the text-book and other models cannot evaluate
currents correctly because diffusion becomes an important mechanism for current
transport. In the next two sections, we describe the calculation of the I-V characteristics
of the MOSFET taking both drift and diffusion currents into account.

5.3 The Pao-Sah Model

One of the earliest accurate models for the MOS transistor was that derived by
Pao and Sah [5.11, 5.12]. The Pao-Sah model includes drift and diffusion currents, and
also takes into account the variation of inversion charge with depth into the
semiconductor. It does, however, make the gradual channel approximation, so it is valid
only for long-channel devices.

Fig.5.8 shows the band-bending in the silicon under conditions of applied VGS and
VDS (but VSB = 0). We assume that (in the region of interest near the surface) the quasi-
fermi levels ε fn and ε fp are flat, implying negligible transverse current in the x direction.
The number of holes and electrons are determined by the locations of ε fp and ε fn , and
are given by :

p = ni exp(−βψ + βφfp) = p0 exp(−βψ) (5.35a)

n = ni exp(+βψ − βφfn) = n0 exp(+βψ − βV ) (5.35b)

Fig 5.8 Band diagram of MOS transistor showing band bending near the surface with VGS and VDS
applied. The quasi-fermi levels and potentials are measured with respect to the bulk intrinsic level.

In these equations, we have used β as a short form for (q k T ) and ψ(x,y) is the potential
at any point (x,y) measured with respect to the bulk intrinsic level. φfp and φfn are the
quasi-fermi potentials measured with respect to the bulk intrinsic level:

ε fp
φfp = φB = − (5.36a)
ε fn
φfp = φB + V(y) = − (5.36b)

Compare Eq.(5.35) with Eq.(2.23) for the MOS capacitor where V(y) is always 0, and the
semiconductor is in quasi-equilibrium.

The drift and diffusion electron currents are now given by

Jdr = qμn n E = − qμn n (5.37a)
Jdiff = q Dn . (5.37b)
Using Eq.(5.35b), the total electron current J becomes

J = Jdr + Jdiff

∂ψ ⎛ ∂ψ ∂φ fn ⎞
= − qμn n + q Dn β n ⎜⎜ − ⎟⎟
∂y ⎝ ∂y ∂y ⎠
∂φ fn ∂ε fn
= − qμn n = + μnn . (5.38)
∂y ∂y

As expected, the total current is proportional to the gradient of the quasi-fermi level.

The drain current ID can be obtained by integrating over x and in the direction of
the width of the transistor, giving

xI xI
∂φ fn
ID = W ∫ Jdx = W ∫ − qμ n n( x, y ) dx, (5.39)
0 0

where xI is the inversion layer “thickness”, and n(x,y) is given by Eq.(5.35b). We

integrate once more with respect to y to get

L L xI
∂φ fn
∫ I D dy = W ∫ ∫ − qμ n n( x, y)
0 0 0
dxdy. (5.40)

Using Eq.(5.36b) and the fact that at y = 0, V = 0 and at y = L, V = VDS, we can transform
the RHS of Eq. (5.40) into an integral in V :

( L) ∫ ∫ n( x, y)dxdV

ID = − qμn W . (5.41)
0 0

The expression for n(x,y) as given in Eq.(5.35b) is through ψ(x,y). This can be taken care
of by converting the integral from x to ψ. For this we need dψ/dx. We refer to Eq.(2.26)
for the MOS capacitor derived by integrating the exact Poisson equation once. This
equation cannot be used here directly, because the silicon in the MOS capacitor was in
(quasi-) equilibrium, unlike the MOS transistor. We need to now integrate a modified
Poisson expressions for n and p, as given by Eqs.(5.35) and (5.36) :

d 2ψ ρ ( x)
= .
dx 2 εs

where ρ (x) = q [N D+ − N A− + p 0 e − βψ − no e βψ − βV ] . (5.42)

The solution of Eq.(5.42) can be obtained, and is similar to Eq. (2.27) :

dψ kT ⎛ n ⎞
= 2 F ⎜⎜ βψ , V , o ⎟⎟ (5.43)
dx qLD ⎝ po ⎠

In the above equation the F function is similar to Eq. (2.28), and is given by

⎧ ⎫
( ) ( )
n n
F(βψ, V, o ) = ⎨ e − βψ + βψ − 1 + o e − βV e βψ − βψ e + βV − 1 ⎬ . (5.44)
po ⎩ po ⎭

xi φB
We can now replace ∫ ndx
by ∫ n dψ
(dψ / dx) , where we define the extent of the

inversion layer xI to be the point where p = ni. (We could have used the point xI’ where n
= ni, but in that case the upper limit would be φ B + V , which complicates the integration.
In any case, there are so few electrons between xI′ and xI, that the two results would be
almost the same. On the other hand, it would not be correct to extend the upper limit to
infinity.) Eq.(5.41) now becomes

exp(βψ − β V )
W μn
ID =
L 2
qno β LD ∫ φ∫ ⎛ n ⎞
dψ dV . (5.45)
0 b
F ⎜⎜ βψ , V , o ⎟⎟
⎝ po ⎠

In the above equation, the surface potential ψs is related to the applied gate voltage VGS
through an equation similar to Eq.(2.41) :

kT ε s ⎛ n ⎞
VGS = ψ S + VFB + 2 F ⎜⎜ βψ S , V , o ⎟⎟ . (5.46)
qLD C ox ⎝ po ⎠

The Pao-Sah double integral of Eq.(5.45) can be evaluated, together with Eq.(5.46), to
give ID as a function of VGS and VDS. This equation is valid for all regimes of operation –
triode, saturation as well as the subthreshold region (VGS < VT).

The result of the integration is shown in Figs.5.9a and 5.9b. Fig. 5.9a shows the
output characteristics for a few values of VGS. It can be seen that the ID values naturally
saturate, without having to artificially invoke constancy in ID. Fig 5.9b shows the
transfer characteristic (ID versus VGS) for VDS = 0.1 V, plotted on a log ID scale. This
curve emphasizes the subthreshold behavior of the drain current. Below the threshold
voltage (about 0.7 V in this case), the current falls off almost exponentially, as the
channel goes from strong inversion to weak inversion, and the number of electrons in the
inversion layer falls off rapidly with decreasing VGS. We will examine the subthreshold
behavior in more detail in Section 5.5.



Fig 5.9. (a) Drain characteristics of an ideal nMOSFET for various gate voltages. (b) Subthreshold
characteristics of an ideal nMOSFET for VDS = 0.1 V

5.4 Brews’ Charge Sheet Model

The charge sheet model for the long-channel transistor developed by Brews [5.13,
5.14] also considers both drift and diffusion components of the current. However, unlike
the Pao-Sah model, Brews considers the inversion charge as a sheet of charge of areal
density QI per cm2, that is, no drop occurs across the inversion layer. This eliminates one
of the integrals of the Pao-Sah model. Suitable approximations allow an evaluation of
the second integral, with the result that the Brews’ model provides an analytical
expression for ID spanning all regimes of operation of the MOSFET, which does not need
numerical integration. The surface potential ψs plays an important role in Brews’ model,
and it is one of the earliest of the surface potential based MOsFET models, which are
becoming increasingly important [5.15].

The starting point for the derivation of the Brews equation is Eq.(5.38) :

∂φ fn
J = − q μn n .
Integrating this along the width, and along x, we can write

∂φ fn
ID = + Wμn QI , (5.47)

where we have assumed that ∂φfn/∂y is not a function of x over the small distance
corresponding to the inversion layer. This “charge sheet” approximation allows us to
replace ∫ q n(x,y) dx by QI(y). The expression for QI(y) which we use is essentially
Eq.(5.5) :

QI(y) = − Cox(VGS − ψs) + qNA LD 2 (βψS)1/2 , (5.48)

where the second term is just the depletion layer charge, and we are assuming that VSB =
0 V.

5.4.1 Calculation of ∂φfn/∂y

Our calculation of ∂φfn/∂y to insert into Eq. (5.47) proceeds as follows. The total
semiconductor charge Qs which is – Cox(VGS − ψs), can be written using Gauss’ law on
Eq. (5.43):

∂ψ kT ⎛ n ⎞
Qs = εs = − 2 ε s F ⎜⎜ βψ s , V , o ⎟⎟ . (5.49)
∂x x =0 qLD ⎝ po ⎠

Using CFBs = ε s LD as in Eq. (2.49), V = φ Fn − φ B , (no po ) = (ni N A ) , and retaining


only the dominant terms in F, we get

⎧⎪ ⎛ ni ⎞
⎫⎪ 2

⎟⎟ exp(βψ s ) exp(− βφ fn + βφ B )⎬
Qs = − 2 C FBs ⎨βψ s + ⎜⎜
q ⎪⎩ ⎝ NA ⎠ ⎪⎭

= − Cox (VGS − ψs) . (5.50)

Note that in the above equation ψs and φfn and hence Qs are functions of y. Squaring
Eq.(5.50) gives

⎧ ⎫
⎪⎪ C (V − ψ ) ⎪⎪ ⎛ ni ⎞

⎨ ⎬ = βψs + ⎜⎜ ⎟⎟ exp(βψs) exp(− βφfn + βφB) .

⎪ 2 kT C FBs ⎪ ⎝ A⎠
⎪⎩ q ⎪⎭

Defining a = 2 C FBs C OX (typical values of a lie between 0.2 to 5), we can rearrange
Eq.(5.51) to get βφfn :

⎧⎪ (βVGS − βψ S )2 / a 2 − βψ s ⎫⎪
βφfn = βφB − ln ⎨ ⎬ . (5.52)
⎪⎩ (ni / N A )2 exp(βψ s ) ⎪⎭

This equation describes how φfn varies with ψs for different VGS values. Plots of φfn are
given in Fig.5.10. For small values of βψs, the numerator of the ln term is almost
(βVGS/a)2, and

⎧ β VGS ⎫
βφfn ≈ βφB – 2 ln ⎨ ⎬ + βψs , (5.53)
⎩ i
a (n / N )
A ⎭

so φfn varies linearly with ψs with unity slope. This happens as long as the channel is in
strong inversion. The electron quasi-fermi level εfn is almost pinned to a value εg/2 − φB
below the conduction band (see Fig.5.11a), and as ψs changes along the channel, so does
φfn by the same amount.

Fig 5.10 Variation of βφFn with βψS for various gate voltages

However, at some point ψs becomes large enough, that all the charge required in
the semiconductor at a particular VGS is supplied by the depletion region, and no inversion
charge is required. Then εfn is no longer tightly coupled to εc. The surface potential ψs
can now no longer increase, but as the quasi-fermi level falls away from εc, εfn continues
to increase (Fig.5.11 b).

The value at which ψs saturates will be called ψsat. From Eq. (5.52), ψsat occurs
when the numerator of the log term goes to 0, that is,

(βVGS − βψsat)2 = a2βψsat . (5.54)

Note that a, γ and δ are related to each other through

(a) (b)

Fig 5.11 (a) Electron quasi-fermi level εfn varies with band bending under strong inversion, (b) Electron
quasi-fermi level εfn moves away from the conduction band after band bending saturates to ψsat.

a =γ β = 8φ B β δ .

The solution of Eq. (5.54) is

a2 a2
βψsat = βVGS + − a βVGS + (5.55)
2 4

In the above equation, if VFB is to be included, VGS would be replaced by VGS − VFB. The
value of the maximum surface potential ψsat for a particular value of VGS signals the onset
of the pinch-off condition at the surface. It can be easily verified that the Eq. (5.54)
corresponds to QI = 0, or

2ε S
Cox(VG − ψs) = + q NA xd = − QD = + q NA ψS (5.56)
qN A

Equation (5.52) can now be differentiated with respect to y to give (remember that ψs is a
function of y):

∂ (βφ fn ) ⎧⎪ 2(βVG − βψ S ) / a 2 + 1 ⎫⎪ ∂ (βψ s )

= ⎨1 + ⎬ . (5.57)
∂y ⎪⎩ (β VG − βψ S )2 / a 2 − βψ s ⎪⎭ ∂y

5.4.2 Calculation of the current ID

Using Eqs.(5.47) and (5.48), we get

1 ∂ (βφ Fn )
ID = − W μn Cox {βVGS − βψs − a(βψs)1/2}. . (5.58)
β 2

Using Eq.(5.57) for ∂(βφfn)/ ∂y in the above equation, we can write

⎧ ⎡ ⎤⎫
− Wμ n c ox ⎪⎡ ⎤ β − βψ + ⎥ ⎪. ∂ ( βψ s ) (5.59)
1 2
⎢ 2( V ) a
⎨⎢ β VGS − βψ S − a( βψ s ) 2 ⎥ + ⎢ 1 ⎥⎬
ID =
β 2
⎪⎣ ⎦ ⎢ β V − βψ + a( βψ ) 2 ⎥ ⎪ ∂y
⎩ ⎣ GS S s ⎦⎭

It is not possible to integrate Eq. (5.59) analytically. We make the following very
reasonable approximation to render it integrable. Call the first term in square brackets A,
and the second B. The value of A is essentially QIβ/Cox, and therefore for large VGS much
greater than B whose value is approximately 2. The term B is important only when QI is
small, that is when we do not have strong inversion – in the pinched-off region, or as we
shall see soon, in the subthreshold regime. Under this condition, ψs ≈ ψsat, and B can be
approximated, using Eq.(5.54), as

2a (βψ s ) + a2
1/ 2
B≈ = 1+ . (5.60)
2a (βψ s ) 2(βψ s )
1/ 2 1/ 2

Integrating Eq.(5.59) and using Eq. (5.60), we get

ψ SL
Wμ n C ox ⎧ ⎫
− βψ S − a(βψ s ) ⎬d (βψ s ) . (5.61)
∫I dy = − ∫ ⎨β V +1+
1/ 2

β 2( βψ s )
D 2 GS 1/ 2
0 ψ ⎩
S0 ⎭

Eq.(5.61) can be integrated analytically. Before we complete the integration, however,

we need to find ψso and ψsL, the values of ψs at y = 0 (the source end) and at y = L (the
drain end). We could have ignored the fact that the band bending at the source end ψso is
a mild function of VGS even in strong inversion, and this would have allowed us to set ψso
equal to 2φB. However, the value of ψsL is difficult to get in this way because it initially
increases with VDS as approximately 2φB + VDS, but eventually saturates to ψsat. The
correct approach to find both ψso and ψsL is to first use the known values of φfn at the
source and drain ends :

At y = 0 (source): φfn = φB
At y = L (drain): φfn = φB + VDS, (5.62)

and then, knowing φfn , we can solve the transcendental equation (5.52) to find ψso and
ψsL. The fact that ψs naturally saturates with increasing φfn (and VDS) as seen in Fig. 5.10,
produces a natural saturation in drain current.

The integration of Eq.(5.61) now gives the drain current of the Brews model :

I D = − (W / L )μ n C OX
1 ⎧
2 ⎨
β ⎩
(1 + βVGS )(βψ sL − βψ so ) − 1 (βψ sL )2 − (βψ so )2
[ ] [ ]

a (βψ sL ) 2 − (βψ so ) 2 + a (βψ sL ) 2 − (βψ so ) 2
2 3 3 1 1

3 ⎭

This single equation accurately describes the drain current of a MOSFET in all
regimes, for any applied voltage VGS and VDS (the latter appearing through ψsL). No
numerical integration is required, though it is necessary to solve the transcendental
equation to obtain ψso and ψsL. The Brews’ model does not need to artificially invoke the
saturation phenomenon; as explained above, the drain current reaches saturation in a
natural manner for large VDS.

5.4.3 The Brews Equation for VSB ≠ 0

So far we have assumed that VSB = 0 in the derivation of the Brews equation. This
can be easily modified if VSB ≠ 0. Firstly in Eq. (5.48), we should be using VGB instead of
VGS. Since VGB = VGS + VSB, we need to replace VGS by VGS + VSB. Secondly, in
computation for ψso and ψsL, we need to recognize that φfn at the source and drain ends
will have the term VSB added on in Eq.(5.62). Also, if VFB ≠ 0, replace VGS by VGS – VFB
everywhere. This then gives the most general equation for ID as a function of VDS, VGS
and VSB for a non-ideal long-channel MOSFET.

5.4.4 Separation of Drift and Diffusion Currents

To get an idea of the relative importance of the drift and diffusion currents in
various regimes of operation, we can easily separate out the two components in the
Brews equation. The drift current, from Eq. (5.37a) is the term containing just ∂ψ/∂y.
Comparing with Eqs.(5.57) and (5.59), it is clear that the term A in Eq.(5.59) is the drift
term, and therefore the term B corresponds to the diffusion term. It can also be argued,
less rigorously, that drift will be important when QI and hence A are large, that is, the
channel is strongly inverted. Diffusion is important when QI is not large (but ∂QI / ∂y may
be large), and this happens when term B dominates.

Accordingly, we can separate out the drift and diffusion currents as follows :

I D ,drift = − (W / L )μ n C ox
1 ⎧
2 ⎨
β ⎩
β VGS (ψ sL − βψ SO ) − (βψ sL )2 − (βψ SO )2 ]
[ ]

− a (βψ sL ) 2 − (βψ so ) 2 ⎬
2 3 3

3 ⎭

ID,diff = − (W / L )μ n C ox
{(βψ SL [
− βψ SO ) + a (βψ SL )
1/ 2
− (βψ SO )
1/ 2
] }. (5.65)

The drift and diffusion components, as well as the total current ID are plotted in Fig.5.12.
This clearly shows that sufficiently below VT (that is in the subthreshold region) diffusion
is the dominant current, whereas in the triode region where strong inversion exists, drift is
the dominant component. Near threshold, both drift and diffusion contribute, and this
region (called moderate inversion) is the most difficult to model accurately.

Fig. 5.12 Drift and diffusion components of drain current. Note that diffusion current dominates in
subthreshold, and drift current dominates in the on condition.

In the subthreshold regime, the surface is in weak inversion (and at sufficiently

low VGS in depletion), and the surface potential is therefore ψsat everywhere along the
channel. This implies that there is no field along the channel (∂ψs/∂y = 0), and therefore
there cannot be any drift current.

5.5 The Subthreshold Regime

The subthreshold regime is an important regime of operation for the MOSFET. In

digital CMOS circuits, the transistor is turned off by applying VGS = 0. The current
flowing in the transistor in the off condition is usually the subthreshold current. It is
important to calculate the subthreshold current accurately since it represents the leakage
current flowing in the transistor, which directly contributes to static power disipiation and
static current drain in CMOS circuits.

5.5.1 Subthreshold current

The subthreshold current can be described by Eq. (5.65), since diffusion current is
dominant in subthreshold. A first glance at Eq. (5.65), together with the understanding
that ψs is almost constant along the channel at a value ψsat seems to indicate that ID ≈ 0.
However, though ψso ≈ ψsL ≈ ψsat, actually ψso and ψsL are slightly different. These can
be calculated form Eq.(5.52) rewritten as the following equations :

⎛ n ⎞
(βVGS − βψso) = a βψso + ⎜⎜ i ⎟⎟ exp(βψso)
2 2
⎝ NA ⎠
⎛ n ⎞
(βVGS − βψsL) = a βψsL + ⎜⎜ i ⎟⎟ exp( βψ SL ) exp(− βVDS ) .
2 2
⎝ NA ⎠

Taking square roots on both sides, and noting that the second term on the RHS is small
because the surface is not in strong inversion, we get after some algebra:

⎛ ni ⎞ exp( βψ s )
ID = − (W / L ) μn
C FBs ⎜⎜ ⎟⎟ ( )
1 − e − βVDS . (5.67)
β2 ⎝ N A ⎠ (2 βψ s )
1/ 2

This equation for the subthreshold current can also be derived more directly, retaining
physical insight, as follows.

The charge QI(y) can be written from Eqs.(5.48) and (5.50) as

⎡⎧ 2
1/ 2

⎪ ⎛ n ⎞
QI(y) = − ⎢
2qN A LD ⎨βψ S + ⎜⎜ i
⎟ exp(βψ s ) exp(− βφ fn + βφ B )⎬ − ( βψ s ) 1/ 2 ⎥
⎢⎪ ⎝ N A ⎟⎠ ⎪ ⎥
⎣⎩ ⎭ ⎦

Since the surface is in weak inversion, the second term in braces is much smaller that the
first, so we can approximate

exp(βψ s )
⎛ n ⎞
QI(y) ≈ − q NA LD ⎜⎜ i ⎟⎟ exp(− βφ fn + βφ B ) . (5.69)
⎝ NA ⎠ (2βψ s )1 / 2
Since ψs ≈ ψsat everywhere, only diffusion current flows, and this is

Q I ( L) − Q I ( D ) ∂QI
ID = Dn W = DnW . (5.70)
L ∂y

Note that since the current is constant along the channel, the gradient of QI(y) is constant.
Using Eq.(5.69) in (5.70), and φfn = φB + V + VSB, we get for the drain current in

⎛ W ⎞ ⎛ kT ⎞ ⎛ n ⎞ exp( βψ sat )
ID = − ⎜ ⎟ μ n ⎜⎜ ⎟⎟qN A LD ⎜⎜ i ⎟⎟ exp(− βVSB ) [1 − exp(− βV DS )] . (5.71)
⎝L⎠ ⎝ q ⎠ ⎝ NA ⎠ (2βψ sat )1 / 2
Eq. (5.71) is the same as Eq.(5.67), except that we have now also included the non-zero
VSB. In Eq.(5.71), βψsat is given by Eq.(5.54), suitably modified to include VSB, the
solution of which is

a2 a2
βψsat = βVGS + βVSB + − a(βVGS +βVSB+ )1/2 , (5.72)
2 4

and therefore ID has a strong VGS dependence through this term.

The conduction mechanism for the MOSFET in subthreshold is very similar to

that of the bipolar transistor. The source acts as the emitter, and the drain as the collector.
The gate voltage VGS reduces the n+p (source-channel) junction barrier to induce injection
from the source into the channel. The electrons flow by diffusion along the channel to the
drain, since the small difference in ψs between source and drain can produce a large
gradient in the number of carriers, though it produces almost no electric field along the
channel. The surface potential ψs is shown as a function of y in Fig. 5.13a. We can
sharpen some of our ideas of the MOSFET from Fig.5.13a. Firstly, the Brews model
considers the region from y = 0 to L, and cannot describe change in the potential going
across the junction from ψBI ( = (kT/q) ln(NDNA/ni2)) to ψso. Secondly, we can use this
picture to plot also ψs(y) for the case of triode and saturation regimes. These are shown in
tFigs. 5.13b and 5.13c respectively. In the triode region, the surface potential varies from
ψso to ψsL along the channel as shown. Accordingly to Eq.(5.20) of the text-book model,
V(y) varies from 0 at the source end to VDS at the drain end, and therefore ψs should vary
from 2φB at the source to 2φB + VDS at the drain. This is not quite correct, because we had
earlier neglected the unequal band-bending at the two ends. In saturation, the value of ψsL
reaches ψsat. Increasing VDS further has no effect on ψsL, thereby causing a saturation of

Fig. 5.13 Plot of surface potential versus y in (a) subthreshold, (b) triode and (c) saturation regimes. (d)
shows the band diagram along the surface of the MOSFET derived from (b).

current. The plots of Fig. 5.13 a-c can be turned around to produce the band diagram
along the surface for the MOSFET, as shown in Fig.5.13d.

Reverting our attention to the subthreshold region, we note that changing VDS has
negligible effect on ID as long as VDS is greater than a few (kT/q). This is clear from
Eq.(5.71) and also from the picture of the MOSFET as a bipolar transistor where
changing the reverse-biased base-collector voltage has no effect on the transistor current.

The drain current in subthreshold is a strong function of VGS, and, to a lesser

extent, VSB. Note that the exp(−βVSB) term Eq.(5.71) really does not come into the
picture since it cancels out the βVSB term in exp(βψsat).

To a first approximation, ID goes as about exp(βVGS), and exp(−βVSB/2) for large

VSB. This implies that the plot of log ID versus VGS will yield almost a straight line in
suthreshold. Accurately calculated plots for different VDS and VBS values, calculated from
the Brews equation are shown in Fig. 5.14.

Fig. 5.14 Transfer characteristics for two different values of VDS and VSB.

It is convenient to have an equation for the subthreshold current ID explicitly in

terms of (VGS - VT), especially for compact models in circuit simulation [5.16]. In weak
inversion, Eq.(5.56), including VSB and VFB, is

Cox(VGS − VFB + VSB −ψsat) = − QD(ψsat) (5.73)

ψsat is a value somewhat less than the strong inversion value 2φB + VSB. Expand QD(ψsat)
in a Taylor’s series expansion around 2φB + VSB :

∂Q D
− QD(ψsat) = − QD(2φB + VSB) − (ψsat − 2φB − VSB) (5.74)
∂ψ sat
Using − = CD, the depletion capacitance of the semiconductor in weak inversion
∂ψ sat
(at ψs = ψsat),

CD = , (5.75)
2ε S
(ψ sat + VSB )
qN A
we get
Q D (2φ B + VSB ) C D
VGS − VFB + VSB − ψ sat = − + (ψ sat − 2φ B − VSB ) . (5.76)
C ox C ox

− Q D (2φ B + VSB )
Using VT' = VFB + 2φB + , the threshold voltage including body effect,
C ox
we get
VGS − VT' = ( 1 + ) (ψsat – 2 φB – VSB), (5.77)
C ox

or ψsat =
(V − VT'
GS ) + 2φ B + VSB . (5.78)
1+ D
C ox

Substituting Eq.(5.78) into Eq.(5.71), we get after some rearrangement :

⎡ β (VGS − VT' )⎤
( )
⎛ kT ⎞ ⎛ CD ⎞
ID = - W μ C OX ⎜⎜ ⎟⎟ ⎜⎜ ⎟⎟ exp ⎢ ⎥[1 − exp(− βVDS )] .(5.79)
L η
⎝ q ⎠ ⎝ C ox ⎠ ⎣ ⎦

Note that the VSB term in Eq.(5.78) has cancelled the exp(−βVSB) term in Eq.(5.71), so
that VSB appears in the subthreshold ID mainly through VT' . In the above equation, we
have used
⎛ C ⎞
η = ⎜⎜1 + D ⎟⎟ ≈ 1 + δ (5.80)
⎝ C ox ⎠

from Eq.(5.29). Note that earlier in Section 5.2.3, we had got
⎛ 2ε S ⎞
C DO = ⎜⎜ ε s 2φ B ⎟⎟ because we had ignored body bias then. If we had included body
⎝ qN A ⎠
2ε S
bias then, we would have got CDO = ε s (2φ B + VSB ) , which is close to but not
qN A
identical with eq. (5.75). The factor η is close to (1+δ) near threshold, but increases
slightly (as CD increases) as VGS falls away from VT. This point also tells us that VGS also
enters Eq.(5.79) through CD and η which are both mild functions of VGS.

Eq.(5.79) is a convenient equation for the subthreshold current since it relates ID

to exp(VGS − VT' ), and emphasizes the fact that the major (though not the only one –
remember η) effect of changing VSB is to change VT, which results in almost parallel
shifts in the ID-VGS curves as shown in Fig. 5.14.

5.5.2 Subthreshold Swing

An important parameter defining the subthreshold characteristics in the

subthreshold swing S, defined as :

S= . (5.81)
d log I D

It can be found, after some lengthy algebra, by differentiating Eq.(5.71) and using (5.72)
to be

⎡ CD ⎤
⎢1 + ⎥
(ln 10) ⎣ C ox ⎦ , (5.82)
q ⎡ ⎛ 2 ⎞⎛⎜ C D ⎞

⎢1 − ⎜ 2 ⎟⎜ ⎟⎟ ⎥
⎢⎣ ⎝ a ⎠⎝ C ox ⎠ ⎥⎦

where CD is given by Eq.(5.75), and is a function of VGS (through ψsat) and VSB. For
typical values, second term in the denominator is small compared to 1 and S can therefore
be approximated as:

kT C kT
S ≈ (ln 10) (1 + D ) = (ln 10) η . (5.83)
q C OX q

Since CD and η are (mild) functions of VGS, S is not quite constant in subthreshold, that is,
the plot of log ID versus VGS is not quite a straight line in the subthreshold region. The
swing S increases slightly at values of VGS further away from VT, that is, at lower values
of ID. A plot of S and ID versus ψsat are shown in Fig. 5.15.

Fig 5.15 Plot of S and Id with respect to ψsat.

Fig 5.16 shows variation of S with a for two different values of ID [5.14]. This shows that
lower values of a are desirable for getting lower subthreshold swings.

Fig 5.16: Variation of S with a for two values of Id

The importance of the subthreshold swing S arises from the fact that it determines how
‘rapidly’ the transistor can be turned off. It also determines the leakage current at VGS =
0. S is usually measured in units of mV/decade, signifying the number of mV by which
VGS must reduce in order to reduce ID by one decade. It can be seen that if the threshold
voltage is 0.6V, the swing is a near-ideal 60 mV/decade, and the current at threshold is 10
μA, the current at VGS = 0 will be 10 orders lower or 0.1fA, which is very good (in fact it
will be larger that this, dominated by reverse leakage of the body-drain p-n junction).
However, if the value of S is a worse-than-ideal value of 150 mV/decade, the leakage
current at VGS = 0 V will be as high as 1 nA. Also, the importance of having an
appropriate value of VT can be understood now. Too small a VT means that the OFF
leakage current will be too high, whereas too large a value of VT means that the ON drive
current, which is proportional to (VGS – VT)2 in saturation, will be too low.

We see from Eq. (5.83) that the best subthreshold swing which can be achieved is
obtained when CD << Cox, and the value is Sideal = (kT/q) ln10, or about 59 mV/decade.
The only way to improve this is to reduce the temperature.

A simple model for subthreshold swing can be obtained by invoking the

equivalent circuit picture of Fig. 5.17, and the approximate form of Eq. (5.71):

βψ s
log ( I D ) = . (5.84)

Fig. 5.17 Equivalent circuit of the MOS transistor. The arrow points to the silicon-oxide interface.

The subthreshold swing S is d(VGS)/d(log ID), which can be written as:

1 1
S = = . (5.85)
∂ (log I D ) / ∂VGS [∂(log I D ) / ∂ψ s ][∂ψ s / ∂VGS ]
Using Eq. (5.84) and Fig. 5.17, we can write

ln(10) ⎛ kT ⎞
S = = ⎜⎜ ⎟⎟ ln(10) η , (5.86)
β ⎛⎜ C ox (C + C ) ⎞⎟ ⎝ q ⎠
⎝ D ox ⎠

which is the same as Eq. (5.83). The physical interpretation simply is that the surface
potential is produced by voltage division of VGS, and this voltage division term
determines the subthreshold swing. This simple model allows us to see easily what
would happen to S in the presence of interface states. As shown in Chapter 3, the effect
of interface states can be represented in the equivalent circuit by a capacitance Cit (= qDit)
appearing in parallel with CD. As a consequence, the subthreshold swing of a MOSFET
in the presence of interface states becomes

ln(10) ⎛ kT ⎞ ⎡ C C ⎤
S = = ⎜⎜ ⎟⎟ ln(10) ⎢1 + D + it ⎥ . (5.87)
β ⎛⎜ C ox (C + C + C ) ⎞⎟ ⎝ q ⎠ ⎣ C ox C ox ⎦
⎝ D it ox ⎠

It can be seen that the presence of interface states degrades (increases) the value of
subthreshold swing.

Sometimes, the quantity S is referred to as the subthreshold slope. However,

since the slope of the log (ID) versus VGS plot would really be d(log ID)/d(VGS), with units
of (mV)−1, it is more correct to refer to S as the subthreshold swing, as we have been

5.6 Effect of Series Source and Drain Resistance

There are some parasitic effects which come into play even for long-channel
transistors. One of these is the parasitic series source and drain resistance. These
parasitic resistances are the resistances of the n+ source and drain regions, and appear in
series with the resistance of the channel. Their values cannot be ignored if the channel
resistance becomes small, for example if the gate voltage is large or the oxide thickness is
small. The MOSFET with parasitic source and drain resistances Rd and Rs is shown in
Fig. 5.18. Labeling the intrinsic MOSFET voltages as VDS and VGS, and the terminal
MOSFET voltages in the presence of the series resistances as VDSt and VDSt , we can write

VDSt = VDS + ID (Rd + Rs) (5.88)

VGSt = VGS + ID ( Rs) . (5.89)

These two equations combined with any of the intrinsic transistor equations (for example,
the modified text-book model of Eq. (5.27)) describes the overall behavior of the
MOSFET. The MOSFET equation can now be obtained by replacing VDS and VGS in
Eq. (5.27) by Eqs. (5.88) and (5.89) to get ID = f(VDSt, VGSt). The resulting equations,
though straightforward are rather complex, and left to the reader to derive. Qualitatively,

it is easy to see that, because of the additional resistance, the drain current will always be
less than in the case of the intrinsic transistor.

Fig. 5.18 The MOSFET with series source and drain resistances. The voltages VDS and VGS denote the
t t
intrinsic transistor voltages, and VDS and VDS denote the terminal voltages.

A specially significant effect of series resistance is when we are looking at the

transfer characteristic (ID versus VGS) for small VDS. In this case, the relevant intrinsic
transistor equation is

ID = μ n C ox
(VGS − VT ) VDS . (5.90)

Using the above, together with Eqs. (5.88) and (5.89) and assuming that Rd = Rs = R,
we get

μ n C ox
t t
ID = . (5.91)
⎧ W
( ( ⎫
⎨1 + μ n C ox R VDS + 2 VGS − VT ⎬
t t
⎩ L ⎭

It can be seen that the ID versus VGSt relationship is no longer linear, as in the case of the
intrinsic transistor, but rather falls off, and increases only sub-linearly. In particular, for
large values of VGSt , the drain current saturates to the value

ID = , (5.92)
{2 R}
consistent with the physical understanding that the series resistance determines the
current rather than the intrinsic channel resistance. This is shown in Fig. 5.19.

Fig. 5.19 The transfer characteristic for the intrinsic transistor, and in the presence of series resistance.

5.7 Drain Breakdown

At sufficiently large drain voltages, breakdown occurs, and the drain current ID
increases substantially. The physical origin of this breakdown is simply impact
ionization and avalanching in the drain depletion region. As in the case of avalanche
breakdown of an n+p junction, the breakdown voltage depends inversely on the doping of
the substrate, going approximately as ( N a 3 ) . Accurate calculation of the breakdown
voltage is difficult because of the two-dimensional fields in the neighborhood of the
drain/surface region where avalanching takes place, and numerical simulation must be
resorted to.

If we approximate the situation to a pure one-dimensional case, then we see from

Fig. 5.4 that the voltage drop across the depletion region near the interface is about (VDS −
VDsat) or about (VDS − VGS + VT). If at breakdown, the voltage across the depletion region
is Vbr, then, as VGS increases, VDS required to cause breakdown also increases by the same
amount. As a consequence, the output drain characteristics of a MOSFET are expected to
look as shown in Fig. 5.20, with the breakdown curves crossing each other. This was
seen in the early metal-gate long-channel transistors, but are not seen in short-channel
modern transistors where 2-D effects cannot be ignored.

Fig. 5.20 Avalanche breakdown characteristics under 1-D approximation.


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5.2 O. Heil, British Patent 493,457 (1935).
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5.10 See, for example, Y. Tsividis, Operation and Modeling of the MOS Transistor (2nd
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5.11 H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal-
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oxide(insulator)-semiconductor transistors,” Solid-St. Electron. 9, 927 (1966).
5.13 J. R. Brews, “A charge sheet model of the MOSFET,” Solid-St. Electron. 21, 345
5.14 J. R. Brews, “Physics of the MOS transistor,” in Applied Solid State Science, Suppl.
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5.15 G. Gildenblat et al., “PSP: An advanced surface-potential based MOSFET model
for circuit simulation,” IEEE Trans. Electron Devices 53, 1979 (2006).
5.16 N. D. Arora, MOSFET Models for VLSI Circuit Simulation, Springer-Verlag, Wien