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36.2.1
0-7803-1450-6 $3.00 0 1993 IEEE IEDM 93-883
in surface channel pMOSFETs, compared with buried (AR/R=AgJgJ for the same absolute degradation AR.
channel ones. Electron trapping also occurs, as indicated Fig.10 shows ISJD as a function of VD-VmAT for long
by the slight positive AVm at lower lVol stress. However, and short devices, where VmATis the potential of the
it seems to be less significant in determining the device pinch-off point. V, can be determined from the
lifetime. I d D data itself, as was first pointed out in [5]. TO
The results of PMOS lifetime extrapolation m obtain more well-defined results, particularly for short
shown in Fig.6. Bias conditions similar to the nMOS case channel devices, VmAT was extracted from Isv$ID VS VD
(Vo=VJ2 and V,=V,J were chosen. The lifetime was curves, instead of I, vs V, ones. The horizontal shift of
defined by AVm=20mV, since AVm was severer than Agm. a curve from the one for Vo=Vm was taken as equal to
The estimated allowable V, (2.5V) is much larger than VNAT, assuming V , a for V,=V,. Here, V, for
that for the nMOS. vD=O.lv was used. Following this VmAT determination
procedure, I d D VS VD-VNAT curves almost
Switching speed independent from LBpp.
Thus, if the voltage applied to the pinch-off region
Applying the 1.9V supply voltage, a reasonably short (=VD-VNAT) is fixed, the electron energy distributions near
ring oscillator delay zpdof 33ps (Fig.7) was obtained for the drain is considered to be independent from the
FO=1, &=0.15pm, while suppressing the standby-current channel length even down to 0 . 1 ~ No . singular I-
to about lOpA/pm (IVmI=0.4V). dependence is detected. However, the results do not mean
According to SPICE simulations, junction capacitance the absence of non-stationary carrier transport. Rather, it
C,, overlap capacitance Cov, and source/drain resistance is believed to have occurred, but equally in all the
RSD are the key parasitic factors that determine the samples, resulting in the failure of its detection. To
inverter delay. By means of the area-restricted channel experimentally catch it, samples with different pinch-off
implant technique. C, is adjusted to be equivalent to region length must be compared.
0 . 1 5 design,
~ while using 0 . 6 design
~ rules. Further
reduction of C, is possible by cutting down the alignment Conclusion
tolerance ( 0 . 3 ~ ) Though
. Cov is controlled by the SiO,
blanket, there still remains room for suppressing the Hot carrier reliability of 0 . 1 5 nMOS
~ and PMOS
PMOS overlap ( L 0 - u 0 . 0 6 p ) . By reducing both C, and was evaluated. The allowable V, was as high as 1.9V.
CO,, 2, about 2Ops should be possible. Parasitic The degradation of PMOS, though much different from
resistance becomes a serious problem. In spite of the TiSi, conventional devices, was less severe than nMOS.
salicidation, high source/drain doping, and large contact Applying the 1.9V, a ring oscillator delay T,, of 33ps
holes, RsD caused, through the reduction of the drive was obtained, maintaining sufficiently high V,. The
current, more than 10%increase in zpp The effect of gate results demonstrate that 0 . 1 5 CMOS
~ with both high
sheet resistance was not serious in this work, since the speed and reliability is feasible.
channel width used was small (W4p.m. W p 8 p ) . No singular channel length dependence was found,
either in hot carrier degradation or impact ionization,
Closer look at nMOS hot carrier effects down to 0 . 1 ~ To . experimentally detect non-stationary
carrier transport, the length of pinch-off region, rather
In Fig.8, the allowable V, is compared with that for than channel length, should be varied as a parameter.
0 . 4 generation
~ devices. The 1.9V V, for the 0 . 1 5 ~
devices is much higher than expected from the constant Acknowledgement
field scaling ( V e L , ) , and even higher than the square-
root scaling level (V,=LovL) [3]. This can be a result of The authors would like to thank N.Ehdo for his
non-stationary carrier transport, which is expected to occur continuous encouragement, and I.Sakai, H.Abiko,
when the channel length approaches 0 . 1 ~ Therefore,
. T.Horiuchi for their useful suggestions.
channel length dependence of nMOS hot carrier effects
have been examined. References
Fig.9 shows 'charge to lifetime' (TI,,) vs impact
ionization rate ( I d , , ) plots [4] for various effective [l] G.A.Sai-Halasz et al., in 1987 IEDM Tech. Dig., p.397.
channel lengths LBpp. The lifetime z is defined by either [2] F.Matsuoka et al., IEEE Trans. Electron Devices, ED-
(A) relative shift in transconductance (Ag,,,/gm=lO%),or 37, 1487 (1990).
(B) absolute shift in source-to-drain linear resistance 131 M.Kakumu et al., EEE Trans. Electron Devices, ED-
(AR=300sZm). For a given I d , , the absolute degradation 37, 1334 (1990).
in R is independent from & down to 0 . 1 ~ The . & [4] C.Hu et al., IEEE Trans. Electron Devices, ED-32, 375
dependence of z in the case of (A) is merely due to the (1985).
difference in the initial R. A shorter device has smaller R, [5] T.Y.Chan et al., IEEE Electron Devices Letters, EDL-
and hence suffers from a larger relative degradation 5, 505 (1984).
36.2.2
884-IEDM 93
-
-m
!3D extension lisp
/ A lpMos1
Schematic MOSFET cross section.
fp)qEm
I \ I
/ P- i
punchthrough t of5nm
stopper
E- -04
8 4
-1
-1Z -2
VDM Vo M Vo M Vc M
(a) nMOS (b) PMOS
Fig3 Shift in linear drain current I,, and charge pumping Fg.4 Lifetime extrapolation for nMOSFET. The lifetime is
current Icp vs stress gate voltage V,. for nMOSFET defined by Ag./&=lO%, where & is the maximum
(LgpP--.16~). transconductance in the linear region.
-1 60 0.5
stress @VD-5V, 310s
36.2.4
886-IEDM 93
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