FP1189 PDF

FP1189
½ - Watt HFET Product Information
Product Features Product Description Functional Diagram

• 50 – 4000 MHz The FP1189 is a high performance ½-Watt HFET GND
(Heterostructure FET) in a low-cost SOT-89 surface-

•
4
+27 dBm P1dB mount package. This device works optimally at a drain
• +40 dBm Output IP3 bias of +8 V and 125 mA to achieve +40 dBm output IP3
• High Drain Efficiency performance and an output power of +27 dBm at 1-dB
compression, while providing 20.5 dB gain at 900 MHz.
• 20.5 dB Gain @ 900 MHz
• Lead-free/Green/RoHS- The device conforms to WJ Communications’ long history 1 2 3
compliant SOT-89 Package of producing high reliability and quality components. The RF IN GND RF OUT
FP1189 has an associated MTTF of greater than 100 years
• MTTF >100 Years Function Pin No.
at a mounting temperature of 85°C and is available in both
the standard SOT-89 package and the environmentally- Input / Gate 1
friendly lead-free/green/RoHS-compliant and green SOT- Output / Drain 3
Applications 89 package. All devices are 100% RF & DC tested. Ground 2, 4
• Mobile Infrastructure
The product is targeted for use as driver amplifiers for
• CATV / DBS wireless infrastructure where high performance and high
• W-LAN / ISM efficiency are required.
• RFID
• Defense / Homeland Security
• Fixed Wireless
Specifications Typical Performance (5)

DC Parameter Units Min Typ Max Parameter Units Typical
Saturated Drain Current, I dss (1) mA 220 290 360 Frequency MHz 915 1960 2140 2450
Transconductance, Gm mS 155 Gain dB 20.6 15.7 14.7 13.2
Pinch Off Voltage, Vp (2) V -2.1 Input Return Loss dB 13 26 24 36
Output Return Loss dB 6.0 9.6 9.0 7.6
RF Parameter (3) Units Min Typ Max Output P1dB dBm +27.4 +27.2 +27.2 +28.1
Operational Bandwidth MHz 50 - 4000 Output IP3 (4) dBm +39.9 +40.4 +39.7 +40.0
Test Frequency MHz 800 Noise Figure dB 2.7 3.7 4.3
Small Signal Gain dB 20.5 IS-95 Channel Power dBm +21 +20.8
@ -45 dBc ACPR
SS Gain (50 Ω, unmatched) dB 17 21 W-CDMA Ch. Power +18.4
Maximum Stable Gain dB 24 @ -45 dBc ACLR
Output P1dB dBm +27.4 Drain Voltage V +8

Output IP3 (4) dBm +40 Drain Current mA 125
Noise Figure dB 2.7 5. Typical parameters represent performance in a tuned application circuit.
Drain Bias +8 V @ 125 mA
1. I dss is measured with Vgs = 0 V, V ds = 3 V.
2. Pinch-off voltage is measured when Ids = 1.2 mA.
3. Test conditions unless otherwise noted: T = 25ºC, VDS = 8 V, IDQ = 125 mA, in a tuned application
circuit with ZL = Z LOPT, ZS = Z SOPT (optimized for output power).
4. 3OIP measured with two tones at an output power of +12 dBm/tone separated by 1 MHz. The
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.
Absolute Maximum Rating Ordering Information

Parameter Rating Part No. Description
Operating Case Temperature -40 to +85 °C FP1189 ½ -Watt HFET
-55 to +150 °C (leaded SOT-89 Pkg)
Storage Temperature
FP1189-G ½ -Watt HFET
DC Power 2.0 W (lead-free/green/RoHS-compliant SOT-89 Pkg)
RF Input Power (continuous) 6 dB above Input P1dB FP1189-PCB900S 870 – 960 MHz Application Circuit
Drain to Gate Voltage, Vdg +14 V FP1189-PCB1900S 1930 – 1990 MHz Application Circuit
Junction Temperature +220° C FP1189-PCB2140S 2110 – 2170 MHz Application Circuit
Operation of this device above any of these parameters may cause permanent damage.
Specifications and information are subject to change without notice.
WJ Communications, Inc • Phone 1-800- WJ1-4401 • FAX: 408-577-6621 • e- mail: sales@wj.com • Web site: www.wj.com September 2004
FP1189
Typical Device Data

S-Parameters (VDS = +8 V, IDS = 125 mA, T = 25°C, calibrated to device leads)
S11 S22
1.0
1.0
S21, Maximum Stable Gain vs. Frequency Swp Max Swp Max
0.8
0.8
6GHz 6GHz
30
6
0.6
0.
0
0
2.
2.
25 0.
4
6 3.0
0.
4
3.
0
5
S21, MSG (dB)
0 0
4. 4.
20 0.2
GH 5.0 2
0.
5.0
4 10.0 10.0
15 GH 6
10.0
10.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0
0
10 5
3 -10.0
4
0
-1 0.
5 DB(|S[2,1]|) DB(MSG) -0.

2
0 -0.
2
0
-5.
.0 3 1 .0
-5.
2
-4 -4
0 .4
2 -3
.0
-3
.0
-0 .4
-0
0 1 2 3 4 5 6
.0
.0
-2
-2
Frequency (GHz)
.6
.6
1
-0
-0
-0.8
-0.8
-1.0
-1.0
Swp Min Swp Min
0.05GHz 0.05GHz
Note:
Measurements were made on the packaged device in a test fixture with 50 ohm input and output lines.
The S-parameters shown are the de-embedded data down to the device leads and represents typical performance of the device.
Freq (MHz) S11 (mag) S11 (ang) S21 (mag) S21 (ang) S12 (mag) S12 (ang) S22 (mag) S22 (ang)
50 1.000 -4.52 10.313 176.55 0.002 87.44 0.544 -3.02
250 0.988 -21.51 10.120 163.88 0.010 76.64 0.535 -13.77
500 0.959 -42.21 9.681 148.45 0.020 64.73 0.520 -27.13
750 0.933 -61.23 9.005 134.71 0.028 53.45 0.495 -39.31
1000 0.895 -78.75 8.270 122.08 0.035 44.25 0.469 -50.54
1250 0.860 -95.09 7.561 109.58 0.040 34.30 0.447 -60.96
1500 0.848 -109.61 7.028 99.15 0.044 26.69 0.428 -70.64
1750 0.821 -122.91 6.408 88.96 0.046 19.57 0.407 -79.82
2000 0.807 -135.32 5.950 79.64 0.048 13.93 0.400 -88.93
2250 0.796 -147.01 5.474 70.37 0.049 7.21 0.386 -97.59
2500 0.785 -157.00 5.087 62.43 0.050 2.99 0.374 -105.24
2750 0.780 -166.26 4.732 53.97 0.050 -1.58 0.376 -113.47
3000 0.775 -175.87 4.415 45.54 0.049 -6.79 0.369 -121.84
3250 0.766 175.78 4.082 38.18 0.049 -9.36 0.368 -129.77
3500 0.770 167.34 3.843 30.76 0.048 -12.48 0.372 -137.25
3750 0.771 159.87 3.602 23.91 0.050 -14.97 0.369 -144.61
4000 0.771 152.07 3.408 16.74 0.050 -17.53 0.374 -152.17
4250 0.771 145.63 3.241 9.15 0.048 -19.53 0.382 -161.00
4500 0.772 138.97 3.053 2.49 0.048 -21.27 0.387 -168.31
4750 0.770 132.07 2.876 -4.50 0.050 -23.00 0.396 -175.08
5000 0.780 126.56 2.743 -10.47 0.048 -25.08 0.408 177.65
5250 0.794 120.21 2.622 -17.28 0.049 -26.64 0.412 170.89
5500 0.795 114.22 2.507 -24.43 0.051 -30.44 0.423 162.41
5750 0.794 108.27 2.346 -31.21 0.052 -30.16 0.442 154.66
6000 0.798 102.86 2.237 -36.95 0.052 -31.18 0.446 147.41
Device S-parameters are available for download off of the website at: http://www.wj.com
FP1189
Application Circuit: 870 – 960 MHz (FP1189-PCB900S)

The application circuit is matched for output power.
Typical RF Performance
Drain Bias = +8 V, Ids = 125 mA, 25°C
Frequency MHz 870 915 960
S21 – Gain dB 20.9 20.6 19.8
S11 – Input Return Loss dB -10 -13 -10
S22 – Output Return Loss dB -5.2 -6.0 -7.6
Output P1dB dBm +27.5 +27.4 +27.5
Output IP3 dBm +39.9
(+12 dBm / tone, 1 MHz spacing)
Noise Figure dB 2.7 2.7 2.6

IS-95 Channel Power dBm +21
@ -45 dBc ACPR
CAP
ID=C10
Vds = 8 V @ 125 mA
C=DNP pF
-Vgg
CAP
ID=C4
C=1000 pF CAP
ID=C11
CAP C=1e5 pF
ID=C3
C=68 pF CAP
ID=C8
C=1000 pF
RES
ID=R1 CAP
R= 20 Ohm CAP
ID=C2 ID=C7
C=18 pF C=68 pF
CAP
ID=C6
C=18 pF
SUBCKT
IND ID=Q1
ID=L1
NET="FP1189"
L=47 nH IND
ID= L3
PORT CAP IND RES 2 RES L =47 nH CAP PORT
P= 1 ID=C1 ID=L4 ID=R2 ID=L2 ID=C9 P= 2
Z =50 Ohm C= 68 pF L=12 nH R= 10 Ohm R=0 Ohm C=68 pF Z =50 Ohm
1
CAP CAP
CAP ID=C12 ID=C5
ID=C13 C= DNP pF C=DNP pF
C=3.9 pF
Bill of Materials
Ref. Desig. Value Part style Size
C1, C3, C7, C9 68 pF Chip capacitor 0603
C2, C6 18 pF Chip capacitor 0603
C4, C8 1000 pF Chip capacitor 0603
C11 0.1 µF Chip capacitor 1206
C13 3.9 pF Chip capacitor 0603
L1, L3 47 nH Multilayer chip inductor 0603
L2 0O Chip resistor 0603
L4 12 nH Multilayer chip inductor 0603
R1 10 O Chip resistor 0603
Q1 FP1189 WJ 0.5W HFET SOT-89
C5, C12, C10 Do Not Place
14 mil GETEKTM ML200DSS (er = 4.2)

The main microstrip line has a line impedance of 50 O.
FP1189
FP1189-PCB900S Application Circuit Performance Plots

S11 vs. Frequency S21 vs. Frequency S22 vs. Frequency
0 22 0
-40c +25c +85c
-5 21 -5
-10 -10
S11 (dB)
S21 (dB)
S22 (dB)
20
-15 -15
19
-20 -20
-25 18 -25
-40c +25c +85c -40c +25c +85c
-30 17 -30
860 880 900 920 940 960 860 880 900 920 940 960 860 880 900 920 940 960
Frequency (MHz) Frequency (MHz) Frequency (MHz)
P1dB vs. Frequency Noise Figure vs. Frequency ACPR vs. Channel Power
IS-95, 9 Ch. Forward, ±885 kHz offset, 30 kHz Meas BW
30 6 -30
freq = 915 MHz
28 5
-40
P1dB (dBm)
ACPR (dBc)
4
NF (dB)
26
3 -50
24
2
22 -60
1
-40c +25c +85c -40c +25c +85c -40 C +25 C +85 C
20 0 -70
860 880 900 920 940 960 860 880 900 920 940 960 16 17 18 19 20 21 22 23 24
Frequency (MHz) Frequency (MHz) Output Channel Power (dBm)
OIP3 vs. Temperature IMD products vs. Output Power OIP3 vs. Output Power
42 fundamental frequency = 915 MHz, 916 MHz; Temp = +25° C fundamental frequency = 915 MHz, 916 MHz; Temp = +25° C
-20 45
IMD products (dBm)
40
OIP3 (dBm)
40
OIP3 (dBm)
38 -40
35
36
-60
IMD_Low
34 freq = 915, 916 MHz 30
IMD_High
+12 dBm / tone
32 -80 25
-40 -15 10 35 60 85 0 4 8 12 16 20 24 0 4 8 12 16 20 24
Temperature (°C) Output Power (dBm) Output Power (dBm)
Output Power / Gain vs. Input Power Output Power / Gain vs. Input Power Output Power / Gain vs. Input Power
frequency = 915 MHz, Temp = -40° C frequency = 915 MHz, Temp = +25° C frequency = 915 MHz, Temp = +85° C
22 30 22 30 22 30
Output Power (dBm)
Output Power (dBm)
Output Power (dBm)
20 26 20 26 20 26
Gain Gain
Gain
Gain (dB)
Gain (dB)
Gain (dB)
18 22 18 22 18 22
16 18 16 18 16 18
14 14 14 14 14 14
Output Power Output Power Output Power
12 10 12 10 12 10
-12 -8 -4 0 4 8 12 -12 -8 -4 0 4 8 12 -12 -8 -4 0 4 8 12
Input Power (dBm) Input Power (dBm) Input Power (dBm)
FP1189

S21 – Gain dB 15.8 15.7 15.5
Output P1dB dBm +27.4 +27.2 +27.4
Noise Figure dB 3.7

IS-95 Channel Power dBm +20.8
@ -45 dBc ACPR
CAP CAP CAP

ID= C4 ID= C10 ID= C3 Vds = 8 V @ 125 mA
C= 33 pF C=DNP pF C= DNP pF
CAP
ID=C11
-Vgg
C=1e5 pF
CAP
ID=C12
C= DNP pF
RES
ID=R1 CAP
R=100 Ohm ID= C8
C= DNP pF
CAP CAP
ID= C13 ID= C7
C=DNP pF C= DNP pF
CAP CAP
ID= C2 ID= C6
C=DNP pF C= 33 pF
SUBCKT
ID= Q1
NET= "FP1189"
IND IND
ID= L1 ID= L3
PORT CAP L= 22 nH 2 IND L= 22 nH CAP PORT
P=1 ID=C1 ID=L2 ID=C9 P=2
Z=50 Ohm C= 33 pF L= 2.7 nH C=33 pF Z=50 Ohm
1
RES
ID= R2
R= 10 Ohm
CAP CAP CAP
ID= C15 ID=C13 ID= C5
C= 1.8 pF C= DNP pF C= 0.5 pF
Bill of Materials
C1, C4, C6, C9 33 pF Chip capacitor 0603
L2 2.7 nH Multilayer chip inductor 0603
C2, C3, C7, C8,
Do Not Place
C10, C12, C13, C14

FP1189

0 17 0
-40C +25C +85C
-5 16 -5
-10 -10
S11 (dB)
S21 (dB)
S22 (dB)
15
-15 -15
14
-20 -20
-25 13 -25
-40C +25C +85C -40C +25C +85C
-30 12 -30
1930 1950 1970 1990 1930 1950 1970 1990 1930 1950 1970 1990
IS-95, 9 Ch. Forward, ±885 kHz offset, 30 kHz Meas BW
30 6 -30
freq = 1960 MHz
28 5
-40
P1dB (dBm)
ACPR (dBc)
4
NF (dB)
26
3 -50
24
2
-60
22 1
-40C +25C +85C -40C +25C +85C -40 C +25 C +85 C
20 0 -70
1930 1950 1970 1990 1930 1950 1970 1990 16 17 18 19 20 21 22 23 24
OIP3 vs. Temperature IMD products vs. Output Power OIP3 vs. Output Power
42 fundamental frequency = 1960, 1961 MHz; Temp = +25° C fundamental frequency = 1960, 1961 MHz; Temp = +25° C
-20 45
IMD products (dBm)
40
OIP3 (dBm)
40
OIP3 (dBm)
38 -40
35
36
-60
34 IMD_Low 30
freq = 1960, 1961 MHz
+12 dBm / tone IMD_High
32 -80 25
-40 -15 10 35 60 85 0 4 8 12 16 20 24 0 4 8 12 16 20 24
Temperature (°C) Output Power (dBm) Output Power (dBm)
Output Power / Gain vs. Input Power Output Power / Gain vs. Input Power Output Power / Gain vs. Input Power
frequency = 1960 MHz, Temp = -40° C frequency = 1960 MHz, Temp = +25° C frequency = 1960 MHz, Temp = +85° C
18 30 18 30 18 30
Output Power (dBm)
Output Power (dBm)
Output Power (dBm)
16 26 16 26 16 26
Gain
Gain (dB)
Gain (dB)
Gain (dB)
14 22 14 Gain 22 14 22
Gain
12 18 12 18 12 18
10 14 10 14 10 14
Output Power Output Power Output Power
8 10 8 10 8 10
-4 0 4 8 12 16 20 -4 0 4 8 12 16 20 -4 0 4 8 12 16 20
Input Power (dBm) Input Power (dBm) Input Power (dBm)
FP1189

S21 – Gain dB 14.7 14.7 14.7
Output P1dB dBm +27.1 +27.2 +26.8
Noise Figure dB 4.2 4.3 4.2

W-CDMA Channel Power dBm +18.4
@ -45 dBc ACPR
-Vgg
CAP Vds = 8 V @ 125 mA
ID=C3
RES C=33 pF
ID=R1
CAP
R =100 Ohm ID=C8
C=1e5 pF
CAP CAP
ID=C11 ID=C7
C=DNP pF C=22 pF
CAP CAP
ID=C2 ID=C6
C=DNP pF C=DNP pF
SUBCKT
ID=Q1
IND NET="FP1189"
IND
ID=L1 ID=L2
PORT CAP L=18 nH 2 IND L=18 nH CAP PORT
ID=C1 RES ID=L3 ID=C9
P=1 ID=R2 P=2
Z =50 Ohm C=22 pF R =10 Ohm L=2.7 nH C=22 pF Z =50 Ohm
1
CAP CAP CAP

ID=C10 ID=C4 ID=C5
C =1.5 pF C =0.5 pF
C=DNP pF
Bill of Materials
C1, C7, C9 22 pF Chip capacitor 0603
C3 33 pF Chip capacitor 0805
L3 2.7 nH Multilayer chip resistor 0603
C2, C4, C6, C11 Do Not Place

FP1189

0 16 0
-40c +25c +85c
-5 15 -5
-10 -10
S11 (dB)
S21 (dB)
S22 (dB)
14
-15 -15
13
-20 -20
-25 12 -25
-40c +25c +85c -40c +25c +85c
-30 11 -30
2110 2130 2150 2170 2110 2130 2150 2170 2110 2130 2150 2170
3GPP W-CDMA, Test Model 1 +64 DPCH, ±5 MHz offset
30 6 -35
freq = 2140 MHz
28 5 -40
P1dB (dBm)
ACPR (dBc)
4 -45
NF (dB)
26
3 -50
24
2 -55
22 1 -60
-40C +25C +85C -40c +25c +85c -40 C +25 C +85 C
20 0 -65
2110 2130 2150 2170 2110 2130 2150 2170 13 14 15 16 17 18 19 20 21
OIP3 vs. Temperature Output Power / Gain vs. Input Power OIP3 vs. Output Power
42 frequency = 2140 MHz, Temp = +25° C fundamental frequency = 1960, 1961 MHz; Temp = +25° C
16 30 45
40
Output Power (dBm)
14 26
OIP3 (dBm)
40
OIP3 (dBm)
Gain
Gain (dB)
38 12 22
35
36
10 18
34 freq = 2140, 2141 MHz 30
8 Output Power 14
+12 dBm / tone
32 6 10 25
-40 -15 10 35 60 85 0 4 8 12 16 20 0 4 8 12 16 20 24
Temperature (°C) Input Power (dBm) Output Power (dBm)
Output Power / Gain vs. Input Power IMD products vs. Output Power Output Power / Gain vs. Input Power
frequency = 2140 MHz, Temp = -40° C fundamental frequency = 2140, 2141 MHz; Temp = +25° C frequency = 2140 MHz, Temp = +85° C
16 30 -20 16 30
IMD products (dBm)
Output Power (dBm)
Output Power (dBm)
14 26 14 26
Gain
Gain (dB)
Gain (dB)
-40
12 22 12 Gain 22
10 18 10 18
-60 IMD_Low
8 14 8 14
Output Power Output Power
IMD_High
6 10 -80 6 10
0 4 8 12 16 20 0 4 8 12 16 20 24 0 4 8 12 16 20
Input Power (dBm) Output Power (dBm) Input Power (dBm)
FP1189
Reference Design: 2450 MHz

Typical RF Performance, 25°C

S-Parameters
S21 – Gain dB 13.2 10
S11 – Input Return Loss dB -36 5 DB(|S[1,1]|) DB(|S[2,1]|) DB(|S[2,2]|)
S22 – Output Return Loss dB -7.6 0

-5
Output P1dB dBm +27.5 +28.1
-10
Output IP3 dBm +38 +40
(+12 dBm / tone, 1 MHz spacing) -15
Drain Voltage V +8 +8 -20
Drain Current mA 100 125 -25
-30
The 2450 MHz Reference Circuit is shown for design purposes only. An 2200 2300 2400 2500 2600 2700
evaluation board is not readily available for this application. The reader can Frequency (MHz)
obtain an FP1189-PCB2140S evaluation board and modify it with the circuit
shown to achieve the performance shown in this reference design. Only two
component changes are required (C4 and L3) from the FP1189-PCB2140S
evaluation board.
Vds = 8 V @ 125 mA
-Vgg CAP
CAP ID=C8
ID=C3
C= 33 pF C= 100000 pF
RES
ID=R1 CAP
R= 100 Ohm ID=C6
C= DNP pF
CAP
ID=C2
C= DNP pF CAP
ID=C7
C= 22 pF
TLINP TLINP TLINP

ID=TL1 ID=TL3 ID=TL4
IND Z0=50 Ohm Z0=50 Ohm Z0=50 Ohm IND
ID=L1 L=135 mil L= 80 mil L= 35 mil ID=L2
CAP L= 18 nH Eeff=4.2 2 Eeff=4.2 IND Eeff=4.2 L=18 nH
PORT ID=C1 RES ID=L3 PORT
P= 1 Loss=0 ID=R2 Loss=0 Loss=0 P= 2
Z= 50 Ohm C= 22 pF F0=0 MHz R= 10 Ohm F0=0 MHz L=1.8 nH F0=0 MHz Z= 50 Ohm
1
TLINP
I D =TL2 CAP
Z 0 =50 Ohm I D =C7
CAP L=45 mil CAP
ID=C4 ID=C5 C= 22 pF
C= 1.2 pF Eeff=4.2 C =0.5 pF
L o s s =0
F 0 =0 MHz SUBCKT
I D =Q1
NET="FP1189"
The lengths shown in the microstrip lines are referenced from the component or pin edge-to-edge.
Bill of Materials
C1, C7, C9 22 pF Chip capacitor 0603
C3 33 pF Chip capacitor 0805
L3 1.8 nH Multilayer chip resistor 0603
C4 R2 10 O Chip resistor 0603
C2, C4, C6, C11 Do Not Place

FP1189
Application Note: Constant-Current Active-Biasing

Special attention should be taken to properly bias the FP1189. +Vdd
Power supply sequencing is required to prevent the device from
operating at 100% Idss for a prolonged period of time and possibly
causing damage to the device. It is recommended that for the safest
R1 R2
operation, the negative supply be “first on and last off.” With a
negative gate voltage present, the drain voltage can then be applied
U1
to the device. The gate voltage can then be adjusted to have the 1 C1
4 Rohm UMT1N
device be used at the proper quiescent bias condition. .01 µF
2 5
An optional active-bias current mirror is recommended for use with
the application circuits shown in this datasheet. Generally in a 3 6
laboratory environment, the gate voltage is adjusted until the drain R4
draws the recommended operating current. The gate voltage 1 kΩ
required can vary slightly from device to device because of device
R3
pinchoff variation, while also varying slightly over temperature. R5
RF OUT
RF IN
The active-bias circuit, shown on the right, uses dual PNP transistors M.N. DUT M.N.
to provide a constant drain current into the FP1189, while also -Vgg
eliminating the effects of pinchoff variation. This configuration is HFET Application Circuit
best suited for applications where the intended output power level of
the amplifier is backed off at least 6 dB away from its compression
point. With the implementation of the circuit, lower P1dB values Parameter FP1189
may be measured for a Class-AB amplifier, where the device will Pos Supply, Vdd +8 V
attempt to source more drain current while the circuit tries to provide Neg Supply, Vgg -5 V
a constant drain current. The circuit should be connected directly in Vds +7.75 V
Ids 125 mA
line with where the voltage supplies would be normally connected
R1 62 Ω
with the amplifier circuit, as shown the diagram. Any required
matching circuitry remains the same, although it is not shown in the R2 2.0 Ω
R3 1.8 kΩ
diagram. This recommended active-bias constant-current circuit
R4 1 kΩ
adds 7 components to the parts count for implementation, but should
cost only an extra $0.144 to realize ($0.10 for U1, $0.0029 for R1, R5 1 kΩ
R3, R4, R5, $0.024 for R2, and $0.0085 for C1).
Temperature compensation is achieved by tracking the voltage

variation with the temperature of the emitter-to-base junction of the
two PNP transistors. As a 1st order approximation, this is achieved
by using matched transistors with approximately the same Ibe
current. Thus the transistor emitter voltage adjusts the HFET gate
voltage so that the device draws a constant current, regardless of the
temperature. A Rohm dual transistor - UMT1N - is recommended
for cost, minimal board space requirements, and to minimize the
variation between the two transistors. Minimizing the variability
between the base-to-emitter junctions allow more accuracy in setting
the current draw. More details can be found in a separate application
note “Active-bias Constant-current Source Recommended for
HFETs” found on the WJ website.
FP1189
FP1189 (SOT-89 Package) Mechanical Information

This package may contain lead-bearing materials. The plating material on the leads is SnPb.
Outline Drawing Product Marking

The FP1189 will be marked with an
“FP1189” designator. An alphanumeric lot
code (“XXXX-X”) is also marked below the
part designator on the top surface of the
package.
Tape and reel specifications for this part are

located on the website in the “Application
Notes” section.
MSL / ESD Rating
ESD Rating: Class 1B

Value: Passes /500V to <1000V
Test: Human Body Model (HBM)
Standard: JEDEC Standard JESD22-A114
Land Pattern ESD Rating: Class IV

Value: Passes at 2000 V min.
Test: Charged Device Model (CDM)
Standard: JEDEC Standard JESD22-C101
MSL Rating: Level 3 at +235° C convection reflow

Standard: JEDEC Standard J-STD-020
Mounting Config. Notes

1. Ground / thermal vias are critical for the proper
performance of this device. Vias should use a .35mm
(#80 / .0135”) diameter drill and have a final plated
thru diameter of .25 mm (.010”).
2. Add as much copper as possible to inner and outer
layers near the part to ensure optimal thermal
performance.
3. Mounting screws can be added near the part to fasten
the board to a heatsink. Ensure that the ground /
thermal via region contacts the heatsink.
4. Do not put solder mask on the backside of the PC board
in the region where the board contacts the heatsink.
5. RF trace width depends upon the PC board material
and construction.
6. Use 1 oz. Copper mi nimum.
7. All dimensions are in millimeters (inches). Angles are
in degrees.
Thermal Specifications 100

MTTF vs. GND Tab Temperature
Parameter Rating
MTTF (million hrs)
Operating Case Temperature -40 to +85°C

10
Thermal Resistance, Rth (1) 68° C/W
Junction Temperature, Tjc (2) 153° C
1
1. The thermal resistance is referenced from the hottest
part of the junction to the ground tab (pin 4).
2. This corresponds to the typical drain biasing condition
0
of +8V, 125 mA at an 85°C case temperature. A
60 70 80 90 100 110 120
minimum MTTF of 1 million hours is achieved for
Tab Temperature (°C)
junction temperatures below 160 °C.
FP1189
FP1189-G (Green / Lead-free SOT-89 Package) Mechanical Information

This package is lead-free/Green/RoHS-compliant. It is compatible with both lead-free (maximum 260°C reflow temperature) and leaded
(maximum 245°C reflow temperature) soldering processes. The plating material on the leads is NiPdAu.
Outline Drawing Product Marking

The FP1189-G will be marked with an
“FP11G” designator. An alphanumeric lot
code (“XXXX-X”) is also marked below the
part designator on the top surface of the
package.
Tape and reel specifications for this part are

located on the website in the “Application
Notes” section.
MSL / ESD Rating
ESD Rating: Class 1B

Value: Passes /500V to <1000V
Land Pattern Test: Human Body Model (HBM)
Standard: JEDEC Standard JESD22-A114
ESD Rating: Class IV

Value: Passes at 2000 V min.
Test: Charged Device Model (CDM)
Standard: JEDEC Standard JESD22-C101
MSL Rating: Level 3 at +260° C convection reflow

Standard: JEDEC Standard J-STD-020
Mounting Config. Notes

1. Ground / thermal vias are critical for the proper
performance of this device. Vias should use a .35mm
(#80 / .0135”) diameter drill and have a final plated
thru diameter of .25 mm (.010”).
2. Add as much copper as possible to inner and outer
layers near the part to ensure optimal thermal
performance.
3. Mounting screws can be added near the part to fasten
the board to a heatsink. Ensure that the ground /
thermal via region contacts the heatsink.
4. Do not put solder mask on the backside of the PC board
in the region where the board contacts the heatsink.
5. RF trace width depends upon the PC board material
and construction.
6. Use 1 oz. Copper minimum.
7. All dimensions are in millimeters (inches). Angles are
in degrees.
Thermal Specifications 100
MTTF vs. GND Tab Temperature
Parameter Rating
MTTF (million hrs)
Operating Case Temperature -40 to +85°C

10
Thermal Resistance, Rth (1) 68° C/W
Junction Temperature, Tjc (2) 153° C
1
1. The thermal resistance is referenced from the hottest
part of the junction to the ground tab (pin 4).
2. This corresponds to t he typical drain biasing condition
0
of +8V, 125 mA at an 85°C case temperature. A
60 70 80 90 100 110 120
minimum MTTF of 1 million hours is achieved for
Tab Temperature (°C)
junction temperatures below 160 °C.

FP1189 PDF

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FP1189

½ - Watt HFET Product Information

Product Features Product Description Functional Diagram

(Heterostructure FET) in a low-cost SOT-89 surface-

Specifications Typical Performance (5)

Output P1dB dBm +27.4 Drain Voltage V +8

Absolute Maximum Rating Ordering Information

Typical Device Data

5 DB(|S[2,1]|) DB(MSG) -0.

Specifications and information are subject to change without notice.

Application Circuit: 870 – 960 MHz (FP1189-PCB900S)

Noise Figure dB 2.7 2.7 2.6

14 mil GETEKTM ML200DSS (er = 4.2)

Specifications and information are subject to change without notice.

FP1189-PCB900S Application Circuit Performance Plots

Output Power (dBm)

Output Power (dBm)

Specifications and information are subject to change without notice.

Application Circuit: 1930 – 1990 MHz (FP1189-PCB1900S)

Noise Figure dB 3.7

CAP CAP CAP

14 mil GETEKTM ML200DSS (er = 4.2)

Specifications and information are subject to change without notice.

FP1189-PCB1900S Application Circuit Performance Plots

Output Power (dBm)

Output Power (dBm)

Specifications and information are subject to change without notice.

Application Circuit: 2110 – 2170 MHz (FP1189-PCB2140S)

Noise Figure dB 4.2 4.3 4.2

CAP CAP CAP

14 mil GETEKTM ML200DSS (er = 4.2)

FP1189-PCB2140S Application Circuit Performance Plots

Output Power (dBm)

Specifications and information are subject to change without notice.

Reference Design: 2450 MHz

Typical RF Performance, 25°C

S21 – Gain dB 13.2 10

S11 – Input Return Loss dB -36 5 DB(|S[1,1]|) DB(|S[2,1]|) DB(|S[2,2]|)

S22 – Output Return Loss dB -7.6 0

TLINP TLINP TLINP

14 mil GETEKTM ML200DSS (er = 4.2)

Specifications and information are subject to change without notice.

Application Note: Constant-Current Active-Biasing

Temperature compensation is achieved by tracking the voltage

Specifications and information are subject to change without notice.

FP1189 (SOT-89 Package) Mechanical Information

Outline Drawing Product Marking

Tape and reel specifications for this part are

MSL / ESD Rating

ESD Rating: Class 1B

Land Pattern ESD Rating: Class IV

MSL Rating: Level 3 at +235° C convection reflow

Mounting Config. Notes

Thermal Specifications 100

Operating Case Temperature -40 to +85°C

FP1189-G (Green / Lead-free SOT-89 Package) Mechanical Information

Outline Drawing Product Marking

Tape and reel specifications for this part are

MSL / ESD Rating

ESD Rating: Class 1B

ESD Rating: Class IV

MSL Rating: Level 3 at +260° C convection reflow