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Performance Evaluation of Innovative Ion-
Sensitive Field Effect Diode for pH Sensing
Ehsan Mohammadi, Negin Manavizadeh
 demands to be addressed including a large dynamic range,
Abstract— In this paper, we have successfully introduced and
characterized an innovative ion sensitive device called “Ion
sensitive field effect diode”, a completely new ion-sensitive sensor.
In conventional ion-sensitive devices, electrolyte/insulator
interface reactions produce a conductive channel between the
drain and the source whereas in our proposed structure, a p-n
junction forms and is responsible for the conductivity. Since it is
for the first time that such device is proposed as an ion sensor,
comprehensive characterizations have been performed based on
our previously TCAD-based model which was developed to
simulate electrolyte and electrolyte/insulator interface.
Considering this reliable model, sensing parameters of pH sensors
such as sensitivity and signal to noise ratio are investigated and
evaluated. Meanwhile, an accurate model to approximate the noise
behavior of the device is proposed. Moreover, the effect of Silicon
active layer thickness and doping concentration on the sensitivity
of the device have been studied. Results reveal that ion sensitive
field effect diode can achieve sensitivity about 5 times higher than
the Nernst limit and can be considered as a promising candidate
toward accurate and more sensitive ion sensors and this new type
of sensor deserves further attention and development.
Index Terms— Detection Limit, Electrolyte/insulator interface,
Ion Sensitive Field Effect Diode, TCAD-based model, pH sensor.
I. INTRODUCTION
E NVIRONMENTAL and biological sensing have gained
increasing attention during the last decades and biosensors, as a
tool to monitor these samples, have grown rapidly in both
research and industry. Since 1970s and invention of Ion
Sensitive Field Effect Transistor (ISFET) [1], this device has
been used in vast applications including health care [2],
environmental monitoring [3], food safety [4], living cell and
antibody-antigen studies, diagnosis of disease, discovery new
drugs and recently, DNA sequencing [5]–[10]. This growth and
wide using of ISFETs owed to rapid and real-time detection,
label-free and CMOS process compatibility [11]. CMOS
compatibility offers high-throughput fabrication process and
therefore low cost sensor, mass production, miniaturization and
integration with read-out circuits, which brings an array of
sensors as a Lab-on-chip handheld devices [5], [12]–[14].
Because of these advantages, ISFETs can compete as a
promising sensory platform with other chemical, labeling, and
optical detection techniques. Although there are limits and
Manuscript received September, 2018.
The authors are with the Faculty of Electrical Engineering, K. N. Toosi
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higher sensitivity, and lower detection limit, several researches
have been conducted to increase the performance of ISFETs.
These researches utilized new materials and innovative
structures such as nanowires, carbon nanotubes, several two-
dimensional materials and dual gate ISFETs [15]–[21].
On the other hand, a different structure of field effect devices
have been proposed and investigated during last two decades to
meet the digital electronics requirements, called Field Effect
Diodes (FEDs) [22]–[25]. Suppressing short channel effects as
well as avoiding channel pinch-off, high Ion to Ioff ratio, lower
subthreshold slope, providing lower energy-delay product all
together with the CMOS process compatibility, offer the FEDs
a promising perspective as a candidate for future logic devices
[22], [23], [26].
FED, like field effect transistor, utilizes the electric field to
make a conductive channel between the source and the drain;
however, doping of the source and the drain areas are opposite
and consist of donor and acceptor dopant, respectively.
Moreover, as another difference, two gates over the channel
control carrier behavior. In this case, by applying different gate
voltages (negative or positive) the local density of majority
carriers can be controlled. Thanks to opposite doping of the
drain and the source, both the electrons and the holes are
available and various local carriers densities can be formed
from the source to the drain. As an example, by applying
positive and negative voltage to the near-the-source-gate (GS)
and near-the-drain-gate (GD) respectively, source-to-drain
channel profile would make an n+npp+ structure which behaves
similar to a forward biased p-n junction diode and conducts the
current, whereas by switching the gates voltages, channel
profile would rearrange as an n+pnp+ which acts as a reversed
bias p-n junction diode and suppresses the current efficiently.
Fig. 1 illustrates these conditions.
So far, FED device families have been utilized as
electrostatic discharge protection [25], memory cell [27], high-
speed digital family and recently logic gates [26], [28].
In this paper, FED has been utilized for ion sensing purposes
and the performance including sensitivity and signal-to-noise
(SNR) has been investigated, according to pH changes as a
standard benchmark [29].
A set of simulations has been conducted to study the device
performance. Since commercial TCAD tools do not support the
physics of the electrolyte/insulator interface to simulate, the
University of Technology, Tehran 1631714191, Iran (e-mail:
E_mohammadi@ee.kntu.ac.ir; manavizadeh@kntu.ac.ir).
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previously established model has been used to imitate To realize the behavior of the device in this configuration, a
electrolyte/insulator physics and evaluate the surface charge single gate FED is simulated to serve as the reference. Fig. 3
density produced by the solution [30]. Then the model was shows the IDS versus gate voltage and back gate voltage curve
applied to Field Effect Diode to study ion sensitivity and of the device. Increasing the gate voltage toward more positive
performance of the device. voltages, increases the electrons concentration beneath the gate,
makes a p-n-n configuration (n-channel) from drain to source
+ _
(a) Source Drain whereas decreasing the voltage, makes p-p-n configuration (p-
GS GD +
channel). As mentioned, both states conduct the current and the
n+ p+ lowest conductance of the channel occurs at depletion, as
Buried Oxide Forward p-n junction observed in Fig. 3.
Substrate

(b) _ +
Source GS GD Drain
+

n+ p+
Buried Oxide Reverse p-n junction

Substrate

Figure 1 schematics view of FED structure and biasing conditions under (a)
forward p-n junction bias and (b) reversed p-n junction bias.

II. RESULTS AND DISCUSSION

A. Physical Model
To study the performance of Field Effect Diode in an ion
sensor configuration, an accurate and robust platform for Ion
sensitive devices analysis is needed. To pursue this, with
respect to the similarity between anions (cations) in the solution
and electrons (holes) in the semiconductor, one can develop a
model to describe the Electrolyte and interactions between the
Electrolyte and the insulator. Thus, the behavior of the device
can be modeled. The model is already described thoroughly in
[30] and compared with literature to confirm the validation and
accuracy of the model.
Figure 3 Electrical characteristics of FED for (a) top gate and (b) back gate
B. Ion sensitive field effect diode voltage sweep.
To exploit the benefits of FED, it was made compatible with
Similar to ISFET, changes of pH alter carrier concentration
ion sensing configuration requirements. The most notable
in the channel, which changes p-n junction characteristics, and
change is that both gates were replaced by the Electrolyte. This
cause to change in drain current. Fig. 4 demonstrates I-V
makes ion sensitive field effect diode (ISFED) like a tunneling
characteristics of ISFED in single and dual gate responses. It is
ISFET [31], while in this case, the p-n junction is set to forward
notable that, due to overcoming the built-in potential of the
bias. Fig. 2 illustrates the schematics view of the sensor. Unlike
diode, the drain-source voltage was set to 700 mV.
the traditional FED, a reversed bias would not happen and the
To simulate ISFEDs, TCAD tool was used with taking effect
least conductivity of the channel occurs at depletion, where
of the following models: Fermi-Dirac carrier statistics,
there is no carrier in the channel to make a conductive channel
Klaassen, Shirahata and lateral electric field-dependent carrier
between the source and the drain.
Fluid Gate mobility, band gap narrowing and Shockley–Read–Hall and
Solution
Auger recombination models [32]. Measurement of the
sensitivity was done using constant current mode i.e. a constant
SiO2
drain current was considered and the shift of I-V curves are
Source Drain reported as the sensitivity. According to Fig. 4, sensitivity of
+ single gate ISFED is the same as of ISFET whereas sensitivity
n+ p+ of dual gate configuration follows a partly different trend. Fig.
5 shows the sensitivity of ISFEDs with various source/drain
Buried Oxide Forward p-n junction doping concentrations for different Silicon thicknesses.
Substrate Dependency of the sensitivity on the Silicon thickness is more
Back Gate
than that of ISFET: while conductance in the ISFET occurs only
Figure 2 Schematic view of ion sensitive field effect diode structure in the case among channel, ISFED can provide a current path between
of positive Fluid gate voltage where p-n junction occurs near the drain.

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source and drain through body, which comes from p-i-n
configuration between terminals. This becomes serious with
thicker bodies, where the resistance of the path decreases.
Figure 4 IDS versus (a) Fluid gate and (b) Back gate voltage for pH 3 to 11 (Si
thickness is 20 nm and oxides thicknesses are 5 and 50 nm for the top and
bottom oxides, respectively and the Source/Drain doping concentration is 1016
cm-3). Insets represent gate voltage responsible for reference current for
different pH values (The reference current of the inset is 50 nA).
Another observation from Fig. 5 is doping concentration
dependency of sensitivity. As shown in this figure, an increase
in the doping concentration leads to lower sensitivity. To
address this phenomenon, carrier concentration in the depth of
Silicon body (from buried oxide to top oxide) is studied.
Figure 5 Sensitivity of ISFEDs with various active layers and doping
concentration (Top oxide and buried oxide are 5 and 50 nm, respectively).
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pH is set to 7, while both gates are grounded and Silicon
thickness is 25 nm. To flow current between the drain and the
source, a conductive channel should be made between them.
This channel could be either electron dominant (n-channel) or
hole dominant (p-channel), depending on the gate voltage. For
electron dominant condition, the difference between carrier
concentrations before and after pH changes (or applying
electric field) depends on the doping concentration since initial
electron concentration in the channel depends highly on the
doping concentration; as a result, in an n-channel device,
sensitivity depends highly on the doping concentration.
Although, this is not the case for hole dominant condition. This
means regardless of doping concentration, the difference
between hole concentration in the channel before and after pH
changes, is almost constant. Moreover, hole concentrations
which are high enough to make a hole-rich channel, lead to low
sensitivities since pH changes make no considerable effect on
the channel condition. This also can be observed in Fig. 4b in
low voltages where ISFED shows very poor sensitivity on p-
channel configuration.
Figure 6 Electrons concentration among the Silicon layer (From buried oxide
interface to top oxide interface). The inset shows the same for the holes. Note
that electron concentration varies with doping while hole concentrations are
almost insensitive to the doping concentration.
Fig. 7 represents I-V curves of an ISFED while voltage applied
to both gates. For each curve, back gate was swept while the
fluid gate is a parameter. All the curves obtained with pH = 7
condition. Higher fluid gate voltage enriches channel with
electrons and as a result, minimum conductivity is pushed to
lower back gate voltage. This happens because a higher
negative back gate voltage is needed to provide enough holes in
the channel to compensate excessive electrons concentration
and make least-conduction-channel condition.
The inset of Fig.7 illustrates minimum point of each curve
against corresponding fluid gate voltage. The slope of the line
indicates the capacitive coupling between the fluid gate and
back gate: the more the slope, the higher coupling occurs. This
suggests that the sensitivity drops with increasing fluid gate,
which is in opposite of the ISFET case.
C. Noise in ISFED
To investigate the performance of ISFEDs, SNR studies have
been performed. SNR can give a good insight about device
performance, since higher SNR leads to lower detection limit
and sensors that are more accurate. For ISFETs, it turns out that
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some models can be driven from p-n junction noises; p-n

Figure 7 IDS versus Back gate voltage for pH 7 with the fluid gate as a parameter
swept from 0 to 1.6 V. The inset shows minimum voltage of each curve against
corresponding fluid gate voltage.
although dual gate configuration enhances the device
sensitivity, detection limit experience no noticeable
enhancement since SNR remains unchanged [33]. The noise
study was performed for low-frequency noise, which is within
the working condition of the device where Flicker noise is
1
dominant [6] which is proportion to . Fig. 8a and 8d represent
𝑓
the power spectral density of ISFED in single and dual gate,
respectively. These figures were obtained from an ISFED with
10 nm Silicon body thickness and source/drain doping
concentration of 1016 cm-3.
There is no model describing noise relations in FEDs, though
junction noises were examined by two models, called Hooge
and McWhorter [34]. Hooge model considers carrier number
fluctuations due to trapping while in McWhorter model, noise
source is considered as recombination of carriers in the device
surface. Hooge model, in low-level currents, is proportion to
leakage current (𝐼0 ) while McWhorter model takes (𝐼02 ) as
proportional factor. Nevertheless, Hooge model is more
realistic in p-n junctions, since FEDs and diodes have some
differences, McWhorter model looks fits better in this case,
especially there is Silicon/oxide interface in FEDs, which is a
remarkable difference and tends to make more accurate
predictions with McWhorter model.
Fig. 8b and e show 𝑆𝐼 versus drain current. In these figures
also, a curve proportion to (𝐼 2 ) is plotted which is in turn
proportion to (𝐼02 ). As illustrated, the curves fit well with
McWhorter model. It is noticeable that in the lowest current, the
curves break up which is due to the fact that there is a minimum
current where the channel is depleted and p-i-n configuration is
formed.
SNR of ISFED is shown in Fig. 8c and f and is defined as
follows:
∆𝐼𝑑
𝑆𝑁𝑅 = (1)
𝛿𝑖𝑑
where ∆𝐼𝑑 is the changes of the drain current due to pH
changes (signal) and 𝛿𝑖𝑑 is the root-mean-square (RMS) of 𝑆𝐼
defined as:
𝑓
𝛿𝑖𝑑 = √∫𝑓 2 𝑆𝐼 𝑑𝑓 (2)
1

Figure 8 Power spectral density of current noise for (a) Fluid gate and (d) Back gate sweep in low frequencies in which another gate is grounded (Dotted lines
indicate 1/f slope as a reference). The normalized power spectral density of current noise for (b) Fluid gate and (e) Back gate (f = 64 Hz) plotted against Id2. SNR
and transconductance of (c) Fluid gate and (f) Back gate sweep. Signals obtained from drain current differences between pH 5 and 6. Transconductance measured at
pH = 5 (Triangles indicate maximum points) (Device with active layer thickness is 10 nm and Source/Drain doping concentration of 1016 cm-3 was examined.)

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and 𝑓1 and 𝑓2 indicate the frequency window.
The peak of the SNR occurs near to peak of
transconductance (like in the case of ISFET[30]), although, the
value of SNR in single gate and dual gate modes are different
(in contrast with ISFETs) and single gate mode shows better
performance. Greater value of power spectral density of current
noise, which is higher in dual gate mode, may consider as the
source of the difference.
As mentioned, power spectral density of current noise tends
to decrease dramatically as the drain current decreases,
consequently, making devices with lower minimum current
may lead to sensors with higher SNR and better performance,
which pave the way to more accurate and sensitive biosensors.
III. CONCLUSION
In this paper, a new type of ion sensitive device based on
FED families was effectively introduced. The device employs
electrolyte/insulator interface charges to modulate carriers’
density in a PIN structure and as a result, changes the current.
Numerical model has been used to simulate field effect diode in
a TCAD tool. Results showed that doping concentration of
source/drain regions as well as the Silicon thickness affect the
sensitivity; lower doping concentration and thinner Silicon
active layer result in higher sensitivity. Electron concentration
depends highly on the doping concentration which causes the
high dependency to the doping concentration. Active body
thickness affects the sensitivity in a stronger way than that of
ISFETs because of additional conductive path deep in the
device between the source and the drain. In this case, a sensor
with a doping concentration of 1015 cm-3 and 10 nm Silicon
layer thickness shows sensitivity about 5 times higher than the
Nernst limit. Results also indicated that SNR of this type of
sensor can achieve higher values in single gate configuration,
means fluid gate mode of ISFEDs serves as a better sensor. This
paper shows that utilizing ISFED opens up a new type of
sensors which worth to pay attention and investigate carefully.
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vol. 43, no. 2, pp. 362–365, 1996, doi: Negin Manavizadeh was born in Tehran, Iran, in 1980. She
10.1109/16.481742. received the B.S. and M.S. degrees in solid-
[25] S. Cao, S. Member, A. a Salman, J. Chun, S. G. Beebe, state physics and the Ph.D. degree in
M. M. Pelella, S. Member, and R. W. Dutton, “Design electrical engineering from the K. N. Toosi
and Characterization of ESD Protection Devices for University of Technology (KNTU),
High-Speed I / O in Advanced SOI Technology,” IEEE Tehran, in 2003, 2006, and 2012,
Trans. Electron Devices, vol. 57, no. March, pp. 644– respectively. In 2011, she joined the
653, 2010. Institute of Microelectronics, Vienna
[26] B. J. Touchaee and N. Manavizadeh, “An inverter gate University of Technology as a visiting
design based on nanoscale S-FED as a function of researcher. She is currently a full-time Assistant Professor with
reservoir thickness,” IEEE Trans. Electron Devices, the Faculty of Electrical Engineering, KNTU, and has been the
vol. 62, no. 10, pp. 3147–3152, 2015, doi: Director of Nano Structures Laboratory (NSL), since 2017.
10.1109/TED.2015.2463099. From 2016 to 2018, she was the Director of the Center for
[27] M. Amirmazlaghani and F. Raissi, “Memory cell using Research and Technology, CReaTech, KNTU. Her research
modified field effect diode,” IEICE Electron. Express, interests include modeling, simulation and fabrication of
vol. 6, no. 22, pp. 1582–1586, 2009, doi: semiconductor and microfluidic devices.
10.1587/elex.6.1582.
[28] B. J. Touchaei and N. Manavizadeh, “Design and
Simulation of Low-Power Logic Gates Based on
Nanoscale Side-Contacted FED,” IEEE Trans.
Electron Devices, vol. 64, no. 1, pp. 306–311, 2017,

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