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Ultra-Low Voltage Design for Interconnections

Chinwuba D. Ezekwe
Department of Electrical Engineering and Computer Sciences
University of California at Berkeley

Abstract—This paper is concerned with minimal level to yield the ultimate in power
high-speed, low-swing, off-chip signaling savings and transmission rates. In practice, further
circuits for Gb/s serial data communication. In swing reduction requires increased receiver
previous work, energy savings was limited by sensitivity, corresponding to increased receiver
power consumption in the transmitter primarily power consumption.
due to the need to drive the termination In this paper, we review a number of existing
resistors at the prevailing signal swings and at interface circuits and evaluate their effectiveness
the receiver due to the need to have a wide for further swing reduction.
common-mode input range. This paper surveys
existing work with the view of reducing energy II. ULTRA-LOW VOLTAGE DESIGN
consumption through proper choice of
The resistance of board wires is sufficiently
transmitter and receiver architecture and
low to be ignored. But, at the high transmission
further reduction in signal swings. This is
rates under consideration, the effect of wire
possible without the loss of signal integrity
inductance becomes quite significant. Essentially,
because the fundamental limit as dictated by
the wavelengths of the frequency components of
thermal noise is several orders of magnitude less
the transmitted signal become comparable to the
than the signal swings in present use.
length of the wire such that an accurate modeling
of signal propagation must take the signal’s wave
nature into account. This requires that the wire be
With the demand for ever increasing considered a transmission line. To avoid signal
microprocessor speeds comes an associated reflections, the line is terminated by its
demand for higher speed interface circuits. At high characteristic impedance, typically 50Ω . It
frequencies, dielectric losses and impedance becomes necessary sometime to add source
mismatches, in addition to resistive losses, varying termination for improved signal integrity at the cost
dielectric constant, crosstalk and thermal noise, of extra power dissipation. These main aspects of
cause high levels of distortion of the received high-speed low-swing signaling are shown in Fig.
signal. Because of its relatively low dispersion and 1.
attenuation characteristics, it is speculated that The characteristic impedance of the line
optical links may be the answer to the high-speed specifies the minimum current that must be sourced
interconnect problem [1]. However, its use at and sunk by the transmitter given the sensitivity of
present comes at a significant expense and the receiver. Reducing this current, thus reducing
inconvenience. Consequently conventional the signal swing, and providing it from a reduced
electrical interconnects remain the method of supply voltage will result in quadratic savings in
choice. energy at the transmitter.
In recent years, low swing interface circuits
Transmitter Receiver
have received significant attention for both on-chip Z0
and off-chip signaling as they allow for higher Vin Vout
transmission rates and lower power consumption RS RL
[2], [3]. These benefits come at the cost of signal
Vin Vout
integrity due to the reduced noise margins. Signal Z0
integrity is improved, however, by the use of
differential signaling, with its high common-mode Figure 1 Simplified schematic of a high-speed
rejection, at the cost of more wiring space. differential link, with optional source termination
Because the data in a differential signal is resistor.
distinguished by the differential voltage polarity as
opposed to the absolute signal voltage level, the
signal swing can, in the ideal case, be reduced to a
III. EXISTING LOW-SWING I/O CIRCUITS B. Static Driver with Reduced Supply
A. Current-Mode Driver The circuit shown in Fig. 3a is a well-known
on-chip level conversion circuit [7]. It consists of a
These are widely used in LVDS transmitters.
couple of inverters and achieves low swing by
They simply direct switched-polarity currents into
using a reduced supply voltage. It is possible to
the transmission line [4], [5]. This is accomplished
replace the PMOS pull-up transistors with NMOS
by the use of a current source, a current sink, and
transistors as shown in Fig. 3b to take advantage of
two NMOS and PMOS switches in bridge
their much lower drive resistance [8]. The low
configuration to steer current of the correct polarity
common-mode output level of these level
to each output. A variation on this theme involves
converters, which is about half of the reduced
the use of all-NMOS switches [6]. The utility of an
supply voltage, has limited their use to on-chip
all-NMOS switch setup is limited, however,
signaling where the absolute ground reference
especially if mid-rail common-mode outputs are
voltage is approximately the same everywhere.
desired because this significantly reduce the
With an AC coupled receiver, however, it becomes
overdrive voltage available for the top switches.
possible to take advantage of the quadratic gains in
At very high frequencies, single termination at
energy savings offered by these level converters.
the load may fail to provide sufficient signal
integrity. In this case, signals reflected from the
load to the source are reflected back to the load. Vddl
Under this condition, source termination is often
included to minimize the second reflection and
thereby improve signal integrity at the cost of extra
power dissipation [4]. Source termination can be
Vout Vin
purely differential, in which case the termination
resistor is tied between the two output nodes. With Vin Vout
this, common-mode signals reflected back from the
load are still fully reflected at the source back to
the load with some being converted to differential
mode noise due to source impedance mismatches
that are often quite significant. A differential
termination that is center-tapped to a stable low-
impedance source as shown in Fig. 2 greatly (a)
minimizes this problem [5]. Vddl
Vbias , p
Vin Vin

Vout Vout
Vout Vin
Vin Vout


Figure 3 (a) Static driver with reduced supply

Vbias ,n voltage. (b) All-NMOS driver with reduced supply

Figure 2 Current-mode driver with center-tapped

source termination.
C. DC-Coupled Receiver D. AC-Coupled Receiver
I-R drops on PCB traces may cause the AC coupling allows for far greater common-
absolute ground reference voltage of chips on the mode range that is limited, in the ideal case, only
same PCB to vary across the board. For this reason, by the breakdown voltage of the on-chip coupling
DC-coupled receivers must be able to accept a capacitors. This approach has been used to realize a
range of common-mode input levels. For example, 1.8V receiver, fully compatible with the LVDS
a typical LVDS receiver shown in Fig. 4 consists standard [11]. This design used a passive biasing
of a PMOS differential pair with an infinite network to set the DC common-mode voltage of
differential impedance load [9]. PMOS inputs are the input devices, but left the AC common-mode
chosen over NMOS input because of the need to voltage to vary with the input. This is undesired
accept common-mode input voltages that can because high frequency noise may drive the input
approach zero specified by the standard. Yet this devices beyond their allowed common-mode input
circuit violates the LVDS standard because the range.
PMOS devices enter the triode region, and Fig. 5 shows the simplified schematic of
consequently lose significant gain, for common- another receiver of this type with an active
mode input levels that approach zero. common-mode biasing circuit [12]. It comprises of
An approach to increase the common-mode a common-mode rejection/stabilization circuit
input range is to combine the PMOS input followed by a latch with a restricted voltage swing.
differential pair with an NMOS input differential Note that termination resistors have been omitted
pair to form a rail-to-rail input stage, and sum the in the diagram but are present in the actual circuit.
currents in a later stage to produce either a fully The common-mode rejection circuit consists of
differential [10] or a single-ended output [5]. NMOS and PMOS infinite differential impedance
Because of the need to have bias currents in both loads connected in parallel. Analysis shows that the
PMOS and NMOS input devices, this approach is common-mode circuit is effectively a parallel
likely to consume twice the power of a single connection of eight diode-connected MOSFETS,
polarity input stage. However, it may be possible to resulting in very low common-mode impedance.
employ an adaptive biasing scheme in which bias On the other hand, the differential half-circuit (top
currents are adjusted by a feedback loop depending or bottom half) is the parallel connection of two
on the common-mode input voltage to minimize diode-connected transistors to two cross-coupled
current wastage. If rail-to-rail capability is not transistors, with the cross-coupled transistors
mandatory, a folded-cascode input stage in which forming a negative impedance that cancels that of
the drains of the input devices are so biased such the diode connected transistors, resulting in very
that the devices remain in the forward active-region high differential-mode impedance. This connection
during extreme input excursions can be employed effectively rejects common-mode signals at all
[6]. frequencies while passing differential-mode
signals. Apart from acting as a latch, the latch
serves to limit the excursion of the differential
voltage between nodes n1+ and n1− . Without the
latch, the impedance between those nodes is
infinite, so that the voltage across them is
inherently unstable. The latch limits the maximum
differential voltage to a manageable value. The
coupling capacitors have capacitance on the order
of the gate capacitance and thus have a minimal
impact on the termination impedance.
The authors claim a DC common-mode input
range of ±690V for a BiCMOS implementation
that achieves 8 Gb/s operation. In practice,
however, this common-mode range cannot be fully
exploited due to the need to limit ESD stress on the
Figure 4 DC-coupled receiver with infinite termination resistors with ESD protection diodes. It
impedance load. has been observed that ESD stress on on-chip

P+ P−

Cin+ n1+ icmc icmc nd+
n in

n1− nd−
Cin− N+
icmc N−


Figure 5 AC-coupled receiver with common-mode voltage stabilization circuit followed by a latch.

termination resistors leads to significant increase in

termination impedance deviation due to V. SUMMARY
temperature and process variation with consequent
Several interface circuits have been proposed
impact on signal integrity [13]. To minimize this
effect, ESD protection diodes that limit the input and implemented. The decision to use DC coupled
swing must be included and on-chip resistors must receivers compels the use of current mode drivers.
Additionally, the receiver must meet the common-
be sized properly so that the ESD protection
devices absorb most of the ESD stress. mode input specification and so requires a supply
Despite this practical limitation, this circuit voltage large enough to accommodate the
approach has the advantage that it can be used with headroom needs of the input devices, given the
a minimum supply voltage since there is no common-mode input range. Properly designed
capacitively-coupled receivers, on the other hand,
common-mode signal, while a higher supply
voltage is mandatory for DC coupled receivers as have less headroom needs and thus require less
well as AC coupled receivers lacking adequate supply voltage. This combined with further
reduction in signal swing using a reduced supply
high-frequency common-mode rejection. This
directly translates into energy savings over other driver has the potential to yield quadratic gains in
methods. energy savings.

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