1 2to4 decoder

2 8 to 3 encoder (with and without priority)

3 8x1 MUX and 1X8 DMUX
4 4 bit binary to gray code converter
5 4 bit comparator
6 Full adder using 3 modeling styles
7 SR, D, JK, T FF
8 4-bit binary, BCD counters (syn/asyn reset)
9 FSM

`
 Ex1: 2to4 decoder

 2-To-4 Decoder – Data Flow

module decoder2to4(O, I);

output[3:0]O;
input[1:0]I;

assign O[0] = (!I(1)) & (!I(0));

assign O[1] = (!I(1)) & (I(0));
assign O[2] = (I(1)) & (!I(0));
assign O[3] = I(1) & I(0);

endmodule

 2-To-4 Decoder – Gate Level Model

module decoder2to4 (O, I);

output[3:0]O;
input[1:0]I;

wire nI1, nI0;

not g1(nI1, I[1]);

not g2(nI0, I[0]);

and g3(O[0], nI1, nI0);

and g4(O[1], nI1, I[0]);
and g5(O[2], I[1], nI[0]);
and g6(O[3], I[1], I[0]);

endmodule

 2-To-4 Decoder – Behavioral Model Using Simple Assignment Statement

module decoder2to4(O, I);

output [3:0]O;
input [1:0]I;
 reg [3:0]O;

always@(I)
begin
O[0] = (!I(1)) & (!I(0));
O[1] = (!I(1)) & (I(0));
O[2] = (I(1)) & (!I(0));
O[3] = I(1) & I(0);
end
endmodule

 2-To-4 Decoder – Behavioral Model Using CASE construct

module decoder2to4 (O,I);

output[3:0]O;
input[1:0]I;

reg[3:0]O;

always@(I)
begin
case(I)
2'b00: O = 4'h0;
2'b01: O = 4'h1;
2'b10: O = 4'h2;
2'b11: O = 4'h4;
default: O = 4'h0;

endcase
end
endmodule

 2-To-4 Decoder – Behavioral Model UsingIF statement

module decoder2to4 (O, I);

output [3:0]O;
input [1:0]I;
 reg [3:0]O;

always@(I)
begin
if(I == 2'b00) O = 4’b0001;
else if(I==2'b01) O = 4’b0010;
else if(I==2'b10) O = 4’b0100;
else if(I==2'b11) O = 4’b1000;
else O = 4’b0000;
end

endmodule

Test bench for 2 to 4 decoder

module tb_decoder2to4 (O, I);

wire [3:0]O;
reg [1:0]I;

decoder2to4 DUT (O, I);

initial
begin
I = 2’b00;
#5 I = 2’b00;
#5 I = 2’b00;
#5 I = 2’b00;
#10 $stop;

end

endmodule
 Ex2: 8 to 3 encoder (with and without priority)

Priority Encoder
 Behavioural model using case statement

module priorityenc(I, Y);

input [7:0]I;

output [7:0]Y;

reg [7:0]Y;
always@( I)

casex(I)

7’b1???????: Y = 3’b111;

7’b?1??????: Y = 3’b110;

7’b??1?????: Y = 3’b101;

7’b???1????: Y = 3’b100;

7’b????1???: Y = 3’b011;

7’b?????1??: Y = 3’b010;

7’b??????1?: Y = 3’b001;

7’b???????1: Y = 3’b000;

default : Y = 3’b000;

endcase

endmodule

 Behavioural model using if statement

module priorityenc(I, Y);

input [7:0]I;

output [7:0]Y;

reg [7:0]Y;
always@( I)

if(I[7]) Y = 3’b111;

else if(I[6]) Y = 3’b110;

else if(I[5]) Y = 3’b101;

else if(I[4]) Y = 3’b100;

 else if(I[3]) Y = 3’b011;

else if(I[2]) Y = 3’b010;

else if(I[1]) Y = 3’b001;

else if(I[0]) Y = 3’b000;

else begin

Y = 3’b000;

$display(“error”);

end

endmodule

testbench
module tb_priorityenc;

reg [7:0]I;

wire [7:0]Y;

priorityenc DUT(I, Y);

intial

begin

I = 8’b00000000

#100 $stop;

end

always #3 I = I + 1;

endmodule
Encoder (Without Priority)

 Behavioural model using case statement

module encoder(I, Y);

input [7:0]I;

output [7:0]Y;

reg [7:0]Y;
always@( I)

case(I)

7’b10000000: Y = 3’b111;

7’b01000000: Y = 3’b110;

7’b00100000: Y = 3’b101;

7’b00010000: Y = 3’b100;

7’b00001000: Y = 3’b011;

7’b00000100: Y = 3’b010;

7’b00000010: Y = 3’b001;

7’b00000001: Y = 3’b000;

default : Y = 3’b000;

endcase

endmodule

 Behavioural model using if statement

module encoder (I, Y);

input [7:0]I;

output [7:0]Y;

reg [7:0]Y;
always@( I)

if(I == 7’b10000000) Y = 3’b111;

else if(I == 7’b01000000) Y = 3’b110;

else if(I == 7’b00100000) Y = 3’b101;

else if(I == 7’b00010000) Y = 3’b100;

else if(I == 7’b00001000) Y = 3’b011;

else if(I == 7’b00000100) Y = 3’b010;

 else if(I == 7’b00000010) Y = 3’b001;

else if(I == 7’b00000001) Y = 3’b000;

else begin

Y = 3’b000;

$display(“error”);

end

endmodule

testbench
module tb_ encoder;

reg [7:0]I;

wire [7:0]Y;

encoder DUT(I, Y);

intial

begin

I = 8’b00000000

#100 $stop;

end

always #3 I = I + 1;

endmodule
 EX3: 8x1 MUX and 1X8 DMUX

 8:1 Multiplexer – Data Flow Model

module MUX8to1_df(I, S, Y);

input [7:0]I;
input [2:0]S;
output Y;

assign Y = (I[0] & ((!S[2]) & (!S[1]) & (!S[0]))) | (I[1] & ((!S[2]) & (!S[1]) & (S[0]))) |
(I[2] & ((!S[2]) & (S[1]) & (!S[0]))) | (I[3] & ((!S[2]) & (S[1]) & (S[0]))) |
(I[4] & ((S[2]) & (!S[1]) & (!S[0]))) | (I[5] & ((S[2]) & (!S[1]) & (S[0]))) |
(I[6] & ((S[2]) & (S[1]) & (!S[0]))) | (I[7] & ((S[2]) & (S[1]) & (S[0])));

endmodule

 8:1 Multiplexer – Gate level Model

module MUX8to1_df(I, S, Y);

input [7:0]I;
input [2:0]S;
output Y;

wire NS2, NS1, NS0;

wire [7:0]W;

not g1(NS2,S[2]);
not g2(NS1,S[1]);
not g3(NS0,S[0]);

and g4(W[0],I[0],NS2,NS1,NS0);
and g5(W[1],I[1],NS2,NS1,S[0]);
and g6(W[2],I[2],NS2,S[1],NS0);
and g7(W[3],I[3],NS2,S[1],S[0]);
and g8(W[4],I[4],S[2],NS1,NS0);
 and g9(W[5],I[5],S[2],NS1,S[0]);
and g10(W[6],I[6],S[2],S[1],NS0);
and g11(W[7],I[7],S[2],S[1],S[0]);

or g12(Y,W[7],W[6] ,W[5],W[4] ,W[3],W[2] ,W[1],W[0]);

endmodule

 8:1 Multiplexer – Behavioural Model using simple assignment statement

module MUX8to1_df(I, S, Y);

input [7:0]I;
input [2:0]S;
output Y;
reg Y;

always@(I,S)
Y = (I[0] & ((!S[2]) & (!S[1]) & (!S[0]))) | (I[1] & ((!S[2]) & (!S[1]) & (S[0]))) |
(I[2] & ((!S[2]) & (S[1]) & (!S[0]))) | (I[3] & ((!S[2]) & (S[1]) & (S[0]))) |
(I[4] & ((S[2]) & (!S[1]) & (!S[0]))) | (I[5] & ((S[2]) & (!S[1]) & (S[0]))) |
(I[6] & ((S[2]) & (S[1]) & (!S[0]))) | (I[7] & ((S[2]) & (S[1]) & (S[0])));

endmodule

 8:1 Multiplexer – Behavioural Model using if statement

module MUX8to1_df(I, S, Y);

input [7:0]I;
input [2:0]S;
output Y;
reg Y;

always@(I,S)

if ( S == 3’b000) Y = I[0];
else if (S == 3’b001) Y = I[1];
 else if (S == 3’b010) Y = I[2];
else if (S == 3’b011) Y = I[3];
else if (S == 3’b100) Y = I[4];
else if (S == 3’b101) Y = I[5];
else if (S == 3’b110) Y = I[6];
else if (S == 3’b111) Y = I[7];
else Y = 1’bz;

endmodule

 8:1 Multiplexer – Behavioural Model using case statement

module MUX8to1_df(I, S, Y);

input [7:0]I;
input [2:0]S;
output Y;
reg Y;

always@(I,S)
case(S)

3’b000: Y = I[0];
3’b001: Y = I[1];
3’b010: Y = I[2];
3’b011: Y = I[3];
3’b100: Y = I[4];
3’b101: Y = I[5];
3’b110: Y = I[6];
3’b111: Y = I[7];
default : Y = 1’bz;
endcase

endmodule
  1:8 DeMultiplexer – Data Flow Model

module DMUX1to8_df(I, S, Y);

input I;
input [2:0]S;
output [7:0]Y;

assign Y[0] = (I[0] & ((!S[2]) & (!S[1]) & (!S[0])));

assign Y[1] = (I[1] & ((!S[2]) & (!S[1]) & (S[0])));
assign Y[2] = (I[2] & ((!S[2]) & (S[1]) & (!S[0]))) ;
assign Y[3] = (I[3] & ((!S[2]) & (S[1]) & (S[0])));
assign Y[4] = (I[4] & ((S[2]) & (!S[1]) & (!S[0])));
assign Y[5] = (I[5] & ((S[2]) & (!S[1]) & (S[0])));
assign Y[6] = (I[6] & ((S[2]) & (S[1]) & (!S[0])));
assign Y[7] = (I[7] & ((S[2]) & (S[1]) & (S[0])));

endmodule

 1:8 DeMultiplexer – Gate level Model

module DMUX1to8_df(I, S, Y);

input I;
input [2:0]S;
output [7:0]Y;

wire NS2, NS1, NS0;

not g1(NS2,S[2]);
not g2(NS1,S[1]);
not g3(NS0,S[0]);

and g4(Y[0],I,NS2,NS1,NS0);
and g5(Y[1],I,NS2,NS1,S[0]);
and g6(Y[2],I,NS2,S[1],NS0);
and g7(Y[3],I,NS2,S[1],S[0]);
 and g8(Y[4],I,S[2],NS1,NS0);
and g9(Y[5],I,S[2],NS1,S[0]);
and g10(Y[6],I,S[2],S[1],NS0);
and g11(Y[7],I,S[2],S[1],S[0]);

endmodule

 1:8 DeMultiplexer – Behavioural Model using simple assignment statement

module DMUX1to8_df(I, S, Y);

input I;
input [2:0]S;
output [7:0]Y;
reg [7:0]Y;

always@(I,S)
begin
Y[0] = (I[0] & ((!S[2]) & (!S[1]) & (!S[0])));
Y[1] = (I[1] & ((!S[2]) & (!S[1]) & (S[0])));
Y[2] = (I[2] & ((!S[2]) & (S[1]) & (!S[0]))) ;
Y[3] = (I[3] & ((!S[2]) & (S[1]) & (S[0])));
Y[4] = (I[4] & ((S[2]) & (!S[1]) & (!S[0])));
Y[5] = (I[5] & ((S[2]) & (!S[1]) & (S[0])));
Y[6] = (I[6] & ((S[2]) & (S[1]) & (!S[0])));
Y[7] = (I[7] & ((S[2]) & (S[1]) & (S[0])));
end
endmodule

 1:8 DeMultiplexer – Behavioural Model using if statement

module DMUX1to8_df(I, S, Y);

input I;
input [2:0]S;
output [7:0]Y;
reg [7:0]Y;
 always@(I,S)

if ( S == 3’b000) Y[0] = I;
else if (S == 3’b001) Y[1] = I;
else if (S == 3’b010) Y[2] = I;
else if (S == 3’b011) Y[3] = I;
else if (S == 3’b100) Y[4] = I;
else if (S == 3’b101) Y[5] = I;
else if (S == 3’b110) Y[6] = I;
else if (S == 3’b111) Y[7] = I;
else Y = 8’bzzzzzzzz;

endmodule

 1:8 DeMultiplexer – Behavioural Model using case statement

module DMUX1to8_df(I, S, Y);

input I;
input [2:0]S;
output [7:0]Y;
reg [7:0]Y;

always@(I,S)
case(S)

3’b000: Y[0] = I;
3’b001: Y[1] = I;
3’b010: Y[2] = I;
3’b011: Y[3] = I;
3’b100: Y[4] = I;
3’b101: Y[5] = I;
3’b110: Y[6] = I;
3’b111: Y[7] = I;
default : Y = 8’bzzzzzzzz;
endcase

endmodule
 Ex 4: 4 bit binary to gray code converter

 DATA FLOW MODEL

module bin2gray(B, G);

input [3:0]B;
output [3:0]G;
assign G[0] = B[1] ^ B[0];
assign G[1] = B[2] ^ B[1];;
assign G[2] = B[3] ^ B[2];;
assign G[3] = B[3];
endmodule
 GATE LEVEL MODEL

module bin2gray(B, G);

input [3:0]B;
output [3:0]G;
xor g1(G[0], B[1], B[0]);
xor g2(G[1], B[2], B[1]);
xor g3(G[2], B[3], B[2]);
buf g4(G[3], B[3]);
endmodule

 BEHAVIORAL MODEL USING SIMPLE ASSIGNMENT STATEMENT

module bin2gray(B, G);

input [3:0]B;
output [3:0]G;
reg [3:0]G;
always@(B)
begin
G[0] = B[1] ^ B[0];
G[1] = B[2] ^ B[1];;
G[2] = B[3] ^ B[2];;
G[3] = B[3];
 end
endmodule

 BEHAVIORAL MODEL USING CASE STATEMENT

module bin2gray(B, G);

input [3:0]B;
output [3:0]G;
reg [3:0]G;
always@(B)
begin
case (B)
4’b0000 : G = 4’b0000;
4’b0001 : G = 4’b0001;
4’b0010 : G = 4’b0011;
4’b0011 : G = 4’b0010;
4’b0100 : G = 4’b0110;
4’b0101 : G = 4’b0111;
4’b0110 : G = 4’b0101;
4’b0111 : G = 4’b0100;
4’b1000 : G = 4’b1100;
4’b1001 : G = 4’b1101;
4’b1010 : G = 4’b1111;
4’b1011 : G = 4’b1110;
4’b1100 : G = 4’b1010;
4’b1101 : G = 4’b1011;
4’b1110 : G = 4’b1001;
4’b1111 : G = 4’b1000;
default: G = 4’b0000;
endcase
end
endmodule
  BEHAVIORAL MODEL USING IF STATEMENT

module bin2gray(B, G);

input [3:0]B;
output [3:0]G;
reg [3:0]G;
always@(B)
begin
if (B[1] ^ B[0]) G[0] = 1; else G[0] = 0;
if (B[2] ^ B[1]) G[1] = 1; else G[1] = 0;
if (B[3] ^ B[2]) G[2] = 1; else G[2] = 0;
if (B[3]) G[3] = 1; else G[3] = 0;
end
endmodule

 BEHAVIORAL MODEL USING IF STATEMENT

module bin2gray(B, G);

input [3:0]B;
output [3:0]G;
reg [3:0]G;
always@(B)
begin
if (B == 4’b0000) G = 4’b0000;
else if (B == 4’b0001) G = 4’b0001;
else if (B == 4’b0010) G = 4’b0011;
else if (B == 4’b0011) G = 4’b0010;
else if (B == 4’b0100) G = 4’b0110;
else if (B == 4’b0101) G = 4’b0111;
else if (B == 4’b0110) G = 4’b0101;

else if (B == 4’b0111) G = 4’b0100;

else if (B == 4’b1000) G = 4’b1100;
else if (B == 4’b1001) G = 4’b1101;
else if (B == 4’b1010) G = 4’b1111;
 else if (B == 4’b1011) G = 4’b1110;
else if (B == 4’b1100) G = 4’b1010;
else if (B == 4’b1101) G = 4’b1011;
else if (B == 4’b1110) G = 4’b1001;
else if (B == 4’b1111) G = 4’b1000;
else G = 4’b0000;
end
endmodule

 TEST BENCH

module tb_bin2gray;
reg [3:0]B;
wire [3:0]G;
bin2gray_beh1 DUT(B, G);
intial
begin
B = 4’b0000;

#100 $stop;
end

always #5 B = B + 4’b0001;
endmodule
 Ex 5. Design of 4-bit comparator

module comparator ( a ,b ,equal ,greater ,lower );

input [3:0] a ,b;

output equal, greater, lower ;
reg equal, greater ,lower ;

always @ (a or b)
begin
equal = 0;
lower = 0;
greater = 0;
if (a<b) lower = 1;
else if (a==b) equal = 1;
else greater = 1;
end

endmodule

module comparator ( a ,b ,equal ,greater ,lower );

input [3:0] a ,b;

output equal, greater, lower ;
reg equal, greater ,lower ;
reg x3, x2, x1, x0;

always @ (a or b)
begin
if(a[3] == b[3]) x3 = 1;
if(a[2] == b[2]) x2 = 1;
if(a[1] == b[1]) x1 = 1;
if(a[0] == b[0]) x0 = 1;
equal = x3 & x2 & x1 & x0;

if ((a[3] > b[3]) |(x3 & (a[2] > b[2])) | (x3 & x2 & (a[1] > b[1])) |
(x3 & x2 & x1 & (a[0] > b[0])) )
greater = 1;

if ((a[3] < b[3]) |(x3 & (a[2] < b[2])) | (x3 & x2 & (a[1] < b[1])) |
(x3 & x2 & x1 & (a[0] < b[0])) )
lower = 1;

endmodule
 Test bench for comparator

module tb_comparator ;

reg [3:0] a ,b;

wire equal, greater, lower ;

comparator ( a ,b ,equal ,greater ,lower );

initial
begin
a = 4’b1000;
b = 4’b1000;
#5 b = 4’b0101;
#5 b = 4’b1010;
#100 $finish;
end

endmodule
 Ex 6: Full adder using 3 modeling styles

Half Adder – Data flow model

module ha_df( A, B, SUM, COUT);

input A, B;
output SUM, COUT;

assign SUM = A ^ B;
assign COUT = A & B;

endmodule

Half Adder – Gate level model

module ha_gl( A, B, SUM, COUT);

input A, B;
output SUM, COUT;

xor g1(SUM, A, B);

and g2(COUT, A, B);

endmodule

Half Adder – Behavioral Model using simple assignment statements

module ha_beh1( A, B, SUM, COUT);

input A, B;
output SUM, COUT;

always@(A, B)
begin
SUM = A ^ B;
COUT = A & B;
end
endmodule

Half Adder – Behavioral Model using case statements

module ha_beh_case( A, B, SUM, COUT);

input A, B;
output SUM, COUT;
wire [1:0] X = {A, B};

always@(X)
begin
case(X)
2'b00: begin
 SUM = 0;
COUT = 0;
end

2'b01: begin
SUM = 1;
COUT = 0;
end

2'b10: begin
SUM = 1;
COUT = 0;
end

2'b11: begin
SUM = 0;
COUT = 1;
end

default: begin
$display ("error");
SUM = 0;
COUT = 0;
end
endcase
end
endmodule

Half Adder – Behavioral Model using if statements

module ha_beh_if( A, B, SUM, COUT);

input A, B;
output SUM, COUT;
wire [1:0] X = {A, B};

always@(X)
begin
if(X==2'b00)
begin SUM = 0; COUT = 0; end
else if(X==2'b01)
begin SUM = 1; COUT = 0; end
else if(s==2'b10)
begin SUM = 1; COUT = 0; end
else
begin SUM = 0; COUT = 1; end
end
end

endmodule

Full Adder – Data flow model

module fa_df( A, B, CIN, SUM, COUT);

input A, B, CIN;
output SUM, COUT;

assign SUM = A ^ B ^ CIN;

assign COUT = A & B | B & CIN | A & CIN;

endmodule

Full Adder – Gate level model

module fa_gl( A, B, CIN, SUM, COUT);

input A, B, CIN;
output SUM, COUT;

wire X1, X2, X3;

xor g1(SUM, A, B, CIN);

and g2(X1, A, B);
and g3(X2, B, CIN);
and g4(X3, A, CIN);
or g5(COUT, X1, X2, X3);

endmodule

Full Adder – Behavioral Model using simple assignment statements

module fa_beh1( A, B, CIN, SUM, COUT);

input A, B, CIN;
output SUM, COUT;

always@(A, B, CIN)
begin
SUM = A ^ B ^ CIN;
COUT = A & B | B & CIN | A & CIN;
end

endmodule

Full Adder – Behavioral Model using case statements

module fa_beh_case( A, B, CIN, SUM, COUT);

input A, B, CIN;
output SUM, COUT;

wire [2:0] X = {A, B, CIN};

always@(X)
begin
case(X)
 3'b000: begin
SUM = 0;
COUT = 0;
end

3'b001: begin
SUM = 1;
COUT = 0;
end

3'b010: begin
SUM = 1;
COUT = 0;
end

3'b011: begin
SUM = 0;
COUT = 1;
end
3'b100: begin
SUM = 1;
COUT = 0;
end

3'b101: begin
SUM = 0;
COUT = 1;
end

3'b110: begin
SUM = 0;
COUT = 1;
end

3'b111: begin
SUM = 1;
COUT = 1;
end

default: begin
$display ("error");
SUM = 0;
COUT = 0;
end
endcase
end
endmodule

Full Adder – Behavioral Model using if statements

module fa_beh_if( A, B, CIN, SUM, COUT);

input A, B, CIN;
output SUM, COUT;
 wire [2:0] X = {A, B, CIN};

always@(X)
begin
if(X==3'b000)
begin SUM = 0; COUT = 0; end
else if(X==3'b001)
begin SUM = 1; COUT = 0; end
else if(s==3'b010)
begin SUM = 1; COUT = 0; end
else if(X==3'b011)
begin SUM = 0; COUT = 1; end
else if(X==3'b100)
begin SUM = 1; COUT = 0; end
else if(X==3'b101)
begin SUM = 0; COUT = 1; end
else if(s==3'b110)
begin SUM = 0; COUT = 1; end
else
begin SUM = 1; COUT = 1; end
end
end

endmodule