Timing Constraints

WASEL: PCSEL:
tldr; Distinguishes between exceptions and tldr; Distinguishes between exceptions types
non-exceptions. OR between branch types.
WASEL controls what enters the WA port of PCSEL controls what goes into PC.
Reg. File.

D-Latch Flip flop

If Z ? 1 : 0: BEQ
If 0: No exceptions If Z ? 0 : 1: BNE
If 1: Exceptions If 0: All basic ops and LD, LDR & ST
If 2: JMP
If 3: ILLOP
WDSEL: If 4: IRQ
tldr; Distinguishes between the four categories
of branching ops, ALU ops and LD/LDR ops BSEL:
and ST. tldr; Distinguishes between Op operations and
WDSEL controls what goes on the path leading Non-op, then between constant and
to WD port of Reg. File. non-constant Op operations.
BSEL controls what enters port B of the ALU.
If 0: (PC + 4) passes through. Basically all
branching ops.

Sequential Circuit
If 1: Output of ALU passes through. Basically all
ops that involve ALU computations except for
LD/LDR.
If 2: Contents READ from Memory passes
through. Basically only LD and LDR.
If DC: Contents don’t enter WD port of Reg.
File. Only ST.
If 0: contents from RA2 of Reg. File passes
through. Applies for all non-constant ops.
If 1: Literal (SXT(ID[15:0])) passes through.
Applies for all constant ops and LD & ST.
If DC: contents don’t get passed into port B of
ALU. Applies for all other non-op operations.

WERF & MWR (& MOE) and then RA2SEL:

tldr; Uniquely identifies ST.
WERF controls whether something can enter WD port of Reg. File. MWR controls whether something can be
written into Memory. RA2SEL controls what enters RA2 port of Reg. File. MOE controls whether something
can be read from Memory. WERF and MWR values are always inverse of each other and they are always
well-defined for all operations (no “dont-cares”) except for RESET for WERF. This is important for MWR to
ensure we do not make fatal mistakes of erroneously writing into memory. MOE and MWR are also always
inverse of each other for values where MOE are defined.

WERF MWR MOE RA2SEL

If 0: ST If 0: NOT ST If 0: ST If 0: NOT ST. Contents from RB goes
If 1: NOT ST If 1: ST If 1: LD OR LDR through. Applies for all ops where
If DC: RESET If DC: Contents don’t enter memory we need contents from RB
applies for all ops where contents If 1: ST: Contents from RC
don’t go into Memory. If DC: Contents don’t come from
RB or RC, applies for all ops where
we do not need RB/RC contents

ASEL:
tldr; Uniquely identifies LDR. Use this to distinguish LDR from LD.
ASEL controls what enters port A of the ALU.

If 0: contents from RA goes through. Applies for all ops where we need contents of RA in ALU for some
computations
If 1: LDR => contents (PC + 4) + 4*SXT(C) will go to ALU (computation is ‘A’ which basically means return the
same thing since we do not actually want to change anything with it. If we don’t want to change anything,
why place this selector before ALU and not before Memory? The reason is because if we put it before
Memory, then contents from LD and ST will have to pass through 2 muxes before it can get to Memory,
which slows down the entire process)
If DC: contents don’t get passed into ALU, applies for all ops where no computations are done by ALU

1. Number of pages in page table (”how many entries”) =

2 to power of (number of VPN bits)

2. Number of pages in physical memory =

2 to power of (number of PPN bits)

3. Size of page (”how large”) = 2 to power of (number of PO bits)

3.5. Bit-length of page = number of page bits + 2

4. Size of page map (”how large”) = number of pages in page

table * bit-length of page