Fabrication Process

1
of CMOS ICs - 2
Lecture# 09
VLSI Design
 2 Lithography
 Chemical-Mechanical Polishing
 Consider a scenario
 Where Silicon dioxide layer is deposited on polysilicon pattern
 The top surface would have hill, due to underlying polysilicon gate
 If we deposit metal layer on top, it will follow the surface contour
 May also be uneven in thickness
 Also lead to breakage due to uneven structure
 This non-planaried surfaces are planarized using
 Chemical-Mechanical Polishing (CMP), involves
 Chemical etching and mechanical polishing to produce plane surfaces

Deposited oxide

CMP

substrate substrate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 3 Lithography
 Chemical-Mechanical Polishing
 We have studied
 The roles of patterns in forming a circuit (or network)
 How layers can be created using physical and chemical process
 Now, we will study
 How the patterns are created in a CMOS IC
 Using the physical and chemical processes we have studied earlier

 Photolithography is a technique which

 Allow us to create patterns of different layers on the surface of a chip
 Done by projecting optical shadow of the pattern on the surface of
chip
 Then employing photographic-type techniques to transfer the pattern
 Similar process is used for PCBs with lower resolutions

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 4 Lithography
 Reticle
 Lithography is continuously evolving to meet smaller process sizes
 The process starts with desired pattern definition for a layer (on
CAD)
 The pattern is transferred onto a high quality glass with metal
(chromium)
 This is called reticle or mask (5 to 10 times the size of the chip)
 The reticle contains two types of regions (see figure)
 Transparent (no metal)
 Opaque (covered with metal)
 The reticle is kept above the surface of the chip
 When the light falls on the reticle
 It projects a shadow on the surface of the chip below

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 5 Lithography
 Pattern Transfer
 In order to transfer the pattern of the reticle on the surface of the
chip
 We coat the surface with a light sensitive liquid plastic called photoresist
 Photoresist is sprayed onto the surface of a spinning wafer
 The spinning evenly coats the entire surface of the wafer with the resist
 With exception at the edges, called beading effect

Photoresist spray Photoresist coating

Spinning wafer Edge bead Edge bead

Flat resist

Wafer

(c) Beading effect

Vacuum chuck

(a) Resist application (b) Coated wafer

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 6 Lithography
 Exposure Step

 Photoresist acts like a photographic film and

reacts to ultraviolet (UV)
 UV has high energy photons (short wavelength)
 This is called exposure step
 After exposure the photoresist is developed using a
chemical rinse
 Most VLSI processes used positive photoresists
(provide high resolution)
 A positive photoresist is initially insoluble,
 and when exposed to UV becomes soluble
 Non-exposed regions are hardened

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 7 Lithography
 Photoresist Development

 Positive photoresist becomes soluble where exposed to UV

 Through the transparent region on the reticle

 After exposure the photoresist layer is developed with a chemical rinse

 The exposed photoresist is removed, exposing the wafer
 Negative photoresist has opposite characteristics
 Shielded regions are soluble, exposed are hardened
 The hardened resist protects underlying regions from the etching process

Ultraviolet Light Ultraviolet Light

Reticle Reticle

Hardened
Exposed resist photoresist layer
Unexposed
Is soluble
resist
Is hardened
Photoresist Photoresist
Wafer Wafer Wafer

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 8 Lithography
 Etching Process

 Consider a scenario, where we want to create pattern of oxide layer

 The whole wafer is covered with oxide layer
 The whole oxide layer is covered with photoresist
 UV patterned exposure is performed using reticle and photoresist is developed

 The surface is subjected to usually a reactive-ion etch (gaseous plasma)

 That removes the exposed layer (oxide or other), photoresist protect unexposed
surface.

 This process can pattern any layer (almost)

 Creating active regions requires slight variation in the process

Hardened
photoresist layer
Patterned oxide layer

Oxide
layer
Wafer Wafer

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 9 Lithography
 Creating Active Regions
 In order to create an active region (doped n+/p+ regions)
 Oxide layer is grown on wafer and patterned (by etching) using lithography
 The new structure is exposed to ion-implantation to create doped regions
 The oxide layer protects the underlying silicon from the incoming beam

 Consider the below example where after etching of the oxide layer
 the exposed wafer is doped with Arsenic atoms, to create n+ regions
 The dopants can only enter silicon where oxide is etched away
 the created n+ regions are slightly larger than oxide openings
 Due to dopant diffusion during the annealing process, called lateral doping (limits
resolution)

Arsenic
ions

n+ n+
Substrate Substrate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 10 Lithography
 Creating Multiple Chips

 It should be noted that the lithographic process discussed here

 Is being perform on one of the die sites in the wafer
 This process repeats on each site in the wafer using step-and-repeat
process
 A wafer stepper is an apparatus that accurately moves (in steps) the wafer to
expose next site

 This sequence produces wafer with a large number of identical sites

 Also, some locations are called sites containing test structures and circuits
 A test site contains MOS capacitors, doped regions, MOSFETs and simple
circuits

 Wafer probes are thin metallic probes that are used to examine the test
sites
 To verify that the fabrication process is progressing correctly Wafer
 Multiple site ensures die site
 uniformity of various parameters across the wafer test site

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

11 Lithography
 Clean Rooms

 The lithographic process is very sensitive to dust particles

 It a dust particle lands on the photoresist,
 it will interfere with the exposure and development, leading to defects

 A dust particle landing on the reticle

 May corrupt the pattern transfer (as it will be imaged down)

 Dust particles ultimately decrease yield considerably in submicron

processes
 A clean room environment uses High-Efficiency Particulate Air (HEPA)
 HEPA filters are 99.97% effective in removing particles of diameter 0.5 μm
 A class X clean room (in British system) means
 There are less than 𝑋 paritlces/ft of diameter 0.5 μm
 A class M Y clean room (in metric system) means
 There are less than 10 paricles/m of diameter 0.5 μm

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

12 Lithography
 Clean Rooms Contd…

 Modern clean rooms have class 1 or better

Class 0.1 𝛍𝐦 0. 𝟐 𝛍𝐦 0. 𝟑 𝛍𝐦 0. 𝟓 𝛍𝐦 0. 𝟓 𝛍𝐦
1 3.5 10 7.5 3.0 1.0
10 3.5 10 7.5 10 3.0 10 1 10
100 7.5 10 3.0 10 1 10
1000 1 10 7.0
10000 1 10 70 10

 Workers must take air shower and wear special suits (bunny suits)
 Before entering a clean room
 Lithographic areas are lit by yellow light as it does not effect
 The UV-sensitive photoresist
 A thin layer of large transparent plastic is place above (well above)
 The reticle to keep dust particles from reaching the reticle surface

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

13 The CMOS Process Flow

 We will now study steps in a p-epitaxial layer

standard silicon CMOS process
 Understand of the process is of p-substrate
importance to every VLSI designer
 The starting point is a p+ wafer with (a) Starting wafer with epitaxial layer
a thin p-type epitaxial layer on top
 The epitaxial layer is created by
dropping silicon atoms onto n‐well
heated wafer p‐epitaxial layer

 Forms high quality crystal layer for (b) Creation of n-well in p-epitaxial layer
transistor (source and drain regions
only) Silicon Nitride

 The wafer itself acts as the

substrate, not shown explicitly in
the figures n‐well
p‐epitaxial layer
 Secondly, the n-well region is
formed (defines location of (c) Active area definition using nitride/oxide
pMOSETs)

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

14 The CMOS Process Flow

 Thirdly, electrical isolation is

provided using field oxide (FOX)
 Between active regions (which
are not formed yet)
n‐well
 The future active regions are p‐epitaxial layer
covered in
(d) Silicon etch
 Oxide (to reduce mechanical
stress on the crystal surface) and FOX FOX FOX FOX
 Nitride for defining silicon etch
regions
n‐well
 Fourthly, etching is performed p‐epitaxial layer

 Removes oxide and silicon from (e) Field oxide (FOX) growth
wafer
 After etching the gaps are filled
with glass insulation called field n‐well
oxide p‐epitaxial layer

 Once FOX is grown, the (f) Surface preparation

nitride/oxide pattern is removed
Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad
15 The CMOS Process Flow

 MOSFETs are now formed using n‐well

a self-aligned gate process p‐epitaxial layer

 The gate oxide layer is (a) Gate oxide growth

deposited
Poly Poly
 Specified by 𝑡

 The gates are created,

n‐well
 Using polysilicon layer pattern p‐epitaxial layer

(b) Poly gate deposition and patterning

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

16 The CMOS Process Flow
 Implant mask of pSelect is used
to create p+ regions of pMOS
 Using ion-implantation (and
Boron implant
annealing)
 The ions pass through thin layer
of gate oxide to form doped Resist

regions
n‐well
p‐epitaxial layer
 No doping is performed under
p+ implants
(c) pSelect mask and implant
 Polysilicon gates as it absorbs
ions Arsenic implant

 This is why “self-aligned gate”

Resist
 A similar procedure creates
 n+ regions for nMOS using n‐well
p‐epitaxial layer
nSelect mask
n+ implants
 Silicide gates are created by (d) Poly gate deposition and patterning
 Layering polysilicon with a
refractory metal
Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad
17 The CMOS Process Flow

 For adding interconnects

 We cover the surface with CVD
oxide CVD
Oxide
 Followed by CMP
n‐well
 Active contacts are added p‐epitaxial layer

CVD oxide layer

 By etching holes in the CVD
oxide
 Filled with a metal (like
tungsten) n‐well
p‐epitaxial layer

 The first layer of metal is added Adding active contacts

 using metal1 mask

 Additional layers of metals can
be added
n‐well
 Using the same process p‐epitaxial layer

 First add vias and then metal Metal1 coating an patterning

layer
Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad
18 The CMOS Process Flow

 After all the layers are added

 The entire chip is covered with
Metal Pad
overglass material
 Like Silicon nitride to provide protection
to chip
 Silicon Nitride is an insulator Overglass cut

 So vias are etched to gain electrical

access to the chip
 Requires and another masking step Wire
Overglass

 Usually the vias connect the

underlying chip pads
Bond
 to a bonding pad (in pad frames)
 External wires are then sold to connect Metal bonding pad
bonding pads to package pins
SiO2 Vias

To Silicon

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

19 Design Rules (1/7)

 Physical design involves creating mask layers

 Using CAD tools to create polygons of various layers (colors and
patterns)
 The drawing area is based on a reference grid
 The distance between points representing a specific length

 The IC fabrication process has limited accuracy

 Which must be taken into account while creating a layout
 E.g a lithographic stepper unit allows linewidths of 0.25 μm
 Will not work on 0.18 μm.

 Also, the etching process has its limitations

 Moreover, some restrictions are due to
 electrical characteristics and physical restrictions at the silicon level

 The above mentioned restrictions translates to Design Rules, which

are
 A set of geometrical specification that dictate design of layout masks

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

20 Design Rules (2/7)
 A design rule set provides numerical values for
 Minimum dimensions, line spacings and other geometrical quantities
 That are derived from limitation of a specific processing line.
 The design rules must be obeyed to insure functional structures
 E.g design rules for polysilicon lines wp wp

 𝑤 = minimum width of a poly silicon line

sp‐p
 𝑠 = minimum poly-to-poly spacing
 These are numerical values in DR listing
 Violations may lead to failure
 Every layer will have similar rules 𝑤 = ??
= minimum width specification 𝑠 = ??

poly

poly
 𝑤
 𝑠 = minimum spacing value
 𝑑 = generic minimum distance

All design rules specifications have units of length (e.g. μm)

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

21 Design Rules (3/7)

 Consider a process defined rules for poly are

 𝑤 0.25 μm , 𝑠 0.425 μm

 The layout grid in CAD tools must be calibrated

 To accommodate the necessary resolution (like 0.025 μm)
 Is 0.05 μm or 0.01 a valid resolution?
 Design rules changes
 From process to process (foundry change)
 As technology advances
 The design rules are acquired from the foundry (for a process)
 And fed in to CAD tools to ensure that rules are observed during design

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

22 Design Rules (4/7)
 Lambda Design Rules

 The customer base is wide and varied (multiple process at a

foundry)
 The foundry provide a simpler set of rules
 which can be scaled for different processes, called lambda design rules
 Based on reference metric 𝜆, all widths, spacing and distance are
 Value 𝑚𝜆
 Where 𝑚 is a multiplier (e.g 𝑤 2𝜆 and 𝑠 3𝜆)
 𝜆 is related to physical length (e.g 𝜆 0.15 μm)
𝑤 2 0.15 μm 0.30 μm

𝑠 3 0.15 μm 0.45 μm

 For submission of design to a different process

 Simply change the 𝜆, and, the relative dimensions remain the same

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 23 Design Rules (5/7)
 Classification

 Design rules may be classified into four main types

 Minimum width
 Minimum spacing
 Surround
 Extension
 Surround rules are enforced when a feature is placed within a
feature
 In PMOS, placing p-select within n-well
 In active contact, contact surrounded by active region (and metal)
 Extension requires a portion of pattern to be extend beyond edged
 Extended poly beyond active regions in MOSFETs

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

24 Design Rules (6/7)
 Misalignment

 A potential problem with the active contact misalignment

 May short the active contact and p-substrate (n+ and p-substrate)
 Resulting in non-functional chip

n+ border Metal plug

+ n+
n
short
p-substrate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 25 Design Rules (7/7)
 Extension

 Extension type design rules also avoid misalignment issues

 Consider the formation of a self-aligned nMOS
 Donor dopant does not reach under the gate (poly)
 Misalignment may short
 Drain and source

poly
poly

n+ n+

dpo
Active Drain-source short

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

26 Assignment No 2, Q. No. 2
Question:
Show complete steps of CMOS process flow to design an inverter.

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad