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VLSI Design
Lecture# 05
VLSI Design
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Class Schedule

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 3 Lab 02 Discussions

Pre Lab Tasks

 Design a full adder using basic logic gates and verify the functionality
using truth tables.
 Design a transmission gate and verify its functionality using DSCH3 tool.
Create a schema symbol for the gate which will be used for in-lab
tasks.

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 4 Lab 02 Discussions

In Lab Task - 1
 Design a half adder using CMOS schematic of basic logic gates (XOR,
AND).
 Verify the functionality of half adder using DSCH3 tool with all possible
inputs.
 Make a schema symbol for half adder.
 Use the symbols to build schematic for full adder which include
half_adder and OR gate.
 Use complementary nMOS and pMOS for schematic of basic gates.
 Design your schematic in DSCH3 tool.
 Simulate the design and verify the functionality of the design.
 Make the verification table which includes all the inputs and
corresponding outputs for the schematic.
 Use space below for Task 1, show your results to your instructor before
you move on.

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 5 Lab 02 Discussions

In Lab Task - 2
 Design an XOR gate using TG and CMOS transistors. Show your
schematic to instructor before you continue.
 Verify the functionality of XOR gate using DSCH3 tool with all possible
inputs.
 Make the verification table (in space given below) which includes all
the inputs and corresponding outputs for the schematic.

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 6 Lab 02 Discussions

In Lab Task - 3
 Design 1-bit Full Adder using Transmission Gates (show your designing
process in space below) and verify its functionality in DSCH3 tool.
 Make a schema symbol for 1-bit full adder.
 Create 4-bit full adder/subtractor by using schema symbol made in
last step (show schematic below).

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

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Assignment No 1. Part 3
Make Following Logic Gates using Transmission Gate
logic. Verify the functionality of Logic Gates using truth
table mentioning state (Open/Close) of all the
transistors.
AND
NAND
OR
NOR

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

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Time for Quiz No 1

Arrange Yourself

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad