Elements of

1
Physical Design
Lecture# 10
VLSI Design
 2 Elements of Physical Design
 Basic Concepts

 We have studied the basic fabrication sequence

 Now we will look into translating logic circuits on to silicon
 Called physical design
 Physical design involves observing the minimum size specification
 Usage of CAD tools to describe silicon masks So far we were
ignoring dimensions
 In physical design step of VLSI design process in layout
 Schematic diagrams are carefully translated in to sets of geometric
patterns
 That are used to define the on-chip physical structures
 Every layer in CMOS have a distinct pattern
 Group of geometrical objects (called polygons), making n-vertex shapes

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 3 Elements of Physical Design
 Basic Concepts

 The layers are electrically equivalent to

the circuit diagram
 So far we have discussed how transistor
networks
 Establishes a logic function
 Another aspect is switching speed
 Which is equally important sometimes
 Complicated to analyze
 In order to analyze, we will find electrical
characteristics of a logic gate
 Depending upon aspect ratios of the
MOSFETs
 As well as parasitic resistance and
capacitances

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 4 Elements of Physical Design
 Basic Concepts

 Dimension of every feature affect the electrical performance of the

circuit
 In VLSI switching speed of some gates will be critical
 Especially those in long complex logic paths
 We will start discussing basic circuit layout
 And slowly move on to high-speed circuits

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

5 Role of Layout Editor
 Physical design is done using a software called layout editor
 Allows a designer to specify shape, dimensions and placement of
polygons
 Complex logic functions are implemented by
 First designing simple gates and storing them (as cells) in the software
library
 Library cells are building blocks of a complex circuit (Like NAND2, NOR2, NOR3
and MUX8 etc.)

 Secondly, Instantiating the cells (creating copies of the cells in the library)
 A copy of a cell is called an instance

 Thirdly, connecting the basic building blocks to form complex circuit

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

6 CAD Toolsets
 The layout must be accurate representation of the logic network
 Along with achieving fast speed by using minimum area
 Small changes in the polygon shapes causes changes in
 In electrical characteristics of the circuit (may or may not be significant)

 A designer with experience is able to find trouble spots

 Using the instincts and simulation results

 Physical design using CAD tools simplifies the designing and

verification
 CAD toolsets are usually combination of software packages
 Each software with its own use in the VLSI design hierarchy

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

7 CAD Toolsets
 Let us concentrate on the CAD tools related to physical design
 Layout Editor
 A GUI for drawing multiple layer polygons (each layer with a separate
pattern or color)

 Design Rule Checker (DRC)

 Ensures that the design can be fabricated within the limits of the
manufacturing process

 Extraction, converts the layout into netlist (used for spice simulation)
 Netlist is an equivalent electrical network including parasitic and
geometrical parameters.

 Layout vs. Schematic (LVS), compares layout with schematic

 Matches nodes, connections and elements etc.

 Other tools: Place and route, electrical rule checker (ERC) & spice
simulator

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 8 Layout of Basic Structures
 Layers and Design Rules
0. Start with a p-
substrate
 A generic masking sequence for a chip is 1. n-Well
2. Active
 oxide layers are implied (between conducting layers)
3. Poly
 Details may vary, slight modification may be needed 4. pSelect
5. nSelect
 We will discuss how to design structures 6. Active Contact
 using the CMOS layers 7. Poly Contact
8. Metal1
 Keeping design rules in mind 9. Via1
 Relevant design rules will be introduced for each structure 10. Metal2
11. Overglass
 Every feature (on every layer) have design rules
 Minimum width, 𝑤 (minimum width of a polygon)
 Minimum spacing, 𝑠 (minimum edge-to-edge distance between two
polygons)
 The numerical values of 𝑤 and 𝑠 depends on the layer

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 9 Layout of Basic Structures
 Drawn and Effective Values

 Design rules defined for the mask

level (reticle).
 The actual fabricated structure will
have different dimensions
w
 Due to limitation of the fabrication
process (lateral etching and doping
etc.)
 We refer to layout (mask or in layout
editor) sizes as the drawn values
s
 and the fabricated values as
effective or final values

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

10 Layout of Basic Structures
 n-Well

 An n-well is required at every location where a pMOS is to created

 The drawings define two rules
 𝑤 = minimum width of an n-well mask feature
 𝑠 = minimum edge to edge spacing of adjacent n-wells
 We can often merge adjacent n-wells
 n-well is to be connected to VDD, when used for pMOS

n-well n-well n-well n-well

snw-nw

n-well n-well

wnw wnw
Cross‐section Mask set

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

11 Layout of Basic Structures
 Active Areas

 Silicon devices are built on active areas of the substrate

 An active area is flat and provides access to the top of the wafer

FOX Active Active

Active

sa-a
wa
Silicon substrate
Cross‐section Active patterns

 Where there is not an active region, exists FOX for isolation

 FOX NOT Active
 FOX Active Surface

 Design rules for Active

 𝑤 = minimum width of an Active feature
 𝑠 = minimum edge to edge spacing of adjacent Active mask
polygons
Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad
 12 Layout of Basic Structures
 Doped Silicon Regions (n+)

 N-diffusions and p-diffusions form n+ and p+ regions

 Active regions, where either accepter or donor nSelect
doping is done
Active
 n+ region is formed where Active and nSelect
overlaps n+

 n nSelect ⋂ Active
Silicon substrate
 Design rules
Cross‐section
 𝑤 = minimum width of an Active feature
 𝑠 = minimum Active-to-nSelect spacing nSelect
sa-n

wa

sa-n
Active
Mask set

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 13 Layout of Basic Structures
 Doped Silicon Regions (p+)

 p+ regions are formed similarly

pSelect
 Only n-well is required for the p+ to be formed Active
 p+ region is where Active, nSelect and n-Well
p+
overlaps
n-well
 p nSelect ⋂ Active ⋂ nWell
Silicon substrate
 Design rules
Cross‐section
 𝑤 = minimum width of an Active feature
 𝑠 = minimum Active-to-pSelect spacing sp-nw pSelect
 𝑠 = minimum pSelect-to-nWell spacing sa-p

wa

sa-p

sp-nw Active

Mask set

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

14
Layout of Basic Structures
 MOSFET
In fabrication process, Poly
 Self-aligned gate MOSFETs are made line is created before n+/p+,
when and block dopants from
 Poly gate completely crosses n+ or p+ reaching underneath
region
𝐿 = Drawn channel length
 A MOSFET require polygon on the poly
mask L
Poly
 Design rules
n+ n+
 𝑤 = minimum width of poly
p-substrate
 𝑠 = minimum poly-to-poly spacing
Cross‐section
 𝑑 = extension of Poly beyond Active L
nSelect L
Poly
 Ensures formation of self-aligned MOSFET
even after some registration error Active
W
 We can say n+ n+ W

 nMOS nSelect ⋂ Active ⋂ Poly Poly

dpo

 n nSelect ⋂ Active ⋂ NOT Poly Masks for nMOS Layout view

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 15
Layout of Basic Structures
 Drawn and Effective Values in MOSFETs

 The critical dimension of MOSFETs are channel length 𝐿 and Width

𝑊.
 The electrical or effective channel length 𝐿 is
 smaller than drawn channel length 𝐿 (due to lateral doping)
 𝐿 𝐿 2𝐿 𝐿 Δ𝐿
 where 𝐿 is active overlap under gate from either side

 The effective channel width 𝑊 is

 Smaller than drawn channel width, due to field oxide growth called
active area encroachment
 𝑊 𝑊 Δ𝑊

 Transistor aspect ratio

 For accurate simulation results, CAD tools approximate effective values

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

16 Layout of Basic Structures
 Active Contacts and Metal1

 Active contact is a cut in Ox1 which connects Active (n+/p+) to

Metal1
 Dimensions of an Active contact Usually 𝑑 𝑑 , 𝑑 ,
results in a square
 𝑑 , = vertical size of the contact contact
 𝑑 , = horizontal size of the contact

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

17 Layout of Basic Structures
 Active Contacts and Metal1

 Design rules to observe

 𝑤 = often specified minimum of exact width of an active contact
 𝑠 = minimum spacing between Active and Active contact
 𝑠 = minimum spacing between Metal1 and Active contact
 𝑤 = minimum width of a Metal1 line
 Each contact offers a resistance 𝑅 contact resistance Ω
 Multiple contacts (𝑁) are added to reduce resistance 𝑅 , 𝑅

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 18 Layout of Basic Structures
 Active, Active Contacts and Poly

Sm-pc

Poly Contact

dpc

Sm-m

Cross Over

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 19 Layout of Basic Structures
 Series and Parallel MOSFETs

 For series-connected MOSFETs, we can compact space

 Merging drain and source regions
 Placing two gates close together (shrinking the merged region)
 𝑠 , minimum Poly-to-Poly design rule applies

 For parallel-connect MOSFETs, we can compact space

 Merging drain and source regions
 Placing two gates close together (but merged regions have active
contacts)
 𝑠 𝑑 2𝑠 design rule applies
 minimum Poly-to-Active contact and active contact size

 For series-connected MOSFETs of unequal widths

 𝑠 applies

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

20 Layout of Basic Structures
 Series Connected MOSFETs

Sp-p

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

21 Layout of Basic Structures
 Parallel Connected MOSFETs

Sg-g

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 22 Layout of Basic Structures
 Series Connected MOSFETs with Different Widths

W2

W1

Sp-a Sp-a

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad