3.155J/6.

152J Lecture 2:
IC Lab Overview

Massachusetts Institute of Technology

02/09/2004

Slides prepared by Professor Martin Schmidt

Outline
„ The MOSFET Structure
„ Semiconductor Doping
„ The MOSFET as a Switch
„ A MOSFET Process
„ The MOS Capacitor Process
„ Reading Assignment
„ Plummer, Chapter 1

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 2

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 MOSFET
G

S D
D

Gate G
Oxide
Source Drain

Bulk
S

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 3

N-Channel MOSFET
+VG
0V +VD

Gate
Oxide
n-type n-type

p-type

0V

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 4

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 Silicon bond model: electrons and holes
„ Electronic structure of
Si is Column IV of the periodic table:
silicon atom:
„ 10 core electrons (tightly
bound)
„ 4 valence electrons (loosely
bound, responsible for most
of the chemical properties)
„ Other semiconductors:
„ Ge, C (diamond form)
„ GaAs, InP, InGaAs,
InGaAsP, GaN, ZnSe, CdSe,
CdTe (on the average, 4
valence electrons per atom)

(From Howe & Sodini)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 5

Silicon is a Semiconductor—
„ Silicon is a crystalline
material
„ Long range orientational and
positional order
„ Two types of “carriers”
(mobile charge particles):
„ electrons and holes

„ Carrier concentrations can be

controlled over many orders
of magnitude by addition
“dopants”
„ selected foreign atoms

„ Carrier concentrations can be

controlled electrostatically

(From Howe & Sodini)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 6

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 A Word About Doping….
Silicon has four valence electrons
It covalently bonds with 4 adjacent atoms in the crystal lattice

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 7

Intrinsic Semiconductor
Increasing Temperature Causes Creation of Free Carriers
1010 cm-3 free carriers at 23C (out of 2x1023 cm-3)
Intrinsic Conductivity

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si
+
Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 8

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 N-type Doping
Phosphorus has 5 valence electrons
‘Donates’ one conduction electron – n-type
Our substrate has 1015 cm-3 phosphorus (1 in 108)

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si P Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 9

P-type Doping
Boron has 3 valence electrons
‘Accepts’ one electron from lattice
Creates a ‘hole’ – p-type

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si B Si Si Si Si

Si Si Si Si Si Si Si Si Si
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 10

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 Counter Doping
The addition of one more B than P causes the
doping type to change from n-type to p-type

Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si

Si Si Si Si P Si Si Si Si

Si Si Si Si B Si Si Si Si

Si Si Si Si Si Si Si Si Si
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 11

Counter Doping Process

n-type (1015 cm-3)

Implant Boron
and Anneal
1015 Concentration

p-type (>1015 cm-3)

n-type (1015 cm-3)

Depth

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 12

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 P/N Junction
+ - + - + - + + - + - + - +
- + - + - + - - + - + - + -
+ - + - + - + + - + - + - +
- + - + - + - - + - + - + -
+ - + - + - + + - + - + - +
- + - + - + - - + - + - + -
+ - + - + - + + - + - + - +

p-type n-type
Depletion Region

- +
- +
- +
- +
p-type - + n-type

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 13

P/N Junction - Diode

I - + I
- +
- +
- +
p-type - + n-type
V
+ V -

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 14

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 N-Channel MOSFET Operation

0V +VG
0V +VD

+++++++++++++++++
Oxide
----------------
n-type n-type

p-type

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 15

MOSFET as a Switch

0V +VG
0V +VD 0V +VD
Gate Gate
Oxide Oxide
n-type n-type n-type n-type

p-type p-type

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 16

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 Microfabricated Devices
„ Starting Material
„ Single crystal silicon
„ Mask Set
„ Contains x,y info
(Top View)
„ Process Sequence
„ Contains z info
(Cross Section)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 17

Sample Mask Set

„ Four Levels (Masks)
Mask Definition

1 Active Area

2 Polysilicon

3 Contact Cuts

4 Aluminum

Transistor Diffusion Polysilicon Metal

(MOSFET) Resistor Resistor Resistor
Spring 2005 (Diode) 3.155J/6.152J – Lecture 2 – Slide 18

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 Our Process
p-channel

„ Poly Gate pMOS

Metal-Oxide-Semiconductor (MOSFET)
Polycrystaline Silicon
polysilicon
Source Gate Drain

-------
p +++++++ p

n-silicon
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 19

Starting Material
„ 6” (150mm) Diameter Silicon Wafer
„ 30 +/- 1 mil thick (~750 µm)
„ n-type (doped with Phosphorus)
„ 1.5 Ω-cm resistivity (1015 cm-3 Phos)
„ <100> crystal orientation

Minor Flat
<100>

Major Flat

Spring 2005
<110> 3.155J/6.152J – Lecture 2 – Slide 20

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 FET Process Steps
1. Characterize the wafer (resistivity, orientation, and type)
2. Grow 5000A ‘Field Oxide’ for device isolation

Typically at 800-1100C for 1 hour in O2 or steam

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 21

Process Steps
3. Pattern Active Area (Mask #1)
Coat with
photoresist

Expose
Mask

Develop

Etch*

Strip resist

*Wet etch
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 22

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 Process Steps

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 23

Process Steps
4. Grow 500A Gate Oxide

5. Deposit 5000A Polysilicon by LPCVD (low pressure

chemical vapor deposition)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 24

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 Process Steps
6. Pattern Polysilicon (Mask #2)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 25

Process Steps
7. Etch Gate Oxide

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 26

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 Process Steps
8. Ion Implantation of Boron
B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+ B+

9. Drive-In (950C in O2)

Note self alignment

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 27

Process Steps
10. Strip Backside

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 28

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 Process Steps
11. Pattern Contact Cuts (Mask #3)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 29

Process Steps
12. Evaporate Aluminum

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 30

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 Process Steps
13. Pattern Aluminum (Mask #4)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 31

Process Steps
14. Sinter (400C – N2:H2)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 32

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 Process Results
„ The Four Mask Process Yields
„ Resistors
„ Metal
„ Polysilicon
„ Diffusion
„ Capacitors
„ Metal-Silicon
„ Metal-Polysilicon
„ Polysilicon-Silicon
„ Gate Oxide
„ Field Oxide
„ Diode
„ MOSFET
„ Bipolar Junction Transistor (low quality)
Spring 2005 3.155J/6.152J – Lecture 2 – Slide 33

Our Labs
„ Lab Session 1
„ 1.1 Lab Safety and Cleanroom Orientation
„ 1.2 RCA (ICL RCA)
„ 1.3 Gate Oxidation
„ Thermco Atmospheric Furnace (5D-FieldOx)
„ Dry Oxidation, 1000°C 60 minutes
„ 1.4 Doped Polysilicon Deposition
„ Thermco LPCVD (6A-Poly)
„ Lab Session 2
„ 2.1 Measure oxide thickness (UV1280)
„ 2.2 HMDS, Photoresist Application, Postbake (SSI coater track)
„ 2.3 Dry etch backside polysilicon (LAM490B)
„ 2.4 Etch backside oxide in BOE until de-wet (OxEtch-BOE)
„ 2.5 Strip frontisde resist with Matrix System One Stripper (Asher)
„ Lab Session 3
„ 3.1 HMDS, Photoresist Application, Pre-bake (SSI coater track)
„ 3.2 Exposure, Development, and Inspection (I-Stepper)
„ 3.3 Dry-etch polysilicon (LAM490B)
„ 3.4 Strip photoresist with Matrix System One Stripper (Asher)
„ 3.5 Visual Inspection.
„ 3.6 HF dip for 30 s (ICL Pre-Metal)
„ 3.7 Device characterization: MOS Capacitor
„ Determine oxide capacitance.
„ Determine bulk dopant concentration.
„ Determine fixed interface charge.
„ 3.8 Sheet resistance measurement: Van der Pauw structure

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 34

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 Lab Session 1
„ 1.1 Lab Safety and Cleanroom Orientation
„ 1.2 RCA (ICL RCA)
„ 1.3 Gate Oxidation
„ Thermco Atmospheric Furnace (5D-FieldOx)
„ Dry Oxidation, 1000°C 60 minutes
„ 1.4 Doped Polysilicon Deposition
„ Thermco LPCVD (6A-Poly)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 35

Lab Session 2
„ 2.1 Measure oxide thickness (UV1280)
„ 2.2 HMDS, Photoresist Application, Postbake
(SSI coater track)
„ 2.3 Dry etch backside polysilicon (LAM490B)
„ 2.4 Etch backside oxide in BOE until de-wet
(OxEtch-BOE)
„ 2.5 Strip frontisde resist with Matrix System
One Stripper (Asher)

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 36

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 Lab Session 3
„ 3.1 HMDS, Photoresist Application, Pre-bake
(SSI coater track)
„ 3.2 Exposure, Development, and Inspection
(I-Stepper)
„ 3.3 Dry-etch polysilicon (LAM490B)
„ 3.4 Strip photoresist with Matrix System One
Stripper (Asher)
„ 3.5 Visual Inspection

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 37

Lab Session 3 (con’t.)

„ 3.6 HF dip for 30 s (ICL Pre-Metal)
„ 3.7 Device characterization: MOS Capacitor
„ Determine oxide capacitance.
„ Determine bulk dopant concentration.
„ Determine fixed interface charge.
„ 3.8 Sheet resistance measurement: Van der
Pauw structure

Spring 2005 3.155J/6.152J – Lecture 2 – Slide 38

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